公开(公告)号：US06542379B1

公开(公告)日：2003-04-01

申请号：US09353992

申请日：1999-07-15

Applicant: John M. Lauffer ,  David J. Russell

Inventor： John M. Lauffer ,  David J. Russell

IPC: H05K116

CPC classification number: H01F41/041 ,  H01F17/0033 ,  H05K1/095 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/0023 ,  H05K3/386 ,  H05K3/4069 ,  H05K3/4644 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/0209 ,  H05K2201/0367 ,  H05K2201/086 ,  H05K2201/09563 ,  H05K2201/097 ,  H05K2201/09881 ,  H05K2203/0568 ,  H05K2203/1453 ,  H05K2203/1461 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T428/24917 ,  Y10T428/2495 ,  Y10T428/24967 ,  Y10T428/24975

Abstract: Passive electrical components such as capacitors, resistors, inductors, transformers, filters and resonators are integrated in to electrical circuits utilizing a process which maximizes the utilization of the planar surfaces of the substrates for high density placement of active components such as logic or memory integrated circuits. The passive components are integrated into a conventional circuit board utilizing a photoimageable dielectric material. The dielectric is photoimaged and etched to provide one or more recesses or openings for the passive devices, and photovias interconnecting the inputs and outputs of the integrated circuit board. The electronic structure comprising at least one of the passive devices integrated into a photoimaged dielectric is described as well as the method of manufacturing the same.

Abstract translation: 电容器，电阻器，电感器，变压器，滤波器和谐振器等被动电气元件集成到电路中，利用最大限度地利用衬底的平面来进行高密度放置有源元件例如逻辑或存储器集成电路 。 将无源部件集成到利用可光成像的电介质材料的常规电路板中。 电介质被光刻和蚀刻以提供用于无源器件的一个或多个凹部或开口，以及互连集成电路板的输入和输出的光电隔离。 描述了包括集成到光电介质中的无源器件中的至少一个的电子结构及其制造方法。

公开(公告)号：US06541848B2

公开(公告)日：2003-04-01

申请号：US09170260

申请日：1998-10-13

Applicant: Toshimi Kawahara ,  Mamoru Suwa ,  Masanori Onodera ,  Syuichi Monma ,  Shinya Nakaseko ,  Takashi Hozumi

Inventor： Toshimi Kawahara ,  Mamoru Suwa ,  Masanori Onodera ,  Syuichi Monma ,  Shinya Nakaseko ,  Takashi Hozumi

IPC: H01L2348

CPC classification number: H01L21/568 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/3107 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/05554 ,  H01L2224/1134 ,  H01L2224/1308 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/4848 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85986 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18165 ,  H01L2924/20752 ,  H05K3/3426 ,  H05K3/3436 ,  H05K2201/0367 ,  H05K2201/10689 ,  Y02P70/613 ,  H01L2224/85186 ,  H01L2224/48465 ,  H01L2924/00 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/4554

Abstract: A semiconductor device includes a semiconductor chip, a resin package for sealing said semiconductor chip, metal layers provided on a mounting-side surface of said resin package in an exposed manner and connecting members for electrically connecting electrode pads provided on the semiconductor chip and the metal layers. The metal layers are provided with stud bumps on the mounting side, the stud bumps serving as external connection terminals.

Abstract translation: 半导体器件包括半导体芯片，用于密封所述半导体芯片的树脂封装，以暴露方式设置在所述树脂封装的安装侧表面上的金属层和用于电连接设置在半导体芯片上的电极焊盘和金属的连接构件 层。 金属层在安装侧设置有螺柱凸块，柱凸起用作外部连接端子。

公开(公告)号：US06535393B2

公开(公告)日：2003-03-18

申请号：US09205796

申请日：1998-12-04

Applicant: Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  J. Michael Brooks ,  Eugene H. Cloud

Inventor： Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  J. Michael Brooks ,  Eugene H. Cloud

IPC: H05K114

CPC classification number: H05K3/4007 ,  H01L23/4951 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H05K1/0271 ,  H05K1/095 ,  H05K3/321 ,  H05K3/325 ,  H05K3/326 ,  H05K2201/0133 ,  H05K2201/0314 ,  H05K2201/0367 ,  H05K2201/09909 ,  H05K2201/10454 ,  H05K2201/10696 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A device comprising a circuit, a lead having a first end connected to the circuit and having a second end, and a deformable structure connected to the second end of the lead. The invention may be embodied on a circuit board, so that the circuit board includes a substrate and a deformable structure connected to said substrate. Also disclosed is a device comprising a circuit having an active side and a non-active side, a package enclosing the active side of the circuit and not enclosing a portion of the non-active side of the circuit, and a lead having a first end connected to the active side of the circuit via a lead-over-chip connection, and having a second end extending from the package. Also disclosed is a device comprising a circuit and a lead formed from a flexible conductor, with the lead having a first end connected to the circuit.

Abstract translation: 一种装置，包括电路，具有连接到所述电路并具有第二端的第一端的引线和连接到所述引线的第二端的可变形结构。 本发明可以实现在电路板上，使得电路板包括基板和连接到所述基板的可变形结构。 还公开了一种包括具有有源侧和非有源侧的电路的装置，封装电路的有源侧的封装件，并且不包围电路的非有源侧的一部分，以及具有第一端 通过芯片上引线连接到电路的有源侧，并具有从封装延伸的第二端。 还公开了一种包括由柔性导体形成的电路和引线的器件，其中引线具有连接到电路的第一端。

公开(公告)号：US06527563B2

公开(公告)日：2003-03-04

申请号：US09912111

申请日：2001-07-23

Applicant: Gary A. Clayton

Inventor： Gary A. Clayton

IPC: H01R1200

CPC classification number: H01R13/2414 ,  G01R1/0466 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/027 ,  H05K3/4007 ,  H05K3/423 ,  H05K3/427 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/0979 ,  H05K2201/10378 ,  H05K2203/0369 ,  H05K2203/0554 ,  H05K2203/1572 ,  H01L2924/00

Abstract: A grid interposer for testing electrical circuits and a method of making a grid interposer. The grid interposer includes upper and lower conductive surfaces sandwiched on either side of an insulating later, connected to each other by a plurality of vias filled with conductive material. The conductive surfaces are flat topped, and incised with a grid of flat topped peaks which are small enough to cut through oxidation of electrical contacts, and ensure good electrical contact with a variety of electrode shapes.

公开(公告)号：US20030031000A1

公开(公告)日：2003-02-13

申请号：US10237579

申请日：2002-09-09

Inventor： Salman Akram ,  Warren M. Farnworth ,  Alan G. Wood ,  J. Michael Brooks ,  Eugene H. Cloud

IPC: H05K007/02 ,  H05K007/06 ,  H05K007/08 ,  H05K007/10

CPC classification number: H05K3/4007 ,  H01L23/4951 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H05K1/0271 ,  H05K1/095 ,  H05K3/321 ,  H05K3/325 ,  H05K3/326 ,  H05K2201/0133 ,  H05K2201/0314 ,  H05K2201/0367 ,  H05K2201/09909 ,  H05K2201/10454 ,  H05K2201/10696 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Disclosed is a device comprising a circuit having an active side and a non-active side, a package enclosing the active side of the circuit and not enclosing a portion of the non-active side of the circuit, and a lead having a first end connected to the active side of the circuit via a lead-over-chip connection, and having a second end extending from the package. Also disclosed is a device comprising a circuit and a lead formed from a flexible conductor, with the lead having a first end connected to the circuit.

Abstract translation: 公开了一种包括具有有源侧和非有源侧的电路的器件，封装电路的有源侧的封装，并且不包围电路的非有源侧的一部分，以及引线，其具有连接到第一端 经由引线芯片连接到电路的有源侧，并且具有从封装延伸的第二端。 还公开了一种包括由柔性导体形成的电路和引线的器件，其中引线具有连接到电路的第一端。

公开(公告)号：US06495397B2

公开(公告)日：2002-12-17

申请号：US09821331

申请日：2001-03-28

Applicant: Jiro Kubota ,  Kenji Takahashi

Inventor： Jiro Kubota ,  Kenji Takahashi

IPC: H01L2144

CPC classification number: H01L24/81 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/1607 ,  H01L2224/75252 ,  H01L2224/81193 ,  H01L2224/81204 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15312 ,  H05K3/24 ,  H05K3/244 ,  H05K3/3436 ,  H05K3/3494 ,  H05K2201/0367 ,  H05K2201/10674 ,  H05K2203/0195 ,  Y02P70/613 ,  Y10T29/49144 ,  H01L2924/00

Abstract: A flip chip method of joining a chip and a substrate is described. A thermo-compression bonder is utilized to align the chip and substrate and apply a contact force to hold solder bumps on the substrate against metal bumps on the chip. The chip is rapidly heated from its non-native side by a pulse heater in the head of the bonder until the re-flow flow temperature of the solder bumps is reached. Proximate with reaching the re-flow temperature at the solder bumps, the contact force is released. The solder is held above its re-flow temperature for several seconds to facilitate wetting of the substrate's metal protrusions and joining. Metal caps comprised of a noble metal such as palladium is applied to the surface of the metal bumps to prevent the metal bumps (which generally comprise a highly-conductive and highly-reactive metal such as copper) from oxidizing in the elevated temperatures just prior to and during the re-flow operation.

Abstract translation: 描述了一种连接芯片和基板的倒装芯片方法。 使用热压接合器来对准芯片和衬底并施加接触力以将衬底上的焊料凸块保持在芯片上的金属凸块上。 芯片通过焊接机头部的脉冲加热器从其非本机侧快速加热，直到达到焊料凸块的再流动温度。 近似达到焊料凸点处的回流温度时，接触力被释放。 焊料被保持在其再流动温度以上几秒钟以便于衬底的金属突起和接合的润湿。 由贵金属如钯构成的金属盖被施加到金属凸块的表面，以防止金属凸块（其通常包括高导电性和高反应性金属如铜）在刚好在高温下的高温下氧化 并在重新流动操作期间。

公开(公告)号：US20020175421A1

公开(公告)日：2002-11-28

申请号：US10151416

申请日：2002-05-20

Inventor： Naoto Kimura

IPC: H01L023/48 ,  H01L023/52 ,  H01L029/40

CPC classification number: H01L23/49833 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/05553 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/3025 ,  H05K1/021 ,  H05K1/144 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09036 ,  H05K2201/09072 ,  H05K2201/10515 ,  H05K2201/1056 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: The semiconductor device according to the present invention is equipped with a plurality of electronic circuits including at least one semiconductor integrated circuit chip, and a plurality of intermediate substrates interposed between the electronic components and a package and mounting the electronic components directly on its one major face, where each of the electronic component has on the one major face at least a plurality of first electrodes connected to the electronic components, a plurality of second electrodes for external connection, and internal connection electrodes for connecting between the electronic components including the connection between the first electrodes and the second electrodes that are mutually corresponding.

Abstract translation: 根据本发明的半导体器件配备有多个电子电路，其包括至少一个半导体集成电路芯片和插入在电子部件和封装之间的多个中间基板，并将电子部件直接安装在其一个主面上 ，其中每个电子部件在一个主面上具有连接到电子部件的至少多个第一电极，用于外部连接的多个第二电极和用于连接电子部件之间的连接的内部连接电极， 第一电极和第二电极相互对应。

公开(公告)号：US20020160540A1

公开(公告)日：2002-10-31

申请号：US10109135

申请日：2002-03-28

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hiroaki Kaida

IPC: H01L021/00

CPC classification number: H03H9/0509 ,  H01L41/053 ,  H03H9/1014 ,  H05K1/111 ,  H05K3/321 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/10636 ,  Y02P70/611

Abstract: An electronic component includes a case substrate. Substrate electrodes having a substantially spherical outer surface are disposed on at least a first principal surface of the case substrate. A piezoelectric resonator is mounted on the case substrate such that the piezoelectric resonator is bonded to the outer surfaces of the substrate electrodes by a conductive bonding material and is supported by the substrate electrodes in a point-contact manner. Also, the formula, Lknull2We

Abstract translation: 电子部件包括壳体基板。 具有基本上球形的外表面的基板电极设置在壳体基板的至少第一主表面上。 压电谐振器安装在壳体基板上，使得压电谐振器通过导电接合材料结合到基板电极的外表面，并且以点接触的方式被基板电极支撑。 此外，满足式Lk-2We

公开(公告)号：US06462414B1

公开(公告)日：2002-10-08

申请号：US09517799

申请日：2000-03-02

Applicant: Sidney Larry Anderson

Inventor： Sidney Larry Anderson

IPC: H01L2348

CPC classification number: H01L24/32 ,  H01L21/4853 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13023 ,  H01L2224/16237 ,  H01L2224/274 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/8547 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K1/112 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09745 ,  H05K2201/10734 ,  H05K2203/041 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49204 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2924/0133 ,  H01L2924/01049 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/13111 ,  H01L2224/05552 ,  H01L2224/45015 ,  H01L2224/45099

Abstract: An integrated circuit package is provided with a ball landing area having a conductive structure for interlocking a conductive ball to the ball pad. The conductive structure improves the attachment strength between an integrated circuit package and an printed circuit board. In an exemplary embodiment, the locking structure is a conductive material added to the surface of the ball pad to provide a nonplanar interface, such as a dome or a step, which interlocks the conductive ball to the ball pad. The improved package construction increases the area of contact, moves the shear plane to a higher and larger portion on the conductive ball, and/or prevents a crack from propagating along a flat plane across the ball joint. This package construction maintains the small size of the ball land areas and the package, increases the life of the integrated circuit package, while offsetting the problem of package warpage.

Abstract translation: 集成电路封装设置有具有用于将导电球与球垫互锁的导电结构的球着陆区域。 导电结构提高了集成电路封装和印刷电路板之间的附着强度。 在示例性实施例中，锁定结构是添加到球垫表面的导电材料，以提供将导电球与球垫互锁的非平面界面，例如圆顶或台阶。 改进的包装结构增加了接触面积，将剪切平面移动到导电球上的更大和更大的部分，和/或防止裂缝沿着穿过球窝接头的平面传播。 该封装结构保持了球形区域和封装的小尺寸，增加了集成电路封装的使用寿命，同时抵消了封装翘曲的问题。

公开(公告)号：US20020104873A1

公开(公告)日：2002-08-08

申请号：US09778658

申请日：2001-02-06

Inventor： Michael G. Lee ,  Connie M. Wong ,  Wen-Chou Vincent Wang

IPC: B23K031/02

CPC classification number: H01L24/02 ,  H01L21/563 ,  H01L23/49816 ,  H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/1601 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K3/3436 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2203/043 ,  H05K2203/0475 ,  H05K2203/111 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method for electrically coupling electrode pads comprising forming a reflowed solder bump on a first electrode pad supported by a first substrate. The reflowed solder bump includes a solder material having a solder melting temperature. The method further includes forming a second electrode pad on a second substrate. The second electrode pad has an electrode structure defined by at least one converging continuous arcuate surface terminating in an apex and having an electrode material whose melting temperature is greater than the solder melting temperature of the solder material. The solder bump is heated to reflow or to soften the solder material, and subsequently the apex of the second electrode pad is pressed or inserted into the heated solder bump to couple the first electrode pad to the second electrode pad. A method for solder bump reflow comprising pressing or inserting the apex of an electrode into a reflowed solder bumps, and then reflowing solder material of the reflowed solder bump. A semiconductor assembly including a semiconductor device having an electrode pad coupled to a semiconductor substrate and comprising an electrode structure defined by a pair of arcuate surfaces generally tangentially terminating in an apex.

Abstract translation: 一种用于电耦合电极焊盘的方法，包括在由第一衬底支撑的第一电极焊盘上形成回流的焊料凸块。 回流的焊料凸块包括具有焊料熔化温度的焊料材料。 该方法还包括在第二基板上形成第二电极焊盘。 第二电极焊盘具有由终止于顶点的至少一个会聚的连续弧形表面限定的电极结构，并且具有熔融温度大于焊料材料的焊料熔化温度的电极材料。 焊料凸块被加热以回流或软化焊料材料，随后将第二电极焊盘的顶点按压或插入加热的焊料凸块中以将第一电极焊盘耦合到第二电极焊盘。 一种用于焊料回流焊的方法，包括将电极的顶点压入或插入回流的焊料凸块中，然后回流回流的焊料凸块的焊料材料。 一种半导体组件，包括具有耦合到半导体衬底的电极焊盘的半导体器件，并且包括由通常以尖端终止的一对弓形表面限定的电极结构。