中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

218 records (took 0.018 seconds)

    COMPLEMENTARY MIRROR IMAGE EMBEDDED PLANAR RESISTOR ARCHITECTURE
    21.
    发明申请
    COMPLEMENTARY MIRROR IMAGE EMBEDDED PLANAR RESISTOR ARCHITECTURE 有权
    补充镜像图像嵌入式平面电阻结构

    公开(公告)号：US20080093113A1

    公开(公告)日：2008-04-24

    申请号：US11861297

    申请日：2007-09-26

    Applicant: Uei-Ming Jow ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Ying-Jiunn Lai

    Inventor： Uei-Ming Jow ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Ying-Jiunn Lai

    IPC: H05K1/16

    CPC classification number: H05K1/167 ,  H05K1/0224 ,  H05K1/025 ,  H05K1/0298 ,  H05K2201/0792 ,  H05K2201/09681 ,  H05K2201/0969

    Abstract: A complementary mirror image embedded planar resistor architecture is provided. In the architecture, a complementary hollow structure is formed on a ground plane or an electrode plane to minimize the parasitic resistance, so as to efficiently enhance the application frequency. In addition, in some cases, some signal transmission lines pass through the position below the embedded planar resistor, and if there is no shield at all, serious interference or cross talk phenomenon occurs. Therefore, the complementary hollow structure of the ground plane, the electrode plane, or a power layer adjacent to the embedded planar resistor is designed to be a mesh structure, so as to reduce the interference or cross talk phenomenon. In this manner, the whole resistor structure has preferable high frequency electrical characteristic in the circuit.

    Abstract translation: 提供了一种互补镜像嵌入式平面电阻架构。 在该结构中，在接地平面或电极平面上形成互补的中空结构以最小化寄生电阻，从而有效地提高施加频率。 此外，在某些情况下，一些信号传输线通过嵌入式平面电阻器下方的位置，如果根本没有屏蔽，则会发生严重的干扰或串扰现象。 因此，将接地平面，电极平面或与嵌入式平面电阻器相邻的功率层的互补空心结构设计为网格结构，以减少干扰或串扰现象。 以这种方式，整个电阻器结构在电路中具有优选的高频电特性。

    Apparatus and method for a printed circuit board that reduces capacitance loading of through-holes
    22.
    发明申请
    Apparatus and method for a printed circuit board that reduces capacitance loading of through-holes 审中-公开
    一种降低通孔电容负载的印刷电路板的装置和方法

    公开(公告)号：US20080087460A1

    公开(公告)日：2008-04-17

    申请号：US11582740

    申请日：2006-10-17

    Applicant: Pat Fung

    Inventor： Pat Fung

    IPC: H05K1/11 ,  H01R12/04

    CPC classification number: H05K1/0251 ,  H05K1/115 ,  H05K3/308 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/0792 ,  H05K2201/09627 ,  H05K2201/10189 ,  H05K2201/1059

    Abstract: An apparatus and method for a printed circuit board (PCB) for reducing capacitance loading of through-holes. The PCB includes a first electrically conductive via for connecting to the PCB a pin from a connector through a top layer of the PCB. The PCB comprises multiple layers that are electrically isolated from the first electrically conductive via. In addition, the connector provides an electrical signal through the pin that is electrically conductive. The PCB includes a second electrically conductive via that is proximate to the first electrically conductive via. The second electrically conductive via is electrically coupled to one of the multiple layers of the PCB. A trace electrically couples the first electrically conductive via to the second electrically conductive via on a bottom layer of the PCB. The trace allows the pin to be electrically coupled to one of the multiple layers of the PCB.

    Abstract translation: 一种用于减小通孔电容负载的印刷电路板（PCB）的装置和方法。 PCB包括用于通过PCB的顶层从连接器连接到PCB的引脚的第一导电通孔。 PCB包括与第一导电通孔电隔离的多个层。 此外，连接器通过引脚提供导电的电信号。 PCB包括靠近第一导电通孔的第二导电通孔。 第二导电通孔电连接到PCB的多个层中的一个。 迹线将第一导电通孔电连接到PCB的底层上的第二导电通孔。 迹线允许引脚电耦合到PCB的多个层中的一个。

    Microelectronic device with mixed dielectric
    24.
    发明申请
    Microelectronic device with mixed dielectric 有权
    具有混合电介质的微电子器件

    公开(公告)号：US20070169959A1

    公开(公告)日：2007-07-26

    申请号：US11338402

    申请日：2006-01-24

    Applicant: Hanyi Ding ,  Brian Welch

    Inventor： Hanyi Ding ,  Brian Welch

    IPC: H05K1/16

    CPC classification number: H05K1/024 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K1/115 ,  H05K2201/0187 ,  H05K2201/0792 ,  H05K2201/09581 ,  H01L2924/00

    Abstract: A microelectronic device and method of making the microelectronic device is provided. A dielectric substrate having first and second surfaces is provided. A first component, located in the dielectric substrate between the first and second surfaces of the dielectric substrate is formed. The first component includes a first interface and a second interface. A second component located in the dielectric substrate and spaced relative to the first component is formed, and a first low permittivity material is formed having a predetermined thickness and a first and second surface, the first surface of the low permittivity material is adjacent to or in contact with a first portion of the first interface of the first component. The first low permittivity material substantially reduces capacitive parasitics of the first component, resulting in a substantially higher characteristic impedance of the first component during operation of the microelectronic device.

    Abstract translation: 提供微电子器件和制造微电子器件的方法。 提供具有第一和第二表面的电介质基片。 形成位于电介质基板之间的电介质基板的第一和第二表面之间的第一部件。 第一组件包括第一接口和第二接口。 形成位于电介质基板中并相对于第一部件间隔开的第二部件，并且形成具有预定厚度的第一低介电常数材料和第一和第二表面，低介电常数材料的第一表面邻近或位于 与第一部件的第一界面的第一部分接触。 第一低介电常数材料显着地减小了第一部件的电容寄生效应，导致在微电子器件工作期间第一部件的特征阻抗基本上更高。

    Apparatus and method of via-stub resonance extinction
    25.
    发明申请
    Apparatus and method of via-stub resonance extinction 审中-公开
    通孔共振消光的装置和方法

    公开(公告)号：US20070152771A1

    公开(公告)日：2007-07-05

    申请号：US11325794

    申请日：2006-01-05

    Applicant: Lei Shan ,  Jeannine Trewhella

    Inventor： Lei Shan ,  Jeannine Trewhella

    IPC: H01P5/02

    CPC classification number: H05K1/023 ,  H05K1/0246 ,  H05K1/112 ,  H05K3/429 ,  H05K2201/0792 ,  H05K2201/10022 ,  H05K2201/10545 ,  H05K2201/10636 ,  H05K2201/10734 ,  Y02P70/611

    Abstract: An apparatus includes a multi-layer printed circuit board having a first through-hole via for a signal connection and a second through hole via for power/ground connections. The printed circuit includes a transmission line connected to at least one through-hole via. A resistor is connected between the first and second through-hole vias to eliminate a resonance notch and achieve a flat frequency response for insertion loss.

    Abstract translation: 一种装置包括具有用于信号连接的第一通孔通孔和用于电力/接地连接的第二通孔通孔的多层印刷电路板。 印刷电路包括连接到至少一个通孔通孔的传输线。 电阻器连接在第一通孔和第二通孔之间以消除谐振陷波并实现用于插入损耗的平坦频率响应。

    Capacitor and electronic apparatus thereof
    26.
    发明申请
    Capacitor and electronic apparatus thereof 审中-公开
    电容器及其电子设备

    公开(公告)号：US20070076350A1

    公开(公告)日：2007-04-05

    申请号：US11529666

    申请日：2006-09-27

    Applicant: Masashi Watanabe ,  Toshiki Ooka ,  Takahiro Sakaguchi

    Inventor： Masashi Watanabe ,  Toshiki Ooka ,  Takahiro Sakaguchi

    IPC: H01G9/10 ,  H05K5/03 ,  H01G4/228

    CPC classification number: H05K1/0243 ,  H01G2/065 ,  H01G9/008 ,  H01G9/10 ,  H05K1/0231 ,  H05K1/112 ,  H05K2201/0792 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09663 ,  H05K2201/10015

    Abstract: According to one embodiment, a capacitor includes a first anode terminal exposed from an end portion of a first inner electrode coupled to one side of a dielectric in a predetermined direction, a second anode terminal exposed from the other end portion of the first electrode in the predetermined direction, a first cathode terminal exposed from a predetermined portion of a second inner electrode that is connected to the other side of the dielectric and provided independently of the first electrode, to insides of the exposed portions of the first and second anode terminals, in the predetermined direction, and a second cathode terminal exposed from a part of the predetermined portion of the second electrode which is close to the second anode terminal, to the insides of the exposed portions of the first and second anode terminals, in the predetermined direction, at a predetermined interval from the first cathode terminal.

    Abstract translation: 根据一个实施例，电容器包括从第一内部电极的端部暴露的第一阳极端子，第一阳极端子沿预定方向耦合到电介质的一侧，第二阳极端子从第一电极的另一端部露出， 从第二内部电极的预定部分暴露的第一阴极端子，其连接到电介质的另一侧并且独立于第一电极而设置在第一和第二阳极端子的暴露部分的内部， 所述预定方向和从所述第二电极的接近所述第二阳极端子的所述预定部分的一部分露出的第二阴极端子沿所述预定方向延伸到所述第一阳极端子和所述第二阳极端子的暴露部分的内部， 从第一阴极端子预定间隔。

    Module having integrated circuit packages coupled to multiple sides with package types selected based on inductance of leads to couple the module to another component
    30.
    发明授权
    Module having integrated circuit packages coupled to multiple sides with package types selected based on inductance of leads to couple the module to another component 失效
    具有耦合到多个侧面的集成电路封装的模块，其具有基于引线的电感选择的封装类型，以将模块耦合到另一个部件

    公开(公告)号：US06507496B2

    公开(公告)日：2003-01-14

    申请号：US09872122

    申请日：2001-05-31

    Applicant: Paul S. Levy ,  David Frame

    Inventor： Paul S. Levy ,  David Frame

    IPC: H05K706

    CPC classification number: H05K1/141 ,  H05K1/181 ,  H05K3/3447 ,  H05K2201/0792 ,  H05K2201/1034 ,  H05K2201/10484 ,  H05K2201/10689 ,  H05K2201/10734 ,  H05K2203/1572

    Abstract: A dual-sided circuit board module designed for an operating position that is not perpendicular to a system motherboard will be coupled to the motherboard by leads having at least two different lengths. Because leads of differing lengths have differing associated inductance, the operating characteristics of the leads and therefore the devices coupled to the leads will differ. In order to improve the operating characteristics of the module, integrated circuit packages are selected based on the inductive (and possibly other) qualities of the leads to which the respective packages are coupled. In one embodiment, leads having a larger inductance are coupled to integrated circuit (IC) packages having a smaller inductance and vice versa, which allows the inductive characteristics of the various components of the module to have more closely matching inductive characteristics than would otherwise be possible.

    Abstract translation: 设计用于不垂直于系统主板的操作位置的双面电路板模块将通过具有至少两个不同长度的引线耦合到母板。 因为不同长度的引线具有不同的相关电感，所以引线的工作特性以及耦合到引线的器件的操作特性将不同。 为了提高模块的工作特性，集成电路封装是基于各个封装所耦合的引线的电感（也可能是其它）的质量来选择的。 在一个实施例中，具有较大电感的引线被耦合到具有较小电感的反馈的集成电路（IC）封装，这允许模块的各种部件的电感特性具有比否则可能更紧密匹配的感应特性 。

Patent Agency Ranking