公开(公告)号：US08119928B2

公开(公告)日：2012-02-21

申请号：US12343844

申请日：2008-12-24

Applicant: Isao Matsui

Inventor： Isao Matsui

IPC: H05K1/16 ,  H05K1/00 ,  H05K1/03

CPC classification number: H01R12/721 ,  H05K1/0231 ,  H05K1/184 ,  H05K3/0052 ,  H05K3/403 ,  H05K2201/09181 ,  H05K2201/0919 ,  H05K2201/10189 ,  H05K2201/10446 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/49117

Abstract: In a multi-layered wiring substrate according to an exemplary aspect of the present invention, a conductor formed in an edge face area functions as a pad for mounting a connector.

Abstract translation: 在根据本发明的示例性方面的多层布线基板中，形成在边缘区域中的导体用作用于安装连接器的垫。

公开(公告)号：US08044861B2

公开(公告)日：2011-10-25

申请号：US12164756

申请日：2008-06-30

Applicant: Anders P. Pedersen ,  Daniel A. Robison ,  Alan Mast

Inventor： Anders P. Pedersen ,  Daniel A. Robison ,  Alan Mast

IPC: H01Q1/38

CPC classification number: H05K3/366 ,  H01Q21/0087 ,  H01Q21/061 ,  H05K1/0219 ,  H05K3/403 ,  H05K2201/0919 ,  Y10T29/49016 ,  Y10T29/49018

Abstract: An electronic device may include a multilayer circuit board having opposing major surfaces and edge surfaces extending between the opposing major surfaces, wireless processing circuitry on at least one of the opposing major surfaces, and an antenna element on at least one of the edge surfaces. The multilayer circuit board may include a conductive trace coupling the antenna element to the wireless processing circuitry.

Abstract translation: 电子设备可以包括多层电路板，其具有相对的主表面和在相对的主表面之间延伸的边缘表面，在相对的主表面中的至少一个上的无线处理电路以及至少一个边缘表面上的天线元件。 多层电路板可以包括将天线元件耦合到无线处理电路的导电迹线。

公开(公告)号：US20110156225A1

公开(公告)日：2011-06-30

申请号：US13062565

申请日：2009-07-31

Applicant: Hiroshi Hozoji ,  Toshiaki Morita ,  Yusuke Yasuda ,  Chiko Yorita ,  Yuji Shirai

Inventor： Hiroshi Hozoji ,  Toshiaki Morita ,  Yusuke Yasuda ,  Chiko Yorita ,  Yuji Shirai

IPC: H01L23/552 ,  H01L21/56

CPC classification number: H01L23/3121 ,  H01L21/561 ,  H01L23/3677 ,  H01L23/552 ,  H01L23/66 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/165 ,  H01L2221/68331 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/45599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/0206 ,  H05K1/0218 ,  H05K3/284 ,  H05K2201/0715 ,  H05K2201/0919 ,  H05K2203/1131 ,  H05K2203/1316 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor device achieving both electromagnetic wave shielding property and reliability in a heating process upon mounting electronic components. In the semiconductor device, mount devices 5 and 6 mounted on a main surface of a circuit board 1 are provided, the mount devices 5 and 6 are electrically connected to a wiring pattern 4 at the main surface of the circuit board 1, a sealant 7 of an insulating resin is formed to seal the mount devices 5 and 6, metal particles are applied to a surface of the sealant 7, and the metal particles applied are sintered, thereby forming an electromagnetic shielding layer 2, and electrically connecting the electromagnetic shielding layer 2 to a ground pattern 3 of the circuit board 1.

Abstract translation: 一种在安装电子元件时实现电加热过程中的电磁波屏蔽性和可靠性的半导体器件。 在半导体装置中，设置安装在电路基板1的主表面上的安装装置5和6，安装装置5和6在电路板1的主表面电连接到布线图案4，密封剂7 形成绝缘树脂以密封安装装置5和6，将金属颗粒施加到密封剂7的表面，并且将所施加的金属颗粒烧结，从而形成电磁屏蔽层2，并将电磁屏蔽层 2到电路板1的接地图案3。

公开(公告)号：US20100207264A1

公开(公告)日：2010-08-19

申请号：US12702804

申请日：2010-02-09

Applicant: Masahiro ONO

Inventor： Masahiro ONO

IPC: H01L23/488

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L23/3135 ,  H01L23/3737 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/552 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19105 ,  H05K1/0218 ,  H05K1/095 ,  H05K3/284 ,  H05K2201/0919 ,  H05K2203/1316 ,  H01L2224/81

Abstract: A module substrate has an interconnection electrode that is exposed at a side end face thereof. A semiconductor component including an IC chip is mounted on the module substrate. A molded part comprising a resin is formed so as to cover at least a part of the semiconductor component. A coating with higher heat conductivity than the molded part is formed on the surface of the molded part by applying a paste made of material with higher heat conductivity than the molded part. This improves heat dissipation. The coating can be formed such that it extends to the surface of the main substrate on which the module substrate with the semiconductor component is mounted and comes into contact with the interconnection electrode on the surface of the main substrate. This further improves heat dissipation.

Abstract translation: 模块基板具有在其侧端面露出的互连电极。 包括IC芯片的半导体部件安装在模块基板上。 形成包含树脂的成型部，以覆盖半导体部件的至少一部分。 通过施加由比模制部件更高的导热性的材料制成的糊料，在模制部件的表面上形成具有比模制部件更高导热性的涂层。 这改善了散热。 涂层可以形成为使得其延伸到其上安装有半导体部件的模块基板的主基板的表面，并且与主基板的表面上的互连电极接触。 这进一步改善了散热。

公开(公告)号：US20100012357A1

公开(公告)日：2010-01-21

申请号：US12548933

申请日：2009-08-27

Applicant: Alan E. Wang ,  Kevin C. Olson

Inventor： Alan E. Wang ,  Kevin C. Olson

IPC: H05K1/03 ,  H05K1/11

CPC classification number: H05K3/445 ,  H01L2224/16225 ,  H05K1/056 ,  H05K3/002 ,  H05K3/0052 ,  H05K3/403 ,  H05K3/426 ,  H05K3/44 ,  H05K3/4614 ,  H05K3/4641 ,  H05K3/4644 ,  H05K2201/0129 ,  H05K2201/0166 ,  H05K2201/0397 ,  H05K2201/0909 ,  H05K2201/09154 ,  H05K2201/09181 ,  H05K2201/0919 ,  H05K2201/09554 ,  H05K2201/09645 ,  H05K2201/09827 ,  H05K2203/1105 ,  H05K2203/135 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A circuit board includes an electrically conductive sheet having an insulative coating surrounding the conductive sheet, with a surface of the insulative coating around an edge of the conductive sheet having an arcuate or rounded shape. At least one electrical conductor is conformally deposited on at least the rounded insulative coating around the edge of the conductive sheet and defined via photolithographic and metallization techniques. Each electrical conductor on the insulative coating thereon around the edge of the conductive sheet conforms to the arcuate or rounded shape of the insulative coating and, therefore, has an arcuate or rounded shape.

Abstract translation: 电路板包括具有围绕导电片的绝缘涂层的导电片，绝缘涂层的表面围绕导电片的边缘具有弓形或圆形形状。 至少一个电导体被共形沉积在导电片的边缘周围的至少圆形绝缘涂层上，并通过光刻和金属化技术限定。 导电片边缘周围的绝缘涂层上的每个电导体符合绝缘涂层的弧形或圆形形状，因此具有弓形或圆形形状。

公开(公告)号：US07589405B2

公开(公告)日：2009-09-15

申请号：US11286058

申请日：2005-11-23

Applicant: Min-Young Son ,  Woo-Dong Lee

Inventor： Min-Young Son ,  Woo-Dong Lee

IPC: H01L23/02

CPC classification number: H01L23/5388 ,  H01L23/3121 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0655 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19105 ,  H05K3/284 ,  H05K3/3452 ,  H05K2201/0919 ,  H05K2201/0989 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Provided are a memory card and a method of fabricating the memory card. The memory card includes: a printed circuit board including conductive wires exposed to at least a portion of an outer wall of the printed circuit board; at least one electronic device mounted on the printed circuit board; and a molding part sealing the at least one electronic device on the printed circuit board and the conductive wires exposed to the outer wall of the printed circuit board, and simultaneously exposing at least a portion of the outer wall of the printed circuit board.

Abstract translation: 提供了存储卡和制造存储卡的方法。 存储卡包括：印刷电路板，包括暴露于印刷电路板的外壁的至少一部分的导线; 安装在印刷电路板上的至少一个电子装置; 以及密封印刷电路板上的至少一个电子器件和暴露于印刷电路板的外壁的导电线的成型部件，并且同时暴露印刷电路板的外壁的至少一部分。

公开(公告)号：US20090141456A1

公开(公告)日：2009-06-04

申请号：US11948338

申请日：2007-11-30

Applicant: Gregg T. Juett

Inventor： Gregg T. Juett

IPC: H05K7/20

CPC classification number: H05K3/4641 ,  H01L23/3735 ,  H01L23/5385 ,  H01L2924/0002 ,  H05K1/0207 ,  H05K1/05 ,  H05K1/053 ,  H05K1/056 ,  H05K1/144 ,  H05K3/0061 ,  H05K3/3436 ,  H05K2201/0338 ,  H05K2201/068 ,  H05K2201/0919 ,  H01L2924/00

Abstract: A multilayer, thermally-stabilized substrate, including: a thermally-conductive core structure, including a central section located horizontally between two edge sections; a top multilayer circuit board connected to the top surface of the central portion of the core structure; and a bottom multilayer circuit board connected to the bottom surface of the central portion of the core structure. The core structure has a core thermal conductance and a effective core horizontal thermal expansion coefficient. The top and bottom multilayer circuit boards each include at least one dielectric layer and at least one electrically-conductive layer, and each have a circuit board thermal conductance that is less than the core thermal conductance of the core structure. The electrically-conductive layers of the top and the bottom circuit boards each have a conductive layer horizontal thermal expansion coefficient that is less than or equal to the effective core horizontal thermal expansion coefficient of the core structure.

Abstract translation: 一种多层热稳定基板，包括：导热芯结构，包括水平位于两个边缘部分之间的中心部分; 连接到所述芯结构的中心部分的顶表面的顶部多层电路板; 以及连接到芯结构的中心部分的底表面的底部多层电路板。 核心结构具有核心导热性和有效的核心水平热膨胀系数。 顶部和底部多层电路板各自包括至少一个电介质层和至少一个导电层，并且每个电路板的电导率小于芯结构的芯热导率。 顶部和底部电路板的导电层各自具有小于或等于芯结构的有效芯水平热膨胀系数的导电层水平热膨胀系数。

公开(公告)号：US20080217758A1

公开(公告)日：2008-09-11

申请号：US12044697

申请日：2008-03-07

Applicant: Guo-cheng Liao

Inventor： Guo-cheng Liao

IPC: H01L23/48 ,  H01L21/00

CPC classification number: H01L23/49838 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/242 ,  H05K3/4092 ,  H05K3/4602 ,  H05K2201/0919 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A package substrate strip having a reserved plating bar and a metal surface treatment method thereof are provided. The metal surface treatment method forms a conductive layer connecting the reserved plating bar and bonding pads of the package substrate stripe and further forms an isolating layer covering the conductive layer. By original plating bars and the reserved plating bar, an anti-oxidation layer can be simultaneously formed on finger contacts, first ball pads electrically connected to the finger contacts, and second ball pads electrically connected to the bonding pads. The package substrate strip and the method for metal surface treatment thereof can simplify manufacturing process, reduce production cost, and improve production efficiency and yield. Furthermore, a chip package applying the package substrate strip is also provided.

Abstract translation: 提供具有预留电镀条和其金属表面处理方法的封装衬底条。 金属表面处理方法形成连接保留电镀条和封装衬底条纹的焊盘的导电层，并进一步形成覆盖导电层的绝缘层。 通过原始电镀条和预留电镀条，可以在手指触点上同时形成抗氧化层，电连接到手指触点的第一焊盘和与焊盘电连接的第二焊盘。 封装基板条及其金属表面处理方法可以简化制造工艺，降低生产成本，提高生产效率和产量。 此外，还提供了应用封装衬底条的芯片封装。

公开(公告)号：US20080205016A1

公开(公告)日：2008-08-28

申请号：US11908726

申请日：2006-03-15

Applicant: Masahiro Takatori ,  Yukihiro Ishimaru

Inventor： Masahiro Takatori ,  Yukihiro Ishimaru

IPC: H05K1/14

CPC classification number: H01L25/0652 ,  H01L23/5385 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0268 ,  H05K1/112 ,  H05K1/117 ,  H05K1/185 ,  H05K3/4611 ,  H05K2201/0919 ,  H05K2201/09845 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A module board has a configuration in which a first circuit board, a first composite sheet, a second circuit board, a second composite sheet, and a third circuit board are laminated in this order. Inspection terminals are arranged in a matrix shape in a predetermined region on an upper surface of the third circuit board. Electronic components are mounted on the first and second circuit boards. The inspection terminals are electrically connected to the electronic components mounted on the first and second circuit boards through vias and wiring patterns.

Abstract translation: 模块板具有以下顺序构造第一电路板，第一复合片，第二电路板，第二复合片和第三电路板。 检查端子在第三电路板的上表面上的预定区域中以矩阵形状布置。 电子部件安装在第一和第二电路板上。 检查端子通过通孔和布线图形电连接到安装在第一和第二电路板上的电子部件。

公开(公告)号：US20080138575A1

公开(公告)日：2008-06-12

申请号：US11856858

申请日：2007-09-18

Applicant: Chih-kuang Yang

Inventor： Chih-kuang Yang

IPC: B32B3/10 ,  H01R43/00

CPC classification number: H05K1/147 ,  H01L23/13 ,  H01L23/5385 ,  H01L25/162 ,  H01L2224/48091 ,  H01L2924/01322 ,  H01L2924/19107 ,  H05K1/142 ,  H05K3/4611 ,  H05K2201/058 ,  H05K2201/091 ,  H05K2201/09109 ,  H05K2201/0919 ,  H05K2201/09481 ,  Y10T29/417 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T428/24322 ,  Y10T428/24917 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A hybrid structure of multi-layer substrates comprises a first multi-layer substrate and a second multi-layer substrate. The first multi-layer substrate stacks up first metal layers, first dielectric layers alternately and has VIAs. A border district of a first metal layer connects with a border district of the corresponding first dielectric layer. The border districts are separated from adjacent first metal layers and adjacent first dielectric layers. The second multi-layer substrate stacks up second metal layers and second dielectric layers alternately. A border district of a second metal layer connects with a border district of the corresponding second dielectric layer. The border districts are separated from adjacent second metal layers and adjacent second dielectric layers. The VIAs are located at the border districts of the first dielectric layers and each VIA has electric conductor therein to connect one first metal layer with one second metal layer.

Abstract translation: 多层基板的混合结构包括第一多层基板和第二多层基板。 第一多层基板交替地堆叠第一金属层，第一介电层并具有VIA。 第一金属层的边界区域与相应的第一介电层的边界区域连接。 边界区域与相邻的第一金属层和相邻的第一介电层分离。 第二多层基板交替堆叠第二金属层和第二电介质层。 第二金属层的边界区域与相应的第二电介质层的边界区域连接。 边界区域与相邻的第二金属层和相邻的第二介电层分离。 VIA位于第一电介质层的边界区，并且每个VIA具有导电体，以将一个第一金属层与一个第二金属层连接。