公开(公告)号：US08837160B2

公开(公告)日：2014-09-16

申请号：US13175683

申请日：2011-07-01

Applicant: Takashi Kariya ,  Hironori Tanaka

Inventor： Takashi Kariya ,  Hironori Tanaka

IPC: H05K1/16 ,  H01L21/48 ,  H01L23/50 ,  H01L23/498 ,  H05K3/38 ,  H05K3/46

CPC classification number: H05K1/162 ,  H01L21/4867 ,  H01L23/498 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K3/388 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A method of producing a capacitor for a printed circuit board includes producing high-dielectric sheets and selecting ones of the high-dielectric sheets, which are substantially free from a defect after the heat process. Each of the high-dielectric sheets is produced by providing a first electrode, forming a first sputter film on the first electrode, forming an intermediate layer on the first sputter film by calcining a sol-gel film, forming a second sputter film on the intermediate layer, and providing a second electrode on the second sputter film. The high-dielectric sheets are subjected to a heat process in which the high-dielectric sheets are subjected to a first temperature at least once and a second temperature higher than the first temperature at least once.

Abstract translation: 一种印刷电路板用电容器的制造方法，其特征在于，制造高介电质片材，并选择在热处理后基本上不存在缺陷的高电介质片材。 每个高电介质片通过提供第一电极来制造，在第一电极上形成第一溅射膜，通过煅烧溶胶 - 凝胶膜在第一溅射膜上形成中间层，在中间层上形成第二溅射膜 并且在第二溅射膜上提供第二电极。 对高电介质片材进行热处理，其中高电介质片材经受至少一次的第一温度和比第一温度高至少一次的第二温度。

公开(公告)号：US20140202750A1

公开(公告)日：2014-07-24

申请号：US14148979

申请日：2014-01-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Takeshi KOGURE ,  Hiromichi KITAJIMA

IPC: H05K1/02 ,  H05K1/18

CPC classification number: H05K1/165 ,  H05K1/0298 ,  H05K2201/0792 ,  H05K2201/09309 ,  H05K2201/0969

Abstract: A multilayer substrate module includes a multilayer circuit substrate, a mounting land, and an input/output terminal. Inside the multilayer circuit substrate, a wiring line that connects the mounting land and the input/output terminal to each other, an inductor that defines a portion of the wiring line, a first ground conductor that is positioned on the one main surface side of the inductor, and a second ground conductor that is positioned on the other main surface side of the inductor are defined by conductor patterns. The area where inductor is located is not superposed with the area where the second ground conductor is located, when the one main surface or the other main surface of the multilayer circuit substrate is viewed in plan, the second ground conductor being closer to the layer where the inductor is located than the first ground conductor is.

Abstract translation: 多层基板模块包括多层电路基板，安装台面和输入/输出端子。 在多层电路基板的内部，将安装台面和输入输出端子彼此连接的布线，限定布线的一部分的电感器，位于第一接地导体的一个主面侧的第一接地导体 电感器和位于电感器的另一主表面侧的第二接地导体由导体图案限定。 电感器所在的区域不与第二接地导体所在的区域重叠，当在平面图中观察多层电路衬底的一个主表面或另一个主表面时，第二接地导体更靠近层 电感器位于第一接地导体之上。

公开(公告)号：US08779298B2

公开(公告)日：2014-07-15

申请号：US13387421

申请日：2010-06-17

Applicant: Richard Asterland

Inventor： Richard Asterland

IPC: H05K1/00

CPC classification number: H05K1/0216 ,  H05K1/0366 ,  H05K3/4688 ,  H05K2201/0284 ,  H05K2201/09309 ,  H05K2201/09518 ,  H05K2201/10689

Abstract: Electronic circuits (1, 101) are disclosed. The electronic circuits comprise a first and a second integrated circuit (10a, 110a, 10b, 110b) and a printed circuit board (PCB) (15, 115). The PCB comprises dielectric layers (30a-c, 130) of polymer-based materials having different dissipation factors arranged in accordance with various embodiments for suppressing noise.

Abstract translation: 公开了电子电路（1,101）。 电子电路包括第一和第二集成电路（10a，110a，10b，110b）和印刷电路板（PCB）（15,115）。 PCB包括根据用于抑制噪声的各种实施例布置的具有不同耗散因数的基于聚合物的材料的介电层（30a-c，130）。

公开(公告)号：US08743529B2

公开(公告)日：2014-06-03

申请号：US13143637

申请日：2010-01-06

Applicant: Todd Hubing ,  Hocheol Kwak ,  Haixin Ke

Inventor： Todd Hubing ,  Hocheol Kwak ,  Haixin Ke

IPC: H01G4/228

CPC classification number: H01G4/232 ,  H01G2/06 ,  H01G4/30 ,  H01G4/35 ,  H01G4/40 ,  H05K1/184 ,  H05K2201/092 ,  H05K2201/09309

Abstract: A capacitor having a stem that is designed to be inserted into a single, large-diameter via hole drilled in a printed circuit board is provided, wherein the stem may have conductive rings for making the positive and negative connections to the printed circuit board power distribution planes. Inside the capacitive stem, current, or at least a portion thereof, may be carried to the main body of the capacitor through low-inductance plates that are interleaved to maximize their own mutual inductance and, therefore, minimize the connection inductance. Alternatively, the capacitor may include a coaxial stem that forms a coaxial transmission line with the anode and cathode terminals forming the inner and outer conductors.

Abstract translation: 提供一种电容器，其具有设计成插入到印刷电路板中钻出的单个大直径通孔中的阀杆，其中所述阀杆可具有导电环，用于使得与所述印刷电路板配电的正极和负极连接 飞机 在电容杆内部，电流或其至少一部分可以通过交错的低电感板传送到电容器的主体，以使其自身的互感最大化，从而使连接电感最小化。 或者，电容器可以包括形成同轴传输线的同轴杆，阳极和阴极端子形成内导体和外导体。

公开(公告)号：US20140133115A1

公开(公告)日：2014-05-15

申请号：US13922349

申请日：2013-06-20

Applicant: FUJI XEROX Co., Ltd.

Inventor： Daisuke IGUCHI

IPC: H05K1/02

CPC classification number: H05K1/0243 ,  H05K1/0231 ,  H05K1/141 ,  H05K1/162 ,  H05K1/181 ,  H05K2201/041 ,  H05K2201/09309 ,  H05K2201/09327 ,  H05K2201/09345 ,  H05K2201/09663

Abstract: A multilayer wiring board includes a signal electrode, a first power supply electrode, and a ground electrode, which are connected to a first element that outputs a signal, an electrode connected to a second element that receives the signal, a ground layer that serves as a return path for a return current of the signal, a first power supply layer that is disposed adjacent to the ground layer with a dielectric layer interposed therebetween and supplies electric power to the first element, and a second power supply layer that is provided independently of the first power supply layer and supplies electric power to the second element. The first power supply layer causes the return current to return to the first element through the first power supply electrode as a displacement current between the ground layer and the first power supply layer.

Abstract translation: 多层布线板包括信号电极，第一电源电极和接地电极，它们连接到输出信号的第一元件，连接到接收信号的第二元件的电极，用作 用于所述信号的返回电流的返回路径，与所述接地层相邻设置有电介质层并且向所述第一元件提供电力的第一电源层和与所述第一电源层独立地设置的第二电源层， 第一电源层并且向第二元件供电。 第一电源层使返回电流通过第一电源电极返回到第一元件，作为接地层和第一电源层之间的位移电流。

公开(公告)号：US08722536B2

公开(公告)日：2014-05-13

申请号：US13959003

申请日：2013-08-05

Applicant: International Business Machines Corporation

Inventor： Daniel Douriet ,  Francesco Preda ,  Brian L. Singletary ,  Lloyd A. Walls

IPC: H01L21/44

CPC classification number: H01L21/768 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/16 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/0231 ,  H05K1/0263 ,  H05K1/113 ,  H05K3/429 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2201/10674 ,  Y10T29/49165

Abstract: A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to “jog” circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate.

Abstract translation: 电路基板使用后馈电顶部电源连接来提供改进的布线灵活性和较低的电源电压降/功率损耗。 在基板的外边缘附近使用电镀通孔，以提供与作为电源平面的管芯相邻的基板的顶部金属层的电源连接。 引脚插入通过电镀通孔以进一步降低电源路径的电阻。 引脚的底端可以延伸越过基板的底部以提供用于电源连接的可焊接互连，或者引脚的底端可以被焊接到基板的底部金属层上的“点动”电路图案，其连接 引脚连接到包括基板的集成电路封装的一个或多个电源端子。

公开(公告)号：US08707552B2

公开(公告)日：2014-04-29

申请号：US11580927

申请日：2006-10-16

Applicant: Takashi Kariya ,  Hironori Tanaka

Inventor： Takashi Kariya ,  Hironori Tanaka

IPC: H05K3/30

CPC classification number: H05K1/162 ,  H01L21/4867 ,  H01L23/498 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K3/388 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A high-dielectric sheet for a printed circuit board includes a first electrode, a first sputter film formed on the first electrode, an intermediate layer formed on the first sputter film by calcining a sol-gel film, a second sputter film formed on the intermediate layer, and a second electrode provided on the second sputter film.

Abstract translation: 用于印刷电路板的高电介质片包括第一电极，形成在第一电极上的第一溅射膜，通过煅烧溶胶 - 凝胶膜在第一溅射膜上形成的中间层，形成在中间体上的第二溅射膜 层和设置在第二溅射膜上的第二电极。

公开(公告)号：US20140085772A1

公开(公告)日：2014-03-27

申请号：US14014773

申请日：2013-08-30

Applicant: SAMHWA CAPACITOR CO., LTD.

Inventor： Young Joo OH ,  Jung Rag YOON ,  Kyung Min LEE ,  Young Min YOO

IPC: H01G4/38

CPC classification number: H01G4/38 ,  H01G2/06 ,  H01G4/40 ,  H05K1/0231 ,  H05K1/116 ,  H05K3/306 ,  H05K3/4641 ,  H05K2201/09309 ,  H05K2201/09345 ,  H05K2201/09718 ,  H05K2201/1034 ,  Y02T10/7022

Abstract: A direct current (DC) link capacitor module includes a printed circuit board (PCB) formed by sequentially disposing a first electrode substrate, an insulation substrate, a second electrode substrate, a third electrode substrate; a plurality of DC link capacitors connected in parallel to each of the first electrode substrate and the second electrode substrate; a plurality of first Y-capacitors connected in series to each of the first electrode substrate and the third electrode substrate, and connected in parallel to the DC link capacitors; and a plurality of second Y-capacitors connected in series to each of the first electrode substrate and the third electrode substrate, and connected in parallel to the first Y-capacitors, thereby achieving a miniaturization and facilitating a fabrication by connecting the plurality of DC link capacitors using the PCB.

Abstract translation: 直流（DC）链路电容器模块包括通过顺序地布置第一电极基板，绝缘基板，第二电极基板，第三电极基板形成的印刷电路板（PCB） 与第一电极基板和第二电极基板中的每一个并联连接的多个DC链路电容器; 多个第一Y电容器，与第一电极基板和第三电极基板中的每一个串联连接，并联连接到直流链路电容器; 以及与第一电极基板和第三电极基板中的每一个串联连接并与第一Y电容器并联连接的多个第二Y电容器，从而实现小型化，并且通过将多个DC链路 电容使用PCB。

公开(公告)号：US08683413B2

公开(公告)日：2014-03-25

申请号：US13621242

申请日：2012-09-15

Applicant: Wiren Dale Becker ,  Jinwoo Choi ,  Tingdong Zhou

Inventor： Wiren Dale Becker ,  Jinwoo Choi ,  Tingdong Zhou

IPC: G06F17/50 ,  G06F9/455 ,  H01L21/00

CPC classification number: H01L21/76838 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/19051 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K3/4629 ,  H05K2201/09309 ,  H05K2201/09681 ,  H05K2201/09727 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A multi-layered ceramic package comprises: a signal layer with identified chip/device area(s) that require a supply of power; and a voltage power (Vdd) layer and a ground (Gnd) layer disposed on opposite sides directly above or below and adjacent to the signal layer and providing a first reference mesh plane and a second reference mesh plane configured utilizing a hybrid mesh scheme. The hybrid mesh scheme comprises: a full dense mesh in a first area directly above or below the identified chip/device area(s); a half dense mesh in a second area that is above or below the edge(s) of the chip/device area; and a wider mesh pitch in all other areas The Vdd traces are aligned to run parallel and adjacent to signal lines in those other areas. Wider traces are provided within the mesh areas that run parallel and adjacent to signal lines.

Abstract translation: 多层陶瓷封装包括：具有需要供电的识别芯片/器件区域的信号层; 以及设置在信号层正上方或下方并相邻的相对侧上的电压功率（Vdd）层和接地（Gnd）层，并提供使用混合网格方案配置的第一参考网格平面和第二参考网格平面。 混合网格方案包括：在识别的芯片/设备区域的正上方或下方的第一区域中的全密度网格; 在芯片/设备区域的边缘的上方或下方的第二区域中的半密度网格; 和所有其他区域中的较宽的网格间距Vdd迹线对齐以与其他区域的信号线平行并相邻。 在与信号线平行且相邻的网格区域内提供更宽的轨迹。

公开(公告)号：US08669758B2

公开(公告)日：2014-03-11

申请号：US13949031

申请日：2013-07-23

Applicant: Broadcom Corporation

Inventor： Iain Barnett ,  William Michael James Holland ,  Jonathan Ephraim David Hurwitz

IPC: G01R19/00

CPC classification number: H05K1/162 ,  G01R15/06 ,  G01R15/16 ,  G01R19/12 ,  G01R19/175 ,  H03H7/004 ,  H05K1/0239 ,  H05K1/0256 ,  H05K2201/09309 ,  H05K2201/09972

Abstract: A voltage measurement circuit is operative to measure a high voltage AC signal and includes a capacitive divider circuit and a compensator circuit. The capacitive divider circuit includes first and second inputs, across which, in use, is received a high voltage AC signal and also includes second and third capacitors. First and second plates of each of the first, second and third capacitors are defined by conductive layers of a printed circuit board and the dielectric of each of the first, second and third capacitors being defined by a non-conducting part of the printed circuit board. A compensator circuit has a configurable transfer function and includes an input connected across the first and second plates of the third capacitor and an output. The compensator circuit is operative to change a voltage received at its input in accordance with the transfer function and to provide the changed voltage at its output.

Abstract translation: 电压测量电路用于测量高压AC信号，并包括电容分压器电路和补偿电路。 电容分压器电路包括第一和第二输入，在使用中，它们被接收高压AC信号，并且还包括第二和第三电容器。 第一，第二和第三电容器中的每一个的第一和第二板由印刷电路板的导电层限定，并且第一，第二和第三电容器中的每一个的电介质由印刷电路板的非导电部分限定 。 补偿电路具有可配置的传递函数，并且包括连接在第三电容器的第一和第二板上的输入端和输出端。 补偿电路可操作以根据传递函数改变其输入处接收的电压，并在其输出端提供改变的电压。