公开(公告)号：US10038264B2

公开(公告)日：2018-07-31

申请号：US15351237

申请日：2016-11-14

Applicant: Microsoft Technology Licensing, LLC

Inventor： David Lukofsky ,  Joseph Christopher Bolling ,  Jeffrey M. Quackenbush ,  Tapani von Rauner

IPC: H01R12/00 ,  H01R12/91 ,  H01R12/78 ,  H01R12/72 ,  H04N13/04

CPC classification number: H01R12/91 ,  H01R12/721 ,  H01R12/78 ,  H04N13/344 ,  H04N2213/001 ,  H04N2213/008 ,  H05K1/0221 ,  H05K1/0295 ,  H05K1/11 ,  H05K3/361 ,  H05K2201/09272 ,  H05K2201/09381 ,  H05K2201/0939

Abstract: A universal coupling is disclosed for electrically and mechanically connecting flexible printed circuit (FPC) components within asymmetric FPC modules. The universal coupling allows a first FPC component to be connected to a second FPC component in two or more different orientations. This allows identical FPC components to be used in two or more asymmetric FPC modules. This in turn allows a reduction in the number of parts and tooling required to fabricate the two or more asymmetric FPC modules, and a simplification of the fabrication process.

公开(公告)号：US09480141B1

公开(公告)日：2016-10-25

申请号：US14032908

申请日：2013-09-20

Applicant: Junis Hamadeh

Inventor： Junis Hamadeh

IPC: H05K1/02 ,  H01R12/00

CPC classification number: H01R12/00 ,  H05K1/0206 ,  H05K1/021 ,  H05K1/113 ,  H05K2201/09381 ,  H05K2201/0939 ,  H05K2201/09463 ,  H05K2201/0959 ,  H05K2201/10106 ,  H05K2201/10401 ,  H05K2201/10416

Abstract: A heat sinking rapid assembly semiconductor package comprising an electrically segmented conductive assembly post. The post is fabricated comprising at least two independent electrically conductive segments separated by an electrically isolating element. An electrical component, such as a semiconductor device, is assembled to an upper portion of the conductive post, wherein each contact of the component is in electrical communication with a respective conductive segment. The post can be mechanically pressed, threaded, or mechanically coupled using any other reasonable mechanical interface into a segmented via or plated-through hole of a printed circuit board (PCB). The electrical segments would be in electrical communication with conductive portions of the segmented via to form a complete electrical circuit between the PCB and the electrical component. A thermally conductive element can be integrated into the post to conduct heat away from the semiconductor device to improve performance and reduce failures related to thermal stress.

Abstract translation: 一种散热快速组装半导体封装，包括电分段的导电组件柱。 该柱被制造成包括由电隔离元件隔开的至少两个独立的导电段。 诸如半导体器件的电气部件被组装到导电柱的上部，其中部件的每个触点与相应的导电部分电连通。 可以使用任何其他合理的机械接口将柱机械地压制，螺纹化或机械耦合到印刷电路板（PCB）的分段通孔或电镀通孔中。 电段将与分段通孔的导电部分电连通，以在PCB和电气部件之间形成完整的电路。 导热元件可以集成到柱中以将热量从半导体器件导出，以提高性能并减少与热应力相关的故障。

公开(公告)号：US20160259139A1

公开(公告)日：2016-09-08

申请号：US15028934

申请日：2014-10-08

Applicant: AMS AG

Inventor： Jochen KRAFT ,  Karl ROHRACHER ,  Jordi TEVA

IPC: G02B6/42 ,  G02B6/13 ,  G02B6/12 ,  H01L23/48 ,  H01L31/16

CPC classification number: G02B6/4283 ,  G02B6/12002 ,  G02B6/13 ,  G02B6/4274 ,  G02B6/428 ,  G02B6/43 ,  G02B2006/121 ,  G02B2006/12107 ,  G02B2006/12121 ,  G02B2006/12123 ,  G02B2006/12147 ,  H01L23/481 ,  H01L23/522 ,  H01L31/16 ,  H01L2224/16225 ,  H05K1/0274 ,  H05K1/115 ,  H05K1/116 ,  H05K1/181 ,  H05K3/429 ,  H05K3/4605 ,  H05K2201/0939 ,  H05K2201/09518 ,  H05K2201/09581 ,  H05K2201/10174

Abstract: The method comprises providing a semiconductor substrate, which has a main surface and an opposite further main surface, arranging a contact pad above the further main surface, forming a through-substrate via from the main surface to the further main surface at a distance from the contact pad and, by the same method step together with the through-substrate via, forming a further through-substrate via above the contact pad, arranging a hollow metal via layer in the through-substrate via and, by the same method step together with the metal via layer, arranging a further metal via layer in the further through-substrate via, the further metal via layer contacting the contact pad, and removing a bottom portion of the metal via layer to form an optical via laterally surrounded by the metal via layer.

Abstract translation: 该方法包括提供半导体衬底，其具有主表面和相对的另一个主表面，将接触焊盘布置在另一个主表面上方，从而从主表面到另一个主表面在距离 接触焊盘，并且通过与通孔基板通孔相同的方法步骤，在接触焊盘上方形成另外的通孔，在穿通基板中经由中空金属通孔层，并且通过相同的方法步骤连同 金属通孔层，在另外的通孔中经由另外的金属通孔层，通过另外的金属通孔层与接触垫接触，以及去除金属通孔层的底部，以形成由金属通孔横向包围的光学通孔 层。

公开(公告)号：US20160148911A1

公开(公告)日：2016-05-26

申请号：US14903858

申请日：2014-07-08

Applicant: PSI CO., LTD.

Inventor： Young Rag Do

IPC: H01L25/075 ,  H01L33/38 ,  H01L33/62

CPC classification number: H01L25/0753 ,  H01L33/38 ,  H01L33/62 ,  H01L2924/0002 ,  H01L2933/0066 ,  H05K1/0295 ,  H05K1/0296 ,  H05K1/111 ,  H05K3/3442 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09381 ,  H05K2201/0939 ,  H05K2201/09427 ,  H05K2201/09954 ,  H05K2201/10106 ,  H05K2201/10583 ,  H05K2201/10636 ,  H05K2201/10651 ,  H05K2203/048 ,  Y02P70/611 ,  H01L2924/00

Abstract: Provided are a nano-scale LED assembly and a method for manufacturing the same. First, a nano-scale LED device that is independently manufactured may be aligned and connected to two electrodes different from each other to solve a limitation in which a nano-scale LED device having a nano unit is coupled to two electrodes different from each other in a stand-up state. Also, since the LED device and the electrodes are disposed on the same plane, light extraction efficiency of the LED device may be improved. Furthermore, the number of nano-scale LED devices may be adjusted. Second, since the nano-scale LED device does not stand up to be three-dimensionally coupled to upper and lower electrodes, but lies to be coupled to two electrodes different from each other on the same plane, the light extraction efficiency may be very improved. Also, since a separate layer is formed on a surface of the LED device to prevent the LED device and the electrode from being electrically short-circuited, defects of the LED electrode assembly may be minimized. Also, in preparation for the occurrence of the very rare defects of the LED device, the plurality of LED devices may be connected to the electrode to maintain the original function of the nano-scale LED electrode assembly.

Abstract translation: 提供了一种纳米级LED组件及其制造方法。 首先，独立制造的纳米级LED器件可以对准并连接到彼此不同的两个电极，以解决将具有纳米单元的纳米级LED器件耦合到彼此不同的两个电极的限制 站立状态。 此外，由于LED器件和电极设置在同一平面上，所以可以提高LED器件的光提取效率。 此外，可以调整纳米级LED器件的数量。 第二，由于纳米尺度的LED器件不能立即连接到上电极和下电极，而是要被连接到在同一平面上彼此不同的两个电极，所以光提取效率可以非常改善 。 此外，由于在LED器件的表面上形成单独的层以防止LED器件和电极电短路，所以可以使LED电极组件的缺陷最小化。 此外，为了准备LED装置的非常罕见的缺陷的发生，可以将多个LED器件连接到电极以保持纳米级LED电极组件的原始功能。

公开(公告)号：US20150093860A1

公开(公告)日：2015-04-02

申请号：US14040552

申请日：2013-09-27

Applicant: David W. Hamby ,  Adam M. Scotch ,  Sridharan Venk ,  Alan Lenef

Inventor： David W. Hamby ,  Adam M. Scotch ,  Sridharan Venk ,  Alan Lenef

IPC: H01L33/62 ,  H01L33/38 ,  H05K1/11 ,  H01L23/00

CPC classification number: H01L33/62 ,  H01L24/83 ,  H01L33/38 ,  H01L2924/12041 ,  H05K1/111 ,  H05K3/303 ,  H05K2201/0939 ,  H05K2201/09809 ,  H05K2201/10106 ,  H05K2203/048 ,  H05K2203/0776 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00

Abstract: The present disclosure is directed to orientation-independent device configuration and assembly. An electronic device may comprise conductive pads arranged concentrically on a surface of the device. The conductive pads on the device may mate with conductive pads in a device location in circuitry. Example conductive pads may include at least a first circular conductive pad and a second ring-shaped conductive pad arranged to concentrically surround the first conductive pad. The concentric arrangement of the conductive pads allows for orientation-independent placement of the device in the circuitry. In particular, the conductive pads of the device will mate correctly with the conductive pads of the circuitry regardless of variability in device orientation. In one embodiment, the device may also be configured for use with fluidic self-assembly (FSA). For example, a device housing may be manufactured with pockets that cause the device to attain neutral buoyancy during manufacture.

Abstract translation: 本公开涉及定向无关的装置配置和组装。 电子设备可以包括同心地布置在设备的表面上的导电焊盘。 器件上的导电焊盘可与电路中的器件位置中的导电焊盘配合。 示例性导电焊盘可以包括至少第一圆形导电焊盘和布置成同心地围绕第一导电焊盘的第二环形导电焊盘。 导电焊盘的同心布置允许器件在电路中的定向无关放置。 特别地，器件的导电焊盘将正确地与电路的导电焊盘配合，而不管器件取向如何变化。 在一个实施例中，该装置还可以被配置为与流体自组装（FSA）一起使用。 例如，可以制造具有在制造期间使装置达到中性浮力的袋的装置壳体。

公开(公告)号：US20140332258A1

公开(公告)日：2014-11-13

申请号：US14368869

申请日：2013-08-20

Applicant: SUMITOMO ELECTRIC PRINTED CIRCUITS, INC. ,  SUMITOMO ELECTRIC INDUSTRIES, LTD.

Inventor： Yoshifumi Uchida ,  Yoshio Oka ,  Takashi Kasuga

IPC: H05K1/11 ,  H05K3/40

CPC classification number: H05K1/116 ,  H05K1/0393 ,  H05K3/0035 ,  H05K3/4038 ,  H05K3/4069 ,  H05K2201/0939 ,  H05K2201/09481 ,  H05K2203/1453 ,  Y10T29/49165

Abstract: An object of the present invention is to provide a double-sided printed wiring board in which a blind via hole can be easily and reliably formed, which can be accurately applied to lands of a surface-mounted component that are arranged at a narrow pitch, and in which an impedance mismatch can be effectively suppressed. The double-sided printed wiring board according to the present invention includes a substrate having an insulating property, a first conductive pattern stacked on a surface of the substrate and having a first land portion, a second conductive pattern stacked on another surface of the substrate and having a second land portion opposing the first land portion, and a blind via hole penetrating through the first land portion and the substrate, in which an average diameter of an outer shape of the first land portion is larger than an average diameter of an outer shape of the second land portion. The blind via hole, the first land portion, and the second land portion preferably have substantially circular outer shapes, and are preferably formed so as to be substantially concentric with each other.

Abstract translation: 本发明的目的是提供一种双面印刷布线板，其中可以容易且可靠地形成盲孔，能够精确地施加到以窄间距布置的表面安装部件的平台上， 并且其中可以有效地抑制阻抗失配。 根据本发明的双面印刷布线板包括具有绝缘性的基板，层叠在基板的表面上的第一导电图案，并且具有第一接地部分，在基板的另一表面上堆叠的第二导电图案，以及 具有与第一接地部相对的第二接地部，以及穿过第一接地部和基板的盲通孔，第一接地部的外形的平均直径大于外形的平均直径 的第二土地部分。 盲通孔，第一接地部和第二接地部优选具有大致圆形的外形，并且优选形成为基本上彼此同心。

公开(公告)号：US08299367B2

公开(公告)日：2012-10-30

申请号：US12841518

申请日：2010-07-22

Applicant: Hsiang-Chih Ni ,  Ching-Feng Hsieh

Inventor： Hsiang-Chih Ni ,  Ching-Feng Hsieh

IPC: H05K1/16 ,  B23K1/20

CPC classification number: H05K1/111 ,  H05K3/3421 ,  H05K2201/09381 ,  H05K2201/0939 ,  Y02P70/611

Abstract: A notch positioning type soldering structure and a method for preventing a pin deviation can prevent a plurality of pins of an electronic component from being deviated when the pins are soldered onto a printed circuit board by a solder, and each of at least two solder pads includes at least one notch, and the solder pads are installed in an alignment direction on the printed circuit board, such that the notch positioning type soldering structure and the method for preventing a pin deviation can improve the efficiency of manufacturing processes and reduce the manufacturing cost.

Abstract translation: 凹口定位型焊接结构和防止引脚偏移的方法可以防止当引脚​​通过焊料焊接到印刷电路板上时电子部件的多个引脚偏离，并且至少两个焊盘中的每一个包括 至少一个切口，并且焊盘沿着印刷电路板上的排列方向安装，使得凹口定位型焊接结构和防止引脚偏离的方法可以提高制造工艺的效率并降低制造成本。

公开(公告)号：US20110284278A1

公开(公告)日：2011-11-24

申请号：US13110136

申请日：2011-05-18

Applicant: Kiyohiro Hine ,  Shigeaki Sakatani ,  Akio Furusawa

Inventor： Kiyohiro Hine ,  Shigeaki Sakatani ,  Akio Furusawa

IPC: H05K1/18

CPC classification number: H05K1/111 ,  H05K3/3442 ,  H05K3/3484 ,  H05K2201/09381 ,  H05K2201/0939 ,  H05K2201/09663 ,  H05K2201/09745 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613

Abstract: A mounting structure includes an insulating substrate having a substrate electrode on which at least one electrode notch is provided and a resist, an electronic component having an electronic component electrode to be electrically connected to the substrate electrode, and solder paste printed on a surface of the substrate electrode. The substrate electrode has a following relation, 0

Abstract translation: 安装结构包括绝缘基板，其具有设置有至少一个电极切口的基板电极和抗蚀剂，具有电连接到基板电极的电子部件电极的电子部件和印刷在基板电极的表面上的焊膏 基板电极。 基板电极具有以下关系：0

公开(公告)号：US07806731B2

公开(公告)日：2010-10-05

申请号：US11321931

申请日：2005-12-29

Applicant: Hem Takiar ,  Cheemen Yu ,  Ken Jian Ming Wang ,  Chin-Tien Chiu ,  Han-Shiao Chen ,  Chih-Chin Liao

Inventor： Hem Takiar ,  Cheemen Yu ,  Ken Jian Ming Wang ,  Chin-Tien Chiu ,  Han-Shiao Chen ,  Chih-Chin Liao

IPC: H01R24/00

CPC classification number: H01L23/49838 ,  H01L23/3121 ,  H01L23/49811 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/30107 ,  H05K1/117 ,  H05K3/242 ,  H05K3/3452 ,  H05K2201/09281 ,  H05K2201/09381 ,  H05K2201/0939 ,  H05K2201/099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.

Abstract translation: 公开了一种加强的半导体管芯基板和封装。 衬底可以包括形成有非线性边缘的接触指状物。 向接触指边缘提供非线性轮廓减少了施加在半导体管芯上的机械应力，否则这些应力将以直接接触指的边缘发生。 衬底可以附加地或可选地包括从接触指一定角度延伸的电镀迹线。 以一定角度延伸，至少衬底边缘处的电镀迹线的端部被覆盖在半导体封装被封装的盖子的下方。 因此，当与主机设备一起使用时，避免了盖子下方的电镀痕迹的端部和主机设备的接触销之间的接触。

公开(公告)号：US20070155247A1

公开(公告)日：2007-07-05

申请号：US11321931

申请日：2005-12-29

Applicant: Hem Takiar ,  Cheemen Yu ,  Ken Wang ,  Chin-Tien Chiu ,  Han-Shiao Chen ,  Chih-Chin Liao

Inventor： Hem Takiar ,  Cheemen Yu ,  Ken Wang ,  Chin-Tien Chiu ,  Han-Shiao Chen ,  Chih-Chin Liao

IPC: H01R24/00

CPC classification number: H01L23/49838 ,  H01L23/3121 ,  H01L23/49811 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/30107 ,  H05K1/117 ,  H05K3/242 ,  H05K3/3452 ,  H05K2201/09281 ,  H05K2201/09381 ,  H05K2201/0939 ,  H05K2201/099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.

Abstract translation: 公开了一种加强的半导体管芯基板和封装。 衬底可以包括形成有非线性边缘的接触指状物。 向接触指边缘提供非线性轮廓减少了施加在半导体管芯上的机械应力，否则这些应力将以直接接触指的边缘发生。 衬底可以附加地或可选地包括从接触指一定角度延伸的电镀迹线。 以一定角度延伸，至少衬底边缘处的电镀迹线的端部被覆盖在半导体封装被封装的盖子的下方。 因此，当与主机设备一起使用时，避免了盖子下方的电镀痕迹的端部和主机设备的接触销之间的接触。