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    Method of electromagnetic noise suppression devices using hybrid electromagnetic bandgap structures
    22.
    发明授权
    Method of electromagnetic noise suppression devices using hybrid electromagnetic bandgap structures 有权
    使用混合电磁带隙结构的电磁噪声抑制装置的方法

    公开(公告)号：US08595924B2

    公开(公告)日：2013-12-03

    申请号：US12603071

    申请日：2009-10-21

    Applicant: William E. McKinzie, III

    Inventor： William E. McKinzie, III

    IPC: H05K3/02 ,  H05K3/10

    CPC classification number: H01P1/20 ,  H01P1/2005 ,  H05K1/0218 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/0236 ,  H05K1/0239 ,  H05K1/162 ,  H05K1/165 ,  H05K1/181 ,  H05K2201/093 ,  H05K2201/09318 ,  H05K2201/09609 ,  H05K2201/09663 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49018 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49155

    Abstract: A hybrid electromagnetic bandgap (EBG) structure for broadband suppression of noise on printed wiring boards includes an array of coplanar patches interconnected into a grid by series inductances, and a corresponding array of shunt LC networks connecting the coplanar patches to a second conductive plane. This combination of series inductances and shunt resonant vias lowers the cutoff frequency for the fundamental stopband. The series inductances and shunt capacitances may be implemented using surface mount component technology, or printed traces. Patches may also be interconnected by coplanar coupled transmission lines. The even and odd mode impedances of the coupled lines may be increased by forming slots in the second conductive plane disposed opposite to the transmission line, lowering the cutoff frequency and increasing the bandwidth of the fundamental stopband. Coplanar EBG structures may be integrated into power distribution networks of printed wiring boards for broadband suppression of electromagnetic noise.

    Abstract translation: 用于宽带抑制印刷电路板上的噪声的混合电磁带隙（EBG）结构包括通过串联电感互连到电网中的共面贴片阵列，以及将共面贴片连接到第二导电平面的相应阵列的分流LC网络。 串联电感和并联谐振通孔的组合降低了基波阻带的截止频率。 串联电感和分流电容可以使用表面贴装元件技术或印刷迹线实现。 补片也可以通过共面耦合传输线相互连接。 可以通过在与传输线相对布置的第二导电平面中形成槽，降低截止频率并增加基带阻带的带宽来增加耦合线的偶模和奇模阻抗。 共面EBG结构可以集成到用于宽带抑制电磁噪声的印刷线路板的配电网络中。

    Micro via adapter socket
    23.
    发明授权
    Micro via adapter socket 有权
    微通孔适配器插座

    公开(公告)号：US08491315B1

    公开(公告)日：2013-07-23

    申请号：US13306979

    申请日：2011-11-29

    Applicant: James M. Ramsey ,  Jose L. Ortega

    Inventor： James M. Ramsey ,  Jose L. Ortega

    IPC: H01R12/00

    CPC classification number: H01R12/714 ,  H05K1/115 ,  H05K2201/09609 ,  H05K2201/10303 ,  H05K2201/10325

    Abstract: A micro via adapter socket (12) is provided by a printed circuit board (30) having an upper layer (32), a lower layer (40) and intermediate interconnect layers (34, 36 and 38). The lower layer (32) has an array of mini vias (60) formed therein for receiving respective ones of mini-springs (62). A top plate (42) is secured above the upper layer (32). The top plate (42) has a plurality of micro-pin recesses (54) spaced apart for registering with respective ones of the micro vias (48) and receiving micro-pins (52). A bottom plate (44) is secured beneath the lower layer (40). The bottom plate (44) has a plurality of mini-pin recesses (66) for removably receiving respective ones of the mini-pins (64). The intermediate interconnect layers (34, 36 and 38) have conductive tracks (76) which electrically connect between the micro vias (48) and the mini vias (60).

    Abstract translation: 微通孔适配器插座（12）由具有上层（32），下层（40）和中间互连层（34,36和38）的印刷电路板（30）提供。 下层（32）具有形成在其中的微通道阵列（60），用于容纳相应的微型弹簧（62）。 顶板（42）固定在上层（32）的上方。 顶板（42）具有间隔开的多个微销凹槽（54），用于与相应的微通孔（48）和接收微销（52）配准。 底板（44）固定在下层（40）的下方。 底板（44）具有多个微型销凹槽（66），用于可拆卸地接收相应的微销（64）。 中间互连层（34,36和38）具有在微通孔（48）和微通孔（60）之间电连接的导电轨道（76）。

    BASE MEMBER
    24.
    发明申请
    BASE MEMBER 审中-公开
    基地会员

    公开(公告)号：US20130048350A1

    公开(公告)日：2013-02-28

    申请号：US13588013

    申请日：2012-08-17

    Applicant: Michio Horiuchi ,  Yasue Tokutake ,  Yuichi Matsuda

    Inventor： Michio Horiuchi ,  Yasue Tokutake ,  Yuichi Matsuda

    IPC: H05K1/05

    CPC classification number: H05K3/4608 ,  H05K1/0287 ,  H05K1/0306 ,  H05K3/002 ,  H05K3/4061 ,  H05K3/42 ,  H05K2201/09609

    Abstract: A base member includes: a core layer including: a plate-like body, made of aluminum oxide; and plural linear conductors, which penetrate through the plate-like body in a thickness direction of the plate-like body; a bonding layer, formed on at least one of a first surface and a second surface of the core layer; and a silicon layer or a glass layer, formed on the bonding layer.

    Abstract translation: 基底构件包括：芯层，包括：由氧化铝制成的板状体; 以及在板状体的厚度方向上穿过板状体的多个线状导体; 形成在芯层的第一表面和第二表面中的至少一个上的结合层; 以及形成在所述接合层上的硅层或玻璃层。

    Wiring board
    25.
    发明授权
    Wiring board 有权
    接线板

    公开(公告)号：US08362369B2

    公开(公告)日：2013-01-29

    申请号：US12792334

    申请日：2010-06-02

    Applicant: Michio Horiuchi ,  Yasue Tokutake ,  Yuichi Matsuda ,  Masao Nakazawa

    Inventor： Michio Horiuchi ,  Yasue Tokutake ,  Yuichi Matsuda ,  Masao Nakazawa

    IPC: H05K1/11

    CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H05K1/0287 ,  H05K1/0306 ,  H05K3/4605 ,  H05K3/4644 ,  H05K2201/09609 ,  H05K2201/09945 ,  H01L2924/00 ,  H01L2224/0401

    Abstract: A wiring board includes a core substrate having a structure including an insulating base material and a large number of filamentous conductors densely provided in the insulating base material and piercing the insulating base material in a thickness direction thereof. Pads made of portions of wiring layers are oppositely disposed on both surfaces of the core substrate and electrically connected to opposite ends of a plurality of filamentous conductors in such a manner that the pads share the filamentous conductors. A wiring connection between one surface side and the other surface side of the core substrate is made through the pads. The insulating base material is made of an inorganic dielectric. Pads made of portions of the wiring layers are disposed on both surfaces of the core substrate and electrically connected only to corresponding one end sides of different groups each formed of a plurality of filamentous conductors.

    Abstract translation: 布线基板包括芯基板，该芯基板具有密封地设置在绝缘基材中的绝缘基材和大量丝状导体，并且在其厚度方向上刺穿绝缘基材。 由布线层部分构成的垫相对地设置在芯基板的两个表面上，并且以多个丝状导体的相对端电连接，使得焊盘共享丝状导体。 通过焊盘制造芯基板的一个表面侧和另一个表面侧之间的布线连接。 绝缘基材由无机电介质制成。 由布线层的一部分制成的垫片设置在芯基板的两个表面上，并且仅电连接到由多个丝状导体形成的不同组的相应一端侧。

    CONDUCTIVE STRUCTURES FOR MICROFEATURE DEVICES AND METHODS FOR FABRICATING MICROFEATURE DEVICES
    26.
    发明申请
    CONDUCTIVE STRUCTURES FOR MICROFEATURE DEVICES AND METHODS FOR FABRICATING MICROFEATURE DEVICES 有权
    用于微型装置的导电结构和用于制造微型装置的方法

    公开(公告)号：US20120302054A1

    公开(公告)日：2012-11-29

    申请号：US13538891

    申请日：2012-06-29

    Applicant: Mark S. Johnson

    Inventor： Mark S. Johnson

    IPC: H01L21/768

    CPC classification number: H05K3/428 ,  H01L21/4857 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/16227 ,  H05K1/0287 ,  H05K3/108 ,  H05K2201/09609 ,  H05K2201/10378

    Abstract: Methods for fabricating conductive structures on and/or in interposing devices and microfeature devices that are formed using such methods are disclosed herein. In one embodiment, a method for fabricating interposer devices having substrates includes forming a plurality of conductive sections on a first substrate in a first pattern. The method continues by forming a plurality of conductive sections on a second substrate in a second pattern. The method further includes constructing a plurality of conductive lines in a common third pattern on both the first substrate and the second substrate. The conductive lines can be formed on the first and second substrates either before or after forming the first pattern of conductive sections on the first substrate and/or forming the second pattern of conductive sections on the second substrate.

    Abstract translation: 在此公开了使用这种方法形成的在和/或介入装置和微特征装置之间的导电结构的制造方法。 在一个实施例中，一种用于制造具有衬底的插入器器件的方法包括以第一图案在第一衬底上形成多个导电部分。 该方法通过在第二图案的第二基板上形成多个导电部分来继续。 该方法还包括在第一基板和第二基板上在公共第三图案中构造多条导线。 导电线可以在形成第一衬底上的第一导电部分图案之前或之后形成在第一衬底和第二衬底上，和/或在第二衬底上形成导电部分的第二图案。

    Circuit board and radiating heat system for circuit board
    27.
    发明授权
    Circuit board and radiating heat system for circuit board 失效
    电路板电路板和辐射热系统

    公开(公告)号：US08319107B2

    公开(公告)日：2012-11-27

    申请号：US12162740

    申请日：2007-02-07

    Applicant: Ki-Geon Lee

    Inventor： Ki-Geon Lee

    IPC: H05K7/20

    CPC classification number: H05K1/0206 ,  H05K1/116 ,  H05K3/0061 ,  H05K3/3447 ,  H05K3/42 ,  H05K2201/09609 ,  H05K2201/09781 ,  H05K2201/0979 ,  H05K2201/10106 ,  H05K2201/10303 ,  H05K2201/10651

    Abstract: A circuit board and a heat radiating system of the circuit board. In the circuit board, a plurality of conductive layer regions coated with a conductor are separately formed on both sides of an insulating substrate, the conductive layer region formed on either side of an insulating region on each of the both sides of the insulating substrate, the plurality of the conductive layer regions includes a plurality of through holes which penetrate through the insulating substrate and are coated with a conductor over an inner wall, the conductor in the through hole electrically conducts the coated conductor of the plurality of the conductive layer regions, one of the lead pins is connected to one of the separated conductive layer regions on the both sides based on the insulating region, and the other lead pin is connected to the other conductive layer region. Accordingly, the efficient heat radiation of the circuit board can prevent the component malfunction, the lifespan reduction, the power consumption increase, and the illuminance drop.

    Abstract translation: 电路板的电路板和散热系统。 在电路基板中，在绝缘基板的两面分别形成涂布有导体的多个导电层区域，在绝缘基板的两侧的绝缘区域的两侧形成的导电层区域， 多个导电层区域包括穿过绝缘基板并在内壁上涂覆有导体的多个通孔，通孔中的导体导电多个导电层区域的涂覆导体，一个 基于绝缘区域将引线引脚连接到两侧的分离的导电层区域中的一个，另一个引脚与另一个导电层区域连接。 因此，电路板的高效散热可以防止元件故障，寿命降低，功率消耗增加和照度下降。

    CAPACITOR-INCORPORATED SUBSTRATE AND COMPONENT-INCORPORATED WIRING SUBSTRATE
    28.
    发明申请
    CAPACITOR-INCORPORATED SUBSTRATE AND COMPONENT-INCORPORATED WIRING SUBSTRATE 有权
    电容器合并基板和元器件并联导线基板

    公开(公告)号：US20120241906A1

    公开(公告)日：2012-09-27

    申请号：US13389364

    申请日：2010-08-04

    Applicant: Naoya Nakanishi

    Inventor： Naoya Nakanishi

    IPC: H01L29/92

    CPC classification number: H05K1/0231 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/09345 ,  H05K2201/09609 ,  H05K2201/09627 ,  H05K2201/10674

    Abstract: An object of the present invention is to provide a capacitor-incorporated wiring substrate in which connection reliability can be improved through ensuring of a path for supply of electric potential even upon occurrence of a faulty connection in a via-conductor group. In a capacitor-incorporated wiring substrate of the present invention, a capacitor 50 is accommodated in a core 11, and a first and a second buildup layers 12 and 13 are formed on the upper and lower sides, respectively, of the capacitor 50. The capacitor-incorporated wiring substrate has a first via-conductor group to be connected to a first electric potential, and a second via-conductor group to be connected to a second electric potential. A first electrode pattern connected to the first via-conductor group, and a plurality of second electrode patterns connected to the second via-conductor group, are formed in a front-surface electrode layer 51 of the capacitor 50. A first conductor pattern connected to the first via-conductor group, and a plurality of second conductor patterns connected to the second via-conductor group, are formed in a proximate conductor layer 31 of a first buildup layer 12. Each of the second electrode patterns and each of the second conductor patterns connect a predetermined number of via electrodes and extend in such a manner as to be orthogonal to each other.

    Abstract translation: 本发明的目的是提供一种通过确保即使在通孔导体组中发生故障连接而产生电位的路径也可以提高连接可靠性的电容器配线布线基板。 在本发明的电容器配线基板中，电容器50容纳在芯体11中，在电容器50的上侧和下侧分别形成有第一和第二堆积层12和13。 电容器配合的布线基板具有要连接到第一电位的第一通孔导体组和要连接到第二电位的第二通孔导体组。 连接到第一通孔导体组的第一电极图案和连接到第二通孔导体组的多个第二电极图案形成在电容器50的前表面电极层51中。第一导体图案连接到 第一通孔导体组以及连接到第二通孔导体组的多个第二导体图案形成在第一堆积层12的邻近的导体层31中。每个第二电极图案和每个第二导体 图案连接预定数量的通孔电极并以彼此正交的方式延伸。

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