公开(公告)号：US20170223837A1

公开(公告)日：2017-08-03

申请号：US15487547

申请日：2017-04-14

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shigeru TAGO ,  Hirofumi SHINAGAWA ,  Yuki WAKABAYASHI

IPC: H05K1/18 ,  H01L23/538 ,  H05K1/11 ,  H05K3/46 ,  H05K1/03 ,  H05K1/09

CPC classification number: H05K1/186 ,  H01L23/5389 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/19105 ,  H05K1/024 ,  H05K1/03 ,  H05K1/0313 ,  H05K1/09 ,  H05K1/11 ,  H05K1/111 ,  H05K1/165 ,  H05K1/185 ,  H05K3/4626 ,  H05K3/4644 ,  H05K2201/0129 ,  H05K2201/10 ,  H05K2201/10015 ,  H05K2201/10098 ,  H05K2203/063 ,  H01L2924/00

Abstract: A component built-in substrate incorporates a chip capacitor in a multilayer substrate including laminated base material layers made of thermoplastic resin. The chip capacitor includes an uneven portion including a recessed portion and a projected portion on one side in a laminated direction. On one side of the chip capacitor in the multilayer substrate, a density of low fluid member with a melting point higher than a fluidization temperature of the base material layers is higher in a region overlapping the recessed portion of the chip capacitor than in a region overlapping the projected portion of the chip capacitor when viewed in the lamination direction.

公开(公告)号：US20170065734A1

公开(公告)日：2017-03-09

申请号：US15119966

申请日：2015-01-21

Applicant: Tetra Laval Holdings & Finance S.A.

Inventor： Iosif IZRAILIT

IPC: A61L2/08 ,  B65B55/08 ,  H05K7/20

CPC classification number: A61L2/087 ,  B65B55/08 ,  H05K1/11 ,  H05K1/185 ,  H05K3/285 ,  H05K7/20463 ,  H05K2201/10 ,  H05K2201/10151 ,  H05K2203/1377

Abstract: Power supply unit, in particular for a sterilization device, comprising at least one electric component, wherein, at least one of the electric components is at least partly covered with a solid insulation layer, wherein the solid insulation layer is adapted to provide an electric insulation.

Abstract translation: 电源单元，特别是用于消毒装置，包括至少一个电气部件，其中，所述电气部件中的至少一个至少部分地被固体绝缘层覆盖，其中所述固体绝缘层适于提供电绝缘 。

公开(公告)号：US20160219712A1

公开(公告)日：2016-07-28

申请号：US14991608

申请日：2016-01-08

Applicant: Samsung-Electro-Mechanics Co., Ltd.

Inventor： Kyung-Hwan Ko ,  Young-Gwan Ko ,  Jae-Ean Lee ,  Jee-Soo Mok ,  Yong-Ho Baek

IPC: H05K1/18 ,  H05K3/46 ,  H05K3/32 ,  H05K1/11 ,  H05K3/30

CPC classification number: H05K1/183 ,  H01L24/14 ,  H01L24/17 ,  H01L24/49 ,  H01L2224/14 ,  H01L2224/16225 ,  H01L2224/17 ,  H01L2224/48091 ,  H01L2224/49109 ,  H01L2224/73257 ,  H01L2924/00014 ,  H05K1/115 ,  H05K1/162 ,  H05K1/182 ,  H05K1/185 ,  H05K3/284 ,  H05K3/4697 ,  H05K2201/0919 ,  H05K2201/09381 ,  H05K2201/10 ,  H05K2201/10007 ,  H05K2201/10022 ,  H05K2201/1003 ,  H01L2224/45099

Abstract: A printed circuit board including an electronic component and a method of producing the same are provided. The printed circuit board includes a multilayered substrate including an insulation layer and an inner circuit layer laminated therein, a cavity disposed in the multilayered substrate, a via disposed in the insulation layer and configured to electrically connect the inner circuit layer with another inner circuit layer, a first electronic component inserted in the cavity, and a bump pad disposed on a surface of the cavity facing the first electronic component, and the bump pad is formed by having the insulation layer and the via exposed to a lateral side of the cavity.

Abstract translation: 提供一种包括电子部件的印刷电路板及其制造方法。 印刷电路板包括：多层基板，包括层压在其中的绝缘层和内部电路层;设置在所述多层基板中的空腔;布置在所述绝缘层中并且构造成将所述内部电路层与另一内部电路层电连接的通孔， 插入该空腔中的第一电子部件和设置在面向第一电子部件的空腔的表面上的凸块焊盘，并且通过使绝缘层和通孔暴露于空腔的侧面而形成凸块焊盘。

公开(公告)号：US20160219709A1

公开(公告)日：2016-07-28

申请号：US14990046

申请日：2016-01-07

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Joon-Sung LEE ,  Yong-Sam LEE ,  Seok-Hwan AHN ,  Jae-Hoon CHOI

IPC: H05K1/18 ,  H05K1/02 ,  H05K3/30 ,  H05K3/00 ,  H05K3/46 ,  H05K1/11 ,  H05K1/03

CPC classification number: H05K1/186 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/113 ,  H05K1/185 ,  H05K3/284 ,  H05K3/4697 ,  H05K2201/10 ,  H05K2201/10015 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00

Abstract: Disclosed is an embedded board and a method of manufacturing the same. The embedded board may include an insulating layer a first circuit layer formed inside the insulating layer a second circuit layer formed on an upper part of the first circuit layer, and the second circuit layer being disposed inside the insulating layer, a first electronic element arranged inside the insulating layer, the first electronic element being spaced apart from the second circuit layer, a metal pillar formed between the first circuit layer and the second circuit layer or the first electronic element, and a first via formed on the upper part of the second circuit layer inside the insulating layer.

Abstract translation: 公开了一种嵌入式电路板及其制造方法。 嵌入式板可以包括绝缘层，第一电路层，形成在绝缘层的内部，形成在第一电路层的上部的第二电路层，第二电路层设置在绝缘层的内部，第一电子元件设置在内部 绝缘层，第一电子元件与第二电路层间隔开，形成在第一电路层和第二电路层或第一电子元件之间的金属柱，以及形成在第二电路的上部的第一通孔 绝缘层内层。

公开(公告)号：US09345146B2

公开(公告)日：2016-05-17

申请号：US12591549

申请日：2009-11-23

Applicant: Bongyoung Kim

Inventor： Bongyoung Kim

IPC: H01M14/00 ,  H05K1/00 ,  H05K1/09 ,  H05K3/24 ,  H01M2/26 ,  H05K3/32 ,  H05K3/06 ,  H05K3/28 ,  H01M10/42 ,  H05K3/00

CPC classification number: H05K3/244 ,  H01M2/26 ,  H01M10/425 ,  H05K1/00 ,  H05K3/0023 ,  H05K3/064 ,  H05K3/28 ,  H05K3/328 ,  H05K2201/10 ,  H05K2201/10037 ,  H05K2203/1115

Abstract: A secondary battery and to a circuit board for the secondary battery. The circuit board having a structure for enhancing the safety of a secondary battery, and a secondary battery with the same. The circuit board for a secondary battery includes an insulation layer, a terminal pad layer formed on the insulation layer, and a plating layer formed on the terminal pad layer. The thickness of the plating layer is greater than 20 micrometers. The plating layer is made of nickel. The secondary battery further includes a circuit protection device, and a bare cell electrically connected to the circuit protection device, wherein circuit protection device including a first lead plate electrically connected to the plating layer of the circuit board, the plating layer of the circuit board being made of the same material as that of the first lead plate of the circuit protection device.

Abstract translation: 二次电池和用于二次电池的电路板。 具有用于增强二次电池的安全性的结构的电路板和具有该二次电池的二次电池。 用于二次电池的电路板包括绝缘层，形成在绝缘层上的端子焊盘层和形成在端子焊盘层上的镀层。 镀层的厚度大于20微米。 镀层由镍制成。 二次电池还包括电路保护装置和电连接到电路保护装置的裸电池，其中电路保护装置包括电连接到电路板的镀层的第一引线板，电路板的镀层为 由与电路保护装置的第一引线板相同的材料制成。

公开(公告)号：US20160037645A1

公开(公告)日：2016-02-04

申请号：US14807598

申请日：2015-07-23

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Jae Ean LEE ,  Jee Soo MOK ,  Young Gwan KO ,  Kyung Hwan KO ,  Yong Ho BAEK

IPC: H05K1/18 ,  H05K1/02 ,  H05K3/46 ,  H05K3/30 ,  H05K3/40 ,  H05K1/11 ,  H05K3/24

CPC classification number: H05K3/4697 ,  H01L2224/16225 ,  H05K1/185 ,  H05K1/186 ,  H05K3/24 ,  H05K3/4602 ,  H05K3/4617 ,  H05K2201/096 ,  H05K2201/10

Abstract: An embedded board and a method of manufacturing the same are provided. The embedded board includes a core substrate below which a mounting pad is formed, a first substrate formed below the core substrate and having a first cavity formed therein, and a second substrate formed below the first substrate and having a second cavity formed therein. The first cavity and the second cavity are connected to each other and externally expose the mounting pad.

Abstract translation: 提供嵌入式电路板及其制造方法。 嵌入式基板包括芯基板，在其下方形成有安装焊盘，第一基板形成在芯基板下方并且具有形成在其中的第一腔体，第二基板形成在第一基板下方并且在其中形成有第二腔。 第一腔体和第二腔体彼此连接并从外部暴露安装垫。

公开(公告)号：US11882660B2

公开(公告)日：2024-01-23

申请号：US18095511

申请日：2023-01-10

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Fan Chen ,  Chien-Hao Wang

IPC: H05K1/18 ,  H01L21/48 ,  H01L23/538 ,  H01L21/56

CPC classification number: H05K1/183 ,  H01L21/486 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/5383 ,  H01L23/5386 ,  H01L2224/04105 ,  H01L2924/11 ,  H01L2924/15153 ,  H05K2201/10

Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.

公开(公告)号：US20230164920A1

公开(公告)日：2023-05-25

申请号：US18095511

申请日：2023-01-10

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Fan CHEN ,  Chien-Hao WANG

IPC: H05K1/18 ,  H01L21/48 ,  H01L23/538 ,  H01L21/56

CPC classification number: H05K1/183 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/5383 ,  H01L21/568 ,  H01L23/5386 ,  H05K2201/10 ,  H01L2924/15153 ,  H01L2224/04105 ,  H01L2924/11

Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.

公开(公告)号：US20190254168A1

公开(公告)日：2019-08-15

申请号：US16397594

申请日：2019-04-29

Applicant: TT Electronics PLC

Inventor： Brent Hans Larson ,  Shivesh Langhanoja

IPC: H05K1/18 ,  G01L19/00 ,  H05K3/32 ,  H05K1/11 ,  H05K1/09 ,  H05K3/28 ,  H05K1/02

CPC classification number: H05K1/185 ,  G01L13/025 ,  G01L19/0007 ,  G01L19/0076 ,  G01L19/148 ,  H05K1/0272 ,  H05K1/09 ,  H05K1/111 ,  H05K1/115 ,  H05K1/16 ,  H05K1/18 ,  H05K1/181 ,  H05K3/28 ,  H05K3/32 ,  H05K7/02 ,  H05K2201/037 ,  H05K2201/10 ,  H05K2201/10151 ,  H05K2203/1327 ,  H05K2203/308

Abstract: A sensor device includes a printed circuit board (PCB) substrate having a top surface, a bottom surface, a slot between the top and bottom surfaces, and two holes through the top surface and reaching into the slot. The sensor device further includes a sensor chip mounted on the top surface of the PCB substrate and above one of the two holes. The sensor device further includes a molding compound covering the sensor chip and sidewall surfaces and the top surface of the PCB substrate.

公开(公告)号：US09972599B2

公开(公告)日：2018-05-15

申请号：US14558955

申请日：2014-12-03

Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.

Inventor： Shih-Ping Hsu ,  Chao-Chung Tseng

IPC: H05K1/18 ,  H01L25/065 ,  H01L23/00 ,  H01L21/683 ,  H01L25/16 ,  H01L25/00 ,  H01L23/538 ,  H05K3/46 ,  H01L23/28 ,  H01L23/29 ,  H05K3/00 ,  H01L23/498 ,  H01L21/48 ,  H05K1/16 ,  H05K3/28 ,  H01L23/50 ,  H05K1/02 ,  H05K3/34

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16112 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2924/15153 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/0231 ,  H05K1/162 ,  H05K1/183 ,  H05K1/185 ,  H05K3/0032 ,  H05K3/0044 ,  H05K3/284 ,  H05K3/3431 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/10 ,  H05K2201/10007 ,  H05K2201/10015 ,  H05K2201/1003 ,  H05K2201/10037 ,  H05K2201/10545 ,  Y10T29/49131 ,  H01L2924/014

Abstract: A method of manufacturing a package structure is provided, including forming a first wiring layer on a carrier board, forming up plurality of first conductors on the first wiring layer, forming a first insulating layer that encapsulates the first wiring layer and the first conductors, forming a second wiring layer on the first insulating layer, forming a plurality of second conductors on the second wiring layer, forming a second insulating layer that encapsulates the second wiring layer and the second conductors, and forming at least an opening on the second insulating layer for at least one electronic component to be disposed therein. Since the first and second insulating layers are formed before the opening, there is no need of stacking or laminating a substrate that already has an opening, and the electronic component will not be laminated and make a displacement. Therefore, the package structure thus manufactured has a high yield rate. The present invention further provides the package structure.