公开(公告)号：US6133534A

公开(公告)日：2000-10-17

申请号：US234215

申请日：1994-04-27

Applicant: Naoki Fukutomi ,  Hidehiro Nakamura ,  Hajime Nakayama ,  Yoshiaki Tsubomatsu ,  Masanori Nakamura ,  Kouichi Kaitou ,  Atsushi Kuwano ,  Itsuo Watanabe ,  Masahiko Itabashi

Inventor： Naoki Fukutomi ,  Hidehiro Nakamura ,  Hajime Nakayama ,  Yoshiaki Tsubomatsu ,  Masanori Nakamura ,  Kouichi Kaitou ,  Atsushi Kuwano ,  Itsuo Watanabe ,  Masahiko Itabashi

IPC: G01R1/073 ,  H05K3/04 ,  H05K3/06 ,  H05K3/20 ,  H05K3/40 ,  H05K3/46 ,  H05K1/09

CPC classification number: G01R1/07314 ,  H05K3/205 ,  H05K3/4007 ,  H05K3/4647 ,  H05K3/4658 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0367 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09781 ,  H05K2203/0152 ,  H05K2203/025 ,  H05K2203/0369 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0726 ,  H05K2203/0733 ,  H05K2203/1476 ,  H05K3/04 ,  H05K3/062 ,  H05K3/20 ,  H05K3/4652 ,  Y10S439/931

Abstract: A wiring board for electrical tests; having an insulating substrate, wiring of predetermined pattern which is embedded in the insulating substrate, and bump electrodes which are formed on the wiring and which are respectively brought into contact with corresponding electrodes of an article to-be-tested. Thus, even when the electrode pitch of the article to-be-tested such as a semiconductor device has become smaller(for example, less than 0.1 [mm]), the electrodes can be formed so as to cope with the electrical tests of the article.

Abstract translation: 用于电气测试的接线板; 具有绝缘基板，嵌入在绝缘基板中的预定图案的布线以及形成在布线上并且分别与要测试的物品的相应电极接触的突起电极。 因此，即使当诸如半导体器件的待测试物品的电极间距变得更小（例如，小于0.1 [mm]）时，也可以形成电极，以便应对电气测试 文章。

公开(公告)号：US6098271A

公开(公告)日：2000-08-08

申请号：US262386

申请日：1999-03-04

Applicant: Jinzo Yamamoto ,  Masahiro Hasumi ,  Tomoji Sugawa

Inventor： Jinzo Yamamoto ,  Masahiro Hasumi ,  Tomoji Sugawa

IPC: G11B5/48 ,  H05K3/36 ,  H05K3/40 ,  G11B5/42

CPC classification number: G11B5/4846 ,  H05K3/363 ,  H05K2201/0367 ,  H05K2201/0969 ,  H05K2201/09736 ,  H05K2201/09745 ,  H05K3/4007 ,  Y10T29/4903

Abstract: A method for assembling a magnetic disk drive with a relaying flexible printed circuit sheet and an actuator includes shaping at least one metal bump to form a first terminal on the relaying flexible printed circuit sheet. The shape of the metal bump determines the amount of solder that will adhere to the metal bump. This amount must be adequate to form an efficient electrical and mechanical connection between the first terminal and a second terminal on the actuator. The next step is laying solder on the metal bump so that the adequate amount of solder remains on the metal bump and forms a solder layer. After the solder layer is formed on the metal bump, the first terminal is placed on the second terminal so that the solder is squeezed between the first and second terminals.

Abstract translation: 一种用于组装具有中继柔性印刷电路板和致动器的磁盘驱动器的方法包括成形至少一个金属凸块以在中继柔性印刷电路板上形成第一端子。 金属凸块的形状确定将粘附到金属凸块的焊料的量。 该量必须足以在第一端子和致动器上的第二端子之间形成有效的电气和机械连接。 下一步是在金属凸块上铺设焊料，使得足够量的焊料保留在金属凸块上并形成焊料层。 在金属凸块上形成焊料层之后，将第一端子放置在第二端子上，使得焊料在第一和第二端子之间被挤压。

公开(公告)号：US6091251A

公开(公告)日：2000-07-18

申请号：US888448

申请日：1997-07-07

Applicant: Alan G. Wood ,  Tim J. Corbett ,  Gary L. Chadwick ,  Chender Huang ,  Larry D. Kinsman

Inventor： Alan G. Wood ,  Tim J. Corbett ,  Gary L. Chadwick ,  Chender Huang ,  Larry D. Kinsman

IPC: G01R1/04 ,  G01R1/067 ,  G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  H01L21/60 ,  H01L21/66 ,  H01L21/68 ,  H01L23/13 ,  H01L23/498 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42

CPC classification number: G01R31/2893 ,  G01R1/0466 ,  G01R1/0483 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/80 ,  H05K3/4007 ,  G01R3/00 ,  G01R31/2863 ,  H01L2224/16145 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/15787 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/423

Abstract: A reusable burn-in/test fixture for discrete TAB die consists of two halves. The first half of the test fixture contains cavity in which die is inserted. When the two halves are assembled, the fixture establishes electrical contact with the die and with a burn-in oven. The test fixture need not be opened until the burn-in and electrical test are completed. The fixture permits the die to be characterized prior to assembly.

Abstract translation: 用于离散TAB模具的可重复使用的老化/测试夹具由两半组成。 测试夹具的前半部分包含插入模具的腔体。 当组装两个半部时，夹具与模具建立电接触，并与老化烘箱连接。 在老化和电气测试完成之前，测试夹具不需要打开。 夹具允许在组装之前对模具进行表征。

公开(公告)号：US6051093A

公开(公告)日：2000-04-18

申请号：US11603

申请日：1998-02-06

Applicant: Norihito Tsukahara

Inventor： Norihito Tsukahara

IPC: H01L21/60 ,  H01L21/56 ,  H01L23/485 ,  H01L23/498 ,  H05K1/00 ,  H05K1/11 ,  H05K3/32 ,  H05K3/40 ,  B32B31/00 ,  H01L21/00

CPC classification number: H01L24/29 ,  H01L21/563 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/743 ,  H01L24/75 ,  H01L24/83 ,  H05K1/113 ,  H05K3/321 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05572 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/29298 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/3511 ,  H05K1/0393 ,  H05K2201/0367 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/1189 ,  H05K3/4069 ,  Y10T156/1054 ,  Y10T156/1062 ,  Y10T156/107 ,  Y10T156/109 ,  Y10T156/1092 ,  Y10T29/4913 ,  Y10T29/49165

Abstract: A mounting method of a semiconductor element capable of joining an electrode of a semiconductor element and a circuit board at high reliability. The method includes a step of forming an external electrode terminal by filling a hole formed in circuit board with a conductive paste, a step of positioning the external electrode terminal and a protruding bump formed on an electrode of a semiconductor, and a step of pressing the semiconductor element to contact between the conductive paste in the hole and the protruding bump thereby electrically connecting the electrode of the semiconductor element and the external electrode terminal of the circuit board. An adhesive sheet of a thermosetting resin, a thermoplastic resin, or a mixed thermosetting and thermoplastic resin may be disposed on the circuit board where the bump breaks through the sheet to contact the paste.

Abstract translation: PCT No.PCT / JP97 / 01971 Sec。 371日期1998年2月6日 102（e）日期1998年2月6日PCT提交1997年6月6日PCT公布。 出版物WO97 / 47031 日期1997年12月11日能够以高可靠性接合半导体元件的电极和电路基板的半导体元件的安装方法。 该方法包括通过用导电膏填充形成在电路板中的孔来形成外部电极端子的步骤，将外部电极端子定位的步骤和形成在半导体的电极上的突起凸起的步骤，以及按压 半导体元件在孔中的导电膏与突出凸起之间接触，从而将半导体元件的电极和电路板的外部电极端子电连接。 可以在电路板上设置热固性树脂，热塑性树脂或混合的热固性和热塑性树脂的粘合片，其中凸块突破片材以接触糊料。

公开(公告)号：US06049977A

公开(公告)日：2000-04-18

申请号：US856991

申请日：1997-05-15

Applicant: Glen G. Atkins ,  Michael S. Cohen ,  Karl H. Mauritz ,  James M. Shaffer

Inventor： Glen G. Atkins ,  Michael S. Cohen ,  Karl H. Mauritz ,  James M. Shaffer

IPC: G01R31/28 ,  H05K1/09 ,  H05K3/34 ,  H05K3/40 ,  H01R9/09

CPC classification number: G01R31/2862 ,  G01R31/2886 ,  H05K3/4007 ,  G01R31/2863 ,  H05K1/095 ,  H05K2201/035 ,  H05K2201/0367 ,  H05K3/3457 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A method of forming electrically conductive pillars on a printed circuit board by providing a printed circuit board having a plurality of electrical traces and forming a plurality of elongate, electrically conductive pillars of superimposed layers of solder and conductive polymer on the printed circuit board. The elongate, electrically conductive pillars are connected by a first end to the electrical traces of the printed circuit board and extend substantially perpendicularly from the printed circuit board such that a second end of each of the plurality of elongate, electrically conductive pillars lies in substantially a common plane which is substantially perpendicular to and above said printed circuit board.

Abstract translation: 一种在印刷电路板上形成导电柱的方法，该方法是通过提供具有多个电迹线的印刷电路板，并在印刷电路板上形成多个细长导电的叠层焊料和导电聚合物的导电柱。 细长的导电柱通过第一端连接到印刷电路板的电迹线并且从印刷电路板基本上垂直地延伸，使得多个细长导电柱中的每一个的第二端基本上位于 基本上垂直于所述印刷电路板上方的公共平面。

公开(公告)号：US5949141A

公开(公告)日：1999-09-07

申请号：US898099

申请日：1997-07-22

Applicant: Warren M. Farnworth ,  David R. Hembree

Inventor： Warren M. Farnworth ,  David R. Hembree

IPC: H01L21/48 ,  H05K3/00 ,  H05K3/06 ,  H05K3/40 ,  H05K3/42 ,  H01L23/48

CPC classification number: H05K3/4007 ,  H01L21/4853 ,  H05K2201/0154 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/135 ,  H05K3/002 ,  H05K3/064 ,  H05K3/423 ,  Y02P80/30 ,  Y10S428/901 ,  Y10T428/31681

Abstract: A process for producing laminated film/metal structures comprising bumped circuit traces on a non-conductive substrate wherein a copper sheet/polyimide film laminate is coated with resist on the exterior surfaces. The resist adjacent the polyimide film is selectively exposed and etched to expose an area of the polyimide film. The exposed polyimide film is etched to form vias through the polyimide film to the inner side of the copper sheet. The resist adjacent the polyimide film is stripped away and a metal bump is electrolytically plated through each via onto the copper sheet. A subsequent layer of resist is electrophoretically applied over the bumps. The resist material adjacent the copper sheet is then selectively exposed and etched to expose areas of the copper sheet. The exposed copper sheet is etched to form circuit traces and the remaining resist adjacent both the polyimide film and the copper sheet is stripped away.

Abstract translation: 一种在非导电性基板上形成有凸起电路迹线的叠层膜/金属结构体的制造方法，其中铜片/聚酰亚胺膜层叠体在外表面上涂有抗蚀剂。 选择性地暴露和蚀刻邻近聚酰亚胺膜的抗蚀剂以暴露聚酰亚胺膜的区域。 蚀刻曝光的聚酰亚胺膜，以通过聚酰亚胺膜形成通孔至铜片的内侧。 剥离与聚酰亚胺膜相邻的抗蚀剂，并通过每个通孔将金属凸块电镀到铜片上。 随后的抗蚀剂层电泳施加在凸块上。 然后选择性地暴露和蚀刻邻近铜片的抗蚀剂材料以暴露铜片的区域。 将曝光的铜片蚀刻以形成电路迹线，并将与聚酰亚胺膜和铜片相邻的其余抗蚀剂剥离。

公开(公告)号：US5929521A

公开(公告)日：1999-07-27

申请号：US828255

申请日：1997-03-26

Applicant: James M. Wark ,  Salman Akram

Inventor： James M. Wark ,  Salman Akram

IPC: H01L21/60 ,  H01L23/485 ,  H01L23/498 ,  H05K3/32 ,  H05K3/40 ,  H01L23/48 ,  H01L23/52 ,  H01L29/46

CPC classification number: H01L24/10 ,  G01R1/06738 ,  H01L22/34 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/81 ,  H05K3/325 ,  H05K3/4007 ,  H01L2224/0401 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/1601 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L24/12 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15787 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/10734 ,  Y10T29/49147 ,  Y10T29/49155

Abstract: A bumped semiconductor device contact structure is disclosed including at least one non-planar contact pad having a plurality of projections extending therefrom for contacting at least one solder ball of a bumped integrated circuit (IC) device, such as a bumped die and a bumped packaged IC device. The projections are arranged to make electrical contact with the solder balls of a bumped IC device without substantially deforming the solder ball. Accordingly, reflow of solder balls to reform the solder balls is not necessary with the contact pad of the present invention. Such a contact pad may be provided on various testing equipment such as probes and the like and may be used for both temporary and permanent connections. Also disclosed is an improved method of forming the contact pads by etching and deposition.

Abstract translation: 公开了凸起的半导体器件接触结构，其包括至少一个非平面接触焊盘，其具有从其延伸的多个突起，用于接触凸起的集成电路（IC）器件的至少一个焊球，例如凸起的裸片和凸起的封装 IC设备。 突起被布置成与凸起的IC器件的焊球电接触，而不会使焊球基本上变形。 因此，本发明的接触焊盘不需要焊球的回流以重新形成焊球。 这样的接触垫可以设置在诸如探针等的各种测试设备上，并且可以用于临时和永久连接。 还公开了通过蚀刻和沉积形成接触焊盘的改进方法。

公开(公告)号：US5915755A

公开(公告)日：1999-06-29

申请号：US953711

申请日：1997-10-17

Applicant: Derek Gochnour ,  Warren M. Farnworth

Inventor： Derek Gochnour ,  Warren M. Farnworth

IPC: G01R1/04 ,  G01R1/067 ,  G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  H01L21/60 ,  H01L21/66 ,  H01L21/68 ,  H01L23/13 ,  H01L23/498 ,  H05K3/00 ,  H05K3/42 ,  H01R9/00

CPC classification number: H01L23/49838 ,  G01R1/0466 ,  G01R1/0483 ,  G01R31/2893 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L24/80 ,  H01L24/85 ,  H05K3/4007 ,  G01R1/06761 ,  G01R3/00 ,  G01R31/2831 ,  G01R31/2863 ,  H01L2224/16145 ,  H01L2224/85001 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/30105 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/423 ,  Y10T29/49121 ,  Y10T29/49144 ,  Y10T29/49149

Abstract: A method for forming an interconnect for establishing electrical communication with a semiconductor die is provided. The method includes: providing a microbump tape and then mounting the tape to a substrate with a compliant layer therebetween. The microbump tape includes an insulating film having a pattern of microbump contact members corresponding to a pattern of bond pads on the die. The compliant layer can be formed of a curable adhesive such as a silicone elastomer. A coupon containing a plurality of microbump tapes can be mounted to a substrate wafer which can then be singulated to form a plurality of interconnects. The interconnects can be used with a testing apparatus for testing unpackaged semiconductor dice.

Abstract translation: 提供一种用于形成用于与半导体管芯建立电连通的互连的方法。 该方法包括：提供微型胶带，然后将胶带安装到其上具有柔顺层的基材上。 微型胶带包括具有对应于模具上的接合焊盘图案的微型块接触部件图案的绝缘膜。 柔性层可以由可固化粘合剂如硅氧烷弹性体形成。 可以将包含多个微型带的试样安装到基板晶片上，然后可以将其分离以形成多个互连。 互连可用于测试未封装的半导体裸片的测试设备。

公开(公告)号：US5915753A

公开(公告)日：1999-06-29

申请号：US8494

申请日：1998-01-16

Applicant: Tomohisa Motomura ,  Osamu Shimada ,  Yoshitaka Fukuoka

Inventor： Tomohisa Motomura ,  Osamu Shimada ,  Yoshitaka Fukuoka

IPC: H01L21/48 ,  H01L21/60 ,  H01L23/12 ,  H05K1/11 ,  H05K1/18 ,  H05K3/06 ,  H05K3/24 ,  H05K3/34 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  H05K3/36

CPC classification number: H05K3/4617 ,  H01L21/4857 ,  H01L21/486 ,  H05K1/113 ,  H05K3/4007 ,  H05K3/4647 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/10674 ,  H05K2203/0733 ,  H05K2203/1189 ,  H05K3/243 ,  H05K3/423 ,  Y10T29/49126 ,  Y10T29/49153

Abstract: A method of producing a high-density wiring board for mounting comprises the steps of providing an electroconductive metallic film on the main surface thereof with a photosensitive resist layer, subjecting the photosensitive resist layer to selective exposure to light and development thereby forming holes for selectively exposing the surface of the electroconductive metallic foil in the photosensitive resist layer, depositing an electroconductive metal by plating on the exposed surface of the electroconductive metallic foil thereby forming electroconductive bumps thereon, peeling off the remainder of the photosensitive resist layer, superposing an insulating polymer sheet on the electroconductive bump forming surface, pressing the resultant superposed layers so that the electroconductive bumps to pierce the polymer sheet in the direction of thickness thereof and allowing the leading end parts of the electroconductive bumps to emerge from the polymer sheet and give rise to connecting terminal parts, and selectively etching off the electroconductive metallic foil thereby forming a wiring pattern.

Abstract translation: 一种制造用于安装的高密度布线板的方法包括以下步骤：在其主表面上提供导电金属膜，其具有光敏抗蚀剂层，使光敏抗蚀剂层选择性地曝光和显影，从而形成用于选择性曝光的孔 在感光性抗蚀剂层中的导电金属箔的表面，通过电镀在导电金属箔的暴露表面上沉积导电金属，从而在其上形成导电凸起，剥离光敏抗蚀剂层的其余部分，将绝缘聚合物片叠加在 导电凸块形成表面，压制所得到的叠置层，使得导电凸块在其厚度方向上刺穿聚合物片材，并允许导电凸起的前端部分从聚合物片材出射并产生连接 并且选择性地蚀刻掉导电金属箔，从而形成布线图案。

公开(公告)号：US5912510A

公开(公告)日：1999-06-15

申请号：US672389

申请日：1996-05-29

Applicant: Lih-Tyng Hwang ,  William H. Lytle

Inventor： Lih-Tyng Hwang ,  William H. Lytle

IPC: H01L21/60 ,  H01L23/485 ,  H05K3/28 ,  H05K3/32 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H05K3/321 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16237 ,  H01L2224/81141 ,  H01L2224/81801 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/04941 ,  H05K2201/0367 ,  H05K2201/09472 ,  H05K2201/10674 ,  H05K3/28

Abstract: A bonding structure (10) is formed between a first component (12) and a second component (11) to form a semiconductor device. The bonding structure (10) comprises a bump (24) that has a pedestal region (22) and a crown region (23). The crown region (23) is anchored into a well region (13) of a conductive material (16) that is formed on the second component (11).

Abstract translation: 在第一部件（12）和第二部件（11）之间形成接合结构（10）以形成半导体器件。 接合结构（10）包括具有基座区域（22）和冠部区域（23）的凸块（24）。 冠部区域（23）被锚定在形成在第二部件（11）上的导电材料（16）的阱区域（13）中。