公开(公告)号：US20220087017A1

公开(公告)日：2022-03-17

申请号：US17380121

申请日：2021-07-20

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Yin-Chen Lin ,  Ming-Hsiao Ke ,  Hui-Yu Huang ,  Chih-Ming Peng ,  Chun-Te Lee

IPC: H05K1/03 ,  H05K13/04 ,  H05K13/02

Abstract: A circuit board tape includes substrate units each including a sprocket-hole region, a layout region and a joining mark. There are odd and more than three sprocket holes on the sprocket-hole region. An imaginary line extended from the joining mark is extended to between a first layout and a second layout located on the layout region. The amount of the sprocket holes between the imaginary lines of the adjacent substrate units is odd. The circuit board tape is cut along the imaginary lines of the different substrate units so as to remove the defective substrate unit from the circuit board tape and divide the circuit board tape into a front tape and a rear tape. After joining the front and rear tapes, the region where a first layout on the front tape and a second layout on the rear tape are located is defined as a combined layout region.

公开(公告)号：US20220037166A1

公开(公告)日：2022-02-03

申请号：US17161818

申请日：2021-01-29

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chih-Ming Kuo ,  Lung-Hua Ho ,  You-Ming Hsu ,  Fei-Jain Wu

IPC: H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31

Abstract: A method of fabricating a semiconductor package includes the steps of: disposing semiconductor devices on a carrier; forming an encapsulation on the carrier to cover the semiconductor devices, a recession of the encapsulation includes a strengthening portion and a recessed portion, the strengthening portion protrudes from the recessed portion and surrounds the recessed portion; and removing the strengthening portion of the recession of the encapsulation.

公开(公告)号：US20210202422A1

公开(公告)日：2021-07-01

申请号：US16910461

申请日：2020-06-24

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Yu-Chen Ma ,  Hsin-Hao Huang ,  Wen-Fu Chou ,  Gwo-Shyan Sheu

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538

Abstract: A flip chip interconnection includes a circuit board, a chip and a solder layer. The chip is mounted on an inner bonding area of the circuit board, the solder layer is located between the circuit board and the chip for bonding bumps to inner leads and a T-shaped circuit unit on the inner bonding area. The T-shaped circuit unit has a main part, a connection part and a branch part, the connection part is connected to the main and branch parts, respectively. The main part extends along a lateral direction and the branch part extends outwardly along a longitudinal direction. The connection part is narrower than the main part in width so as to prevent solder short caused by solder overflow on the branch part.

公开(公告)号：US20210185800A1

公开(公告)日：2021-06-17

申请号：US16866796

申请日：2020-05-05

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Yi-Chen Lien ,  Yen-Ping Huang ,  Hui-Yu Huang ,  Chih-Ming Peng ,  Chun-Te Lee

IPC: H05K1/02 ,  H05K3/00

Abstract: A circuit board includes a substrate having a through hole, a circuit layer, a first measurement mark and a second measurement mark. According to the first and second measurement marks, an electronic detection device can measure a first distance between a first edge of the through hole and the first measurement mark and a second distance between a second edge of the through hole and the second measurement mark to determine whether the through hole has an undesired size or shift.

公开(公告)号：US10797213B2

公开(公告)日：2020-10-06

申请号：US16260528

申请日：2019-01-29

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chin-Tang Hsieh ,  Cheng-Hung Shih

IPC: H01L33/62 ,  H01L33/38

Abstract: A microchip is electrically connected to a substrate to become a chip package, preferably for LED. A chip of the package includes a body and at least one electrode which is disposed and exposed on a surface of the body. The electrode includes a confining groove and a confining wall. The confining wall is peripherally located around the confining groove and provided to confine at least one conductive particle of an adhesive in the confining groove. The electrode of the chip is electrically connected to a bonding pad of a substrate via the conductive particle confined in the confining groove.

公开(公告)号：US20190279926A1

公开(公告)日：2019-09-12

申请号：US15990747

申请日：2018-05-28

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chin-Tang Hsieh

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package includes a chip and a circuit substrate having leads. Each of the leads has an upper wide portion and a lower wide portion in a bonding area so as there are an upper notch and a lower notch in the bonding area. The upper and lower notches face toward the upper and lower wide portions of the adjacent lead, respectively. The upper and lower wide portions are designed to prevent defective bonding caused by shifting between the leads and the chip humps. Additionally, there are adequate etching spaces between the leads because the wide portions and the notches are staggered with each other such that incomplete etching between the leads is preventable during etching process.

公开(公告)号：US20190186037A1

公开(公告)日：2019-06-20

申请号：US15867878

申请日：2018-01-11

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Cheng-Hung Shih ,  Tsuo-Yun Chu ,  Xin-Wei Lo ,  Nian-Cih Yang

IPC: C25D21/04 ,  C25D17/06 ,  C25D5/08

Abstract: An electroplating system for depositing a plating material on an object includes a pressure device and an anode element. The pressure device includes a lid having first and second through holes and a base having a chamber, conduction holes and third through holes located in the chamber. Each of the conduction tubes includes a conduction hole connecting to one of the third through holes. The lid covers the chamber, the first through holes communicate with the chamber for spraying an electroplating solution toward the object and the second through holes reveal the conduction holes. A passage of electric force line is formed in the connected holes and the third through holes filled with the electroplating solution, and the anode element is located outside the passage of electric force line. The electroplating system can prevent defective plating and enhance plating efficiency.

公开(公告)号：US20180090379A1

公开(公告)日：2018-03-29

申请号：US15342241

申请日：2016-11-03

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chia-Jung Tu ,  Chih-Lung Chen ,  Wen-Hsiang Liao ,  Chung-Hsiang Wei ,  Yung-Chi Liu

IPC: H01L21/78 ,  H01L23/544 ,  H01L21/304

CPC classification number: H01L21/78 ,  H01L21/6835 ,  H01L2221/68327

Abstract: A wafer dicing method comprises providing a wafer and performing a cutting procedure and a contacting procedure. The wafer includes a plurality of dies and a metal layer, wherein the metal layer is formed on a scribe line which is formed between adjacent dies. A cutter is used to cut the metal layer along the scribe line during the cutting procedure to form a plurality of dies on the wafer, and the metal layer cut by the cutter remains a plurality of metal burrs on the dies. A brush is used to contact with the metal burrs along the cutting slot during the contracting procedure to prevent each of the metal burrs from protruding from a surface of each of the dies.

公开(公告)号：US09929051B1

公开(公告)日：2018-03-27

申请号：US15342241

申请日：2016-11-03

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chia-Jung Tu ,  Chih-Lung Chen ,  Wen-Hsiang Liao ,  Chung-Hsiang Wei ,  Yung-Chi Liu

IPC: H01L21/00 ,  H01L21/78 ,  H01L21/30 ,  H01L23/544 ,  H01L21/304

CPC classification number: H01L21/78 ,  H01L21/6835 ,  H01L2221/68327

Abstract: A wafer dicing method comprises providing a wafer and performing a cutting procedure and a contacting procedure. The wafer includes a plurality of dies and a metal layer, wherein the metal layer is formed on a scribe line which is formed between adjacent dies. A cutter is used to cut the metal layer along the scribe line during the cutting procedure to form a plurality of dies on the wafer, and the metal layer cut by the cutter remains a plurality of metal burrs on the dies. A brush is used to contact with the metal burrs along the cutting slot during the contracting procedure to prevent each of the metal burrs from protruding from a surface of each of the dies.

公开(公告)号：US09000569B2

公开(公告)日：2015-04-07

申请号：US14042976

申请日：2013-10-01

Applicant: Chipbond Technology Corporation

Inventor： Chin-Tang Hsieh ,  You-Ming Hsu ,  Ming-Sheng Liu ,  Chih-Ping Wang

IPC: H01L21/4763 ,  H01L23/00 ,  H01L23/28 ,  H01L23/532 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L23/28 ,  H01L23/3192 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a carrier, a first protective layer, a second protective layer, and a third protective layer. A first surface of the first protective layer comprises a first anti-stress zone. A first extension line from a first bottom edge intersects with a second extension line from a second bottom edge to form a first base point. A first projection line is formed on the first surface, an extension line of the first projection line intersects with the second bottom edge to form a first intersection point, a second projection line is formed on the first surface, and an extension line of the second projection line intersects with the first bottom edge to form a second intersection point. A zone by connecting the first base point, the first intersection point and the second intersection point is the first anti-stress zone.

Abstract translation: 半导体结构包括载体，第一保护层，第二保护层和第三保护层。 第一保护层的第一表面包括第一抗应力区。 来自第一底部边缘的第一延伸线与第二延伸线从第二底部边缘相交以形成第一基点。 第一投影线形成在第一表面上，第一投影线的延长线与第二底边缘相交形成第一交点，第二投影线形成在第一表面上，第二投影线形成在第二表面的延伸线上 投影线与第一底边相交形成第二交点。 通过连接第一基点，第一交点和第二交点的区域是第一抗应力区域。