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    Process for filling etched holes
    35.
    发明授权
    Process for filling etched holes 有权

    公开(公告)号：US09708183B2

    公开(公告)日：2017-07-18

    申请号：US15046239

    申请日：2016-02-17

    Applicant: Memjet Technology Ltd.

    Inventor： Angus North ,  Ronan O'Reilly ,  Gregory McAvoy

    IPC: B81C1/00 ,  B41J2/16

    CPC classification number: B81C1/00611 ,  B41J2/1603 ,  B41J2/1628 ,  B41J2/1631 ,  B41J2/1639 ,  B41J2/1645 ,  B81B2201/052 ,  B81B2203/0353 ,  B81C2201/0104 ,  B81C2201/0121

    Abstract: A process for filling one or more etched holes defined in a frontside surface of a wafer substrate. The process includes the steps of: (i) depositing a layer of a thermoplastic first polymer onto the frontside surface and into each hole; (ii) reflowing the first polymer; (iii) exposing the wafer substrate to a controlled oxidative plasma; (iv) optionally repeating steps (i) to (iii); (v) depositing a layer of a photoimageable second polymer; (vi) selectively removing the second polymer from regions outside a periphery of the holes using exposure and development; and (vii) planarizing the frontside surface to provide holes filled with a plug comprising the first and second polymers, which are different than each other. Each plug has a respective upper surface coplanar with the frontside surface.

    Method for adaptive feedback controlled polishing
    36.
    发明授权
    Method for adaptive feedback controlled polishing 有权
    自适应反馈控制抛光方法

    公开(公告)号：US09573243B2

    公开(公告)日：2017-02-21

    申请号：US14532338

    申请日：2014-11-04

    Applicant: Headway Technologies, Inc.

    Inventor： Terry Moore ,  Brant Nease

    IPC: C03C15/00 ,  C03C25/68 ,  H01L21/302 ,  H01L21/461 ,  H01L21/311 ,  B24B37/013 ,  B24B49/12 ,  H01L21/321 ,  H01L21/3105 ,  H01L21/66 ,  B81C99/00

    CPC classification number: B24B37/013 ,  B24B49/12 ,  B81C99/0065 ,  B81C2201/0104 ,  H01L21/302 ,  H01L21/31053 ,  H01L21/3212 ,  H01L22/12 ,  H01L22/26

    Abstract: An adaptive feedback control method is provided for a chemical mechanical polish process to minimize a dielectric layer clearing time difference between two annular regions on a substrate. An optical system with an optical window passes below the polishing pad and detects reflected light interference signals from at least two annular regions. A pre-clearing time difference is determined and is used to calculate an adjustment to one or both of a CMP head membrane pressure and a retaining ring pressure. The pressure adjustment is applied before the end of the polish cycle to avoid the need for a second polish cycle and to reduce a dishing difference and a resistance difference in a metal layer in the at least two annular regions. In some embodiments, a second pressure adjustment is performed before the end of the cycle and different CMP head membrane pressure adjustments are made in different pressure zones.

    Abstract translation: 提供了一种用于化学机械抛光工艺的自适应反馈控制方法，以最小化介电层清除衬底上的两个环形区域之间的时间差。 具有光学窗口的光学系统通过抛光垫下方并且检测来自至少两个环形区域的反射光干涉信号。 确定预清除时间差，并用于计算对CMP头膜压力和保持环压力之一或两者的调节。 在抛光循环结束之前施加压力调节，以避免需要第二抛光循环并且减少至少两个环形区域中的金属层中的凹陷差和电阻差。 在一些实施例中，在循环结束之前执行第二压力调节，并且在不同的压力区域中进行不同的CMP头部膜压力调节。

    Method of increasing MEMS enclosure pressure using outgassing material
    37.
    发明授权
    Method of increasing MEMS enclosure pressure using outgassing material 有权
    使用排气材料增加MEMS外壳压力的方法

    公开(公告)号：US09452925B2

    公开(公告)日：2016-09-27

    申请号：US14832786

    申请日：2015-08-21

    Applicant: InvenSense, Inc.

    Inventor： Cerina Zhang ,  Martin Lim ,  Jongwoo Shin ,  Joseph Seeger

    IPC: H01L23/02 ,  H01L21/54 ,  B81C1/00 ,  B81B7/02

    CPC classification number: B81C1/00301 ,  B81B7/007 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C1/0023 ,  B81C1/00238 ,  B81C1/00246 ,  B81C1/00269 ,  B81C2201/0104 ,  B81C2201/0132 ,  B81C2203/0145 ,  B81C2203/019 ,  B81C2203/035 ,  B81C2203/0792

    Abstract: Semiconductor manufacturing processes include providing a first substrate having a first passivation layer disposed above a patterned top-level metal layer, and further having a second passivation layer disposed over the first passivation layer; the second passivation layer has a top surface. The processes further include forming an opening in a first portion of the second passivation layer, and the opening exposes a portion of a surface of the first passivation layer. The processes further include patterning the second and first passivation layers to expose portions of the patterned top-level metal layer and bonding a second substrate and the first substrate to each other. The bonding occurs within a temperature range in which at least the exposed portion of the first passivation layer undergoes outgassing.

    Abstract translation: 半导体制造工艺包括提供第一衬底，其具有设置在图案化顶层金属层上方的第一钝化层，并且还具有设置在第一钝化层上的第二钝化层; 第二钝化层具有顶表面。 所述方法还包括在第二钝化层的第一部分中形成开口，并且开口暴露第一钝化层的表面的一部分。 所述方法还包括图案化第二钝化层和第一钝化层以暴露图案化顶层金属层的部分并将第二衬底和第一衬底彼此结合。 接合发生在至少第一钝化层的暴露部分经历脱气的温度范围内。

    PROCESS FOR FILLING ETCHED HOLES
    38.
    发明申请
    PROCESS FOR FILLING ETCHED HOLES 有权
    填充蚀刻孔的方法

    公开(公告)号：US20160236930A1

    公开(公告)日：2016-08-18

    申请号：US15046239

    申请日：2016-02-17

    Applicant: Memjet Technology Ltd.

    Inventor： Angus North ,  Ronan O'Reilly ,  Gregory McAvoy

    IPC: B81C1/00

    CPC classification number: B81C1/00611 ,  B41J2/1603 ,  B41J2/1628 ,  B41J2/1631 ,  B41J2/1639 ,  B41J2/1645 ,  B81B2201/052 ,  B81B2203/0353 ,  B81C2201/0104 ,  B81C2201/0121

    Abstract: A process for filling one or more etched holes defined in a frontside surface of a wafer substrate. The process includes the steps of: (i) depositing a layer of a thermoplastic first polymer onto the frontside surface and into each hole; (ii) reflowing the first polymer; (iii) exposing the wafer substrate to a controlled oxidative plasma; (iv) optionally repeating steps (i) to (iii); (v) depositing a layer of a photoimageable second polymer; (vi) selectively removing the second polymer from regions outside a periphery of the holes using exposure and development; and (vii) planarizing the frontside surface to provide holes filled with a plug comprising the first and second polymers, which are different than each other. Each plug has a respective upper surface coplanar with the frontside surface.

    Abstract translation: 一种用于填充限定在晶片衬底的前表面中的一个或多个蚀刻孔的工艺。 该方法包括以下步骤：（i）将热塑性第一聚合物层沉积到前表面和每个孔中; （ii）回流第一聚合物; （iii）将晶片衬底暴露于受控氧化等离子体; （iv）任选地重复步骤（i）至（iii）; （v）沉积可光成像的第二聚合物层; （vi）使用曝光和显影从所述孔的外周边区域选择性地除去所述第二聚合物; 和（vii）平面化前侧表面以提供填充有彼此不同的第一和第二聚合物的塞子的孔。 每个插头具有与前侧表面共面的相应的上表面。

    Method for Adaptive Feedback Controlled Polishing
    39.
    发明申请
    Method for Adaptive Feedback Controlled Polishing 有权
    自适应反馈控制抛光方法

    公开(公告)号：US20160121451A1

    公开(公告)日：2016-05-05

    申请号：US14532338

    申请日：2014-11-04

    Applicant: Headway Technologies, Inc.

    Inventor： Terry Moore ,  Brant Nease

    IPC: B24B37/013 ,  B24B49/12

    CPC classification number: B24B37/013 ,  B24B49/12 ,  B81C99/0065 ,  B81C2201/0104 ,  H01L21/302 ,  H01L21/31053 ,  H01L21/3212 ,  H01L22/12 ,  H01L22/26

    Abstract: An adaptive feedback control method is provided for a chemical mechanical polish process to minimize a dielectric layer clearing time difference between two annular regions on a substrate. An optical system with an optical window passes below the polishing pad and detects reflected light interference signals from at least two annular regions. A pre-clearing time difference is determined and is used to calculate an adjustment to one or both of a CMP head membrane pressure and a retaining ring pressure. The pressure adjustment is applied before the end of the polish cycle to avoid the need for a second polish cycle and to reduce a dishing difference and a resistance difference in a metal layer in the at least two annular regions. In some embodiments, a second pressure adjustment is performed before the end of the cycle and different CMP head membrane pressure adjustments are made in different pressure zones.

    Abstract translation: 提供了一种用于化学机械抛光工艺的自适应反馈控制方法，以最小化介电层清除衬底上的两个环形区域之间的时间差。 具有光学窗口的光学系统通过抛光垫下方并且检测来自至少两个环形区域的反射光干涉信号。 确定预清除时间差，并用于计算对CMP头膜压力和保持环压力之一或两者的调节。 在抛光循环结束之前施加压力调节，以避免需要第二抛光循环并且减少至少两个环形区域中的金属层中的凹陷差和电阻差。 在一些实施例中，在循环结束之前执行第二压力调节，并且在不同的压力区域中进行不同的CMP头部膜压力调节。

    Semiconductor device and method of manufacturing the same
    40.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08211751B2

    公开(公告)日：2012-07-03

    申请号：US12810279

    申请日：2008-12-12

    Applicant: Satoshi Yamamoto ,  Hirokazu Hashimoto

    Inventor： Satoshi Yamamoto ,  Hirokazu Hashimoto

    IPC: H01L21/50

    CPC classification number: B81C1/00317 ,  B81C2201/0104 ,  B81C2201/0108 ,  B81C2201/0125 ,  B81C2203/0118 ,  B81C2203/0145 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14683 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of manufacturing a semiconductor device includes: a bonding step of bonding a first substrate with optical transparency and a second substrate having a surface on which a functional element is provided to each other such that the functional element faces the first substrate; a thinning step of thinning at least one of the first and second substrates; and a through-hole forming step of forming a cavity and a through-hole communicated with the cavity in at least part of a bonding portion between the first and second substrates. According to the present invention, it is possible to prevent irregularities or cracks caused by the presence or absence of the cavity and more regularly thin the substrate. In addition, it is possible to manufacture a semiconductor device capable of contributing to the miniaturization of devices and electronic equipment having the devices, using a more convenient process.

    Abstract translation: 一种制造半导体器件的方法包括：将具有光学透明性的第一衬底和第二衬底接合的接合步骤，其中功能元件彼此设置在其上，使得功能元件面向第一衬底; 减薄所述第一和第二基板中的至少一个的薄化步骤; 以及通孔形成步骤，在第一和第二基板之间的接合部分的至少一部分中形成与空腔连通的空腔和通孔。 根据本发明，可以防止由于空腔的存在或不存在引起的不规则或裂纹，并且更规则地使基板变薄。 此外，可以使用更方便的工艺来制造能够有助于具有该器件的器件和电子设备的小型化的半导体器件。

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