公开(公告)号：US20150243535A1

公开(公告)日：2015-08-27

申请号：US14335110

申请日：2014-07-18

Applicant: STS SEMICONDUCTOR & TELECOMMUNICATIONS CO., LTD.

Inventor： Eun Soo LEE ,  Hee Cheol KIM ,  Sung Yong KIM ,  Seung Tae LEE ,  Ig Jun SHIN

IPC: H01L21/67 ,  C23C14/34 ,  H01J37/34 ,  C23C14/02 ,  H01L21/285 ,  H01L21/02

CPC classification number: H01L21/67167 ,  C23C14/566 ,  H01J37/32889 ,  H01L21/28568 ,  H01L21/67196 ,  H01L21/67207

Abstract: A cluster type semiconductor processing apparatus and a method for manufacturing a semiconductor device using the same are provided. The cluster type semiconductor processing apparatus includes a polyhedral transfer module to transfer a wafer, a first process module communicating with the transfer module, a degassing process of removing fumes from a surface of the wafer being performed in the first process module, a second process module communicating with the transfer module, a plasma cleaning process of cleaning the surface of the wafer being performed in the second process module, a standby module communicating with the transfer module, the wafer having undergone the degassing process and the plasma cleaning process being maintained in the standby module for a certain time, and a third process module communicating with the transfer module, a metal sputtering process of depositing a metal film on the wafer being performed in the third process module.

Abstract translation: 提供了一种簇型半导体处理装置和使用其的半导体器件的制造方法。 集束型半导体处理装置包括用于传送晶片的多面体转移模块，与转移模块连通的第一处理模块，在第一处理模块中执行的从晶片表面去除烟雾的脱气过程，第二处理模块 与所述传送模块通信，清洁在所述第二处理模块中执行的所述晶片表面的等离子体清洁处理，与所述传送模块通信的备用模块，经过所述脱气处理的所述晶片和所述等离子体清洁处理被保持在 待机模块，以及与所述传送模块通信的第三处理模块，在所述第三处理模块中执行在所述晶片上沉积金属膜的金属溅射工艺。

公开(公告)号：US09029242B2

公开(公告)日：2015-05-12

申请号：US13161424

申请日：2011-06-15

Applicant: James M. Holden ,  Nir Merry ,  Todd Egan

Inventor： James M. Holden ,  Nir Merry ,  Todd Egan

IPC: H01L21/00 ,  H01L21/3065 ,  B23K26/06 ,  B23K26/36 ,  B23K26/40 ,  H01L21/78

CPC classification number: B23K26/0635 ,  B23K26/0624 ,  B23K26/364 ,  B23K26/40 ,  B23K2103/172 ,  B23K2103/42 ,  B23K2103/50 ,  H01J37/32889 ,  H01J2237/332 ,  H01J2237/334 ,  H01L21/30655 ,  H01L21/67069 ,  H01L21/67196 ,  H01L21/67207 ,  H01L21/78

Abstract: Methods and apparatuses for dicing substrates by both laser scribing and plasma etching. A method includes laser ablating material layers, the ablating by a laser beam with a centrally peaked spatial power profile to form an ablated trench in the substrate below thin film device layers which is positively sloped. In an embodiment, a femtosecond laser forms a positively sloped ablation profile which facilitates vertically-oriented propagation of microcracks in the substrate at the ablated trench bottom. With minimal lateral runout of microcracks, a subsequent anisotropic plasma etch removes the microcracks for a cleanly singulated chip with good reliability.

Abstract translation: 通过激光划线和等离子体蚀刻对基板进行切割的方法和装置。 一种方法包括激光烧蚀材料层，用具有中心峰值空间功率分布的激光束进行烧蚀，以在正向倾斜的薄膜器件层下面的衬底中形成消融沟槽。 在一个实施例中，飞秒激光形成正倾斜的消融轮廓，其有助于在烧蚀的沟槽底部处的衬底中的微裂纹的垂直定向传播。 随着微裂纹的侧向跳动最小，随后的各向异性等离子体蚀刻可以清除具有良好可靠性的干净分割芯片的微裂纹。

公开(公告)号：US09028191B2

公开(公告)日：2015-05-12

申请号：US13163165

申请日：2011-06-17

Applicant: Takeshi Yasui ,  Yukitomo Hirochi ,  Satoshi Takano ,  Ritsuo Horii ,  Makoto Kawabata

Inventor： Takeshi Yasui ,  Yukitomo Hirochi ,  Satoshi Takano ,  Ritsuo Horii ,  Makoto Kawabata

IPC: H01L21/67 ,  H01J37/32

CPC classification number: H01L21/67196 ,  H01J37/32743 ,  H01J37/32788 ,  H01J37/32889 ,  H01J37/32899 ,  H01L21/67201

Abstract: Reduction in cooling rate of a substrate having a lower temperature is suppressed because the substrate having a lower temperature is not affected by radiant heat of a substrate having a higher temperature while cooling a plurality of substrates in a cooling chamber. The substrate processing apparatus includes a load lock chamber configured to accommodate stacked substrates; a first transfer mechanism having a first transfer arm provided with a first end effector, and configured to transfer the substrates into/from the load lock chamber at a first side of the load lock chamber; a second transfer mechanism having a second transfer arm provided with a second end effector, and configured to transfer the substrates into/from the load lock chamber at a second side of the load lock chamber; a barrier installed between the substrates to be spaced apart from the substrates supported by a substrate support provided in the load lock chamber; and an auxiliary barrier unit installed between the substrate support and the barrier, wherein the auxiliary barrier unit is installed at places other than standby spaces of the end effectors.

Abstract translation: 由于具有较低温度的基板在冷却室中冷却多个基板的同时不受具有较高温度的基板的辐射热的影响，因此抑制了具有较低温度的基板的冷却速率的降低。 基板处理装置包括：负载锁定室，被配置为容纳堆叠的基板; 第一传送机构，其具有设置有第一端部执行器的第一传送臂，并且被配置为在所述负载锁定室的第一侧将所述基板传送到所述负载锁定室中或从所述负载锁定室传送; 第二传送机构，具有设置有第二端部执行器的第二传送臂，并且被配置为在所述负载锁定室的第二侧将所述基板传送到所述负载锁定室中或从所述负载锁定室传送; 安装在基板之间的屏障，其与由设置在负载锁定室中的基板支撑件支撑的基板间隔开; 以及安装在所述基板支撑件和所述屏障之间的辅助屏障单元，其中所述辅助屏障单元安装在所述末端执行器的备用空间以外的位置。

公开(公告)号：US20150044390A1

公开(公告)日：2015-02-12

申请号：US14525902

申请日：2014-10-28

Applicant: Tokyo Electron Limited

Inventor： Jozef Brcka ,  Osayuki Akiyama

IPC: C23C16/44 ,  C23C16/52 ,  H01J37/32 ,  C23C16/503

CPC classification number: C23C16/4405 ,  B08B7/0035 ,  C23C16/46 ,  C23C16/503 ,  C23C16/52 ,  H01J37/32091 ,  H01J37/32165 ,  H01J37/32449 ,  H01J37/32862 ,  H01J37/32889

Abstract: A method of operating a filament assisted chemical vapor deposition (FACVD) system. The method includes depositing a film on a substrate in a reactor of the FACVD system. During the depositing, a DC power is supplied to a heater assembly to thermally decompose a film forming material. The method also includes cleaning the heater assembly, or an interior surface of the reactor, or both. During the cleaning, an alternating current is supplied to the heater assembly to energize a cleaning media into a plasma.

Abstract translation: 一种操作细丝辅助化学气相沉积（FACVD）系统的方法。 该方法包括在FACVD系统的反应器中的衬底上沉积膜。 在沉积期间，向加热器组件供应直流电力以热分解成膜材料。 该方法还包括清洁加热器组件或反应器的内表面，或两者。 在清洁期间，向加热器组件供应交流电，以将清洁介质激励到等离子体中。

公开(公告)号：US20140367041A1

公开(公告)日：2014-12-18

申请号：US14476060

申请日：2014-09-03

Applicant: Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC: H01L21/78 ,  B23K26/36 ,  H01L21/67 ,  H01L23/544 ,  H01J37/32

CPC classification number: H01L21/822 ,  B23K26/36 ,  H01J37/32889 ,  H01J37/32899 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/67069 ,  H01L21/67092 ,  H01L21/67207 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

公开(公告)号：US20140329095A1

公开(公告)日：2014-11-06

申请号：US14348417

申请日：2012-09-28

Applicant: Domenic V. Planta ,  Leybold Optics GmbH

Inventor： Harro Hagedorn ,  Jurgen Pistner ,  Michael Klosch-Trageser ,  Michael Scherer

IPC: H01J37/32 ,  C23C14/02 ,  C23C14/34 ,  H01J37/34 ,  C23C14/58

CPC classification number: H01J37/32082 ,  C23C14/0036 ,  C23C14/021 ,  C23C14/022 ,  C23C14/024 ,  C23C14/34 ,  C23C14/505 ,  C23C14/52 ,  C23C14/568 ,  C23C14/5826 ,  H01J37/32733 ,  H01J37/32779 ,  H01J37/32889 ,  H01J37/34 ,  H01J37/3408 ,  Y10T428/31504

Abstract: The invention relates to an apparatus (1) for producing a reflection-reducing layer on a surface (21) of a plastics substrate (20). The apparatus comprises a first sputtering device (3) for applying a base layer (22) to the surface (21) of the plastics substrate (20), a plasma source (4) for plasma-etching the coated substrate surface (21), and a second sputtering device (5) for applying a protective layer (24) to the substrate surface (21). These processing devices (3, 4, 5) are arranged jointly in a vacuum chamber (2), which has inlets (8) for processing gases. In order to move the substrate (20) between the processing devices (3, 4, 5) in the interior of the vacuum chamber (2), a conveying apparatus (10) is provided which is preferably in the form of a rotary table (11).—Furthermore, the invention relates to a method for producing such a reflection-reducing layer on the surface (21) of the plastics substrate (20).

Abstract translation: 本发明涉及一种用于在塑料基板（20）的表面（21）上制造反射层的装置（1）。 该设备包括用于将基底层（22）施加到塑料基底（20）的表面（21）的第一溅射装置（3），用于等离子体蚀刻涂覆的基底表面（21）的等离子体源（4） 以及用于将保护层（24）施加到所述基板表面（21）的第二溅射装置（5）。 这些处理装置（3,4,5）共同设置在具有用于处理气体的入口（8）的真空室（2）中。 为了将基板（20）移动到真空室（2）的内部的处理装置（3,4,5）之间，提供了输送装置（10），其优选地为旋转台 此外，本发明涉及在塑料基板（20）的表面（21）上制造这种反射减少层的方法。

公开(公告)号：US08853056B2

公开(公告)日：2014-10-07

申请号：US14146887

申请日：2014-01-03

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC: H01L21/00 ,  H01L21/78 ,  H01L21/67 ,  H01L21/822 ,  H01L21/308

CPC classification number: H01L21/822 ,  B23K26/36 ,  H01J37/32889 ,  H01J37/32899 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/67069 ,  H01L21/67092 ,  H01L21/67207 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

Abstract translation: 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 一种方法包括在半导体晶片上形成掩模，该掩模包括覆盖并保护集成电路的层。 通过激光划线工艺对掩模和半导体晶片的一部分进行构图，以提供图案化掩模，并在集成电路之间部分地形成沟槽而不通过半导体晶片。 每个沟槽都有一个宽度。 通过沟槽等离子体蚀刻半导体晶片以形成对应的沟槽延伸部分并对集成电路进行分割。 每个相应的沟槽延伸部具有宽度。

公开(公告)号：US20140120697A1

公开(公告)日：2014-05-01

申请号：US14146887

申请日：2014-01-03

Applicant: APPLIED MATERIALS, INC.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

IPC: H01L21/822

CPC classification number: H01L21/822 ,  B23K26/36 ,  H01J37/32889 ,  H01J37/32899 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/67069 ,  H01L21/67092 ,  H01L21/67207 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

Abstract translation: 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 一种方法包括在半导体晶片上形成掩模，该掩模包括覆盖并保护集成电路的层。 通过激光划线工艺对掩模和半导体晶片的一部分进行构图，以提供图案化掩模，并在集成电路之间部分地形成沟槽而不通过半导体晶片。 每个沟槽都有一个宽度。 通过沟槽等离子体蚀刻半导体晶片以形成对应的沟槽延伸部分并对集成电路进行分割。 每个相应的沟槽延伸部具有宽度。

公开(公告)号：US20130160795A1

公开(公告)日：2013-06-27

申请号：US13337418

申请日：2011-12-27

Applicant: Ying Xiao ,  Chin-Hsiang Lin

Inventor： Ying Xiao ,  Chin-Hsiang Lin

IPC: H01L21/3065 ,  B08B6/00

CPC classification number: H01J37/321 ,  G03F7/427 ,  H01J37/32596 ,  H01J37/32706 ,  H01J37/32807 ,  H01J37/32889 ,  H01J37/32899 ,  H01L21/31138

Abstract: In some embodiments, the present disclosure relates to a plasma etching system having direct and localized plasma sources in communication with a processing chamber. The direct plasma is operated to provide a direct plasma to the processing chamber for etching a semiconductor workpiece. The direct plasma has a high potential, formed by applying a large bias voltage to the workpiece. After etching is completed the bias voltage and direct plasma source are turned off. The localized plasma source is then operated to provide a low potential, localized plasma to a position within the processing chamber that is spatially separated from the workpiece. The spatial separation results in formation of a diffused plasma having a zero/low potential that is in contact with the workpiece. The zero/low potential of the diffused plasma allows for reactive ashing to be performed, while mitigating workpiece damage resulting from ion bombardment caused by positive plasma potentials.

Abstract translation: 在一些实施例中，本公开涉及具有与处理室连通的直接和局部等离子体源的等离子体蚀刻系统。 操作直接等离子体以向处理室提供直接等离子体以蚀刻半导体工件。 直接等离子体具有高电位，通过向工件施加大的偏置电压而形成。 蚀刻完成后，偏置电压和直接等离子体源关闭。 然后操作局部等离子体源以将低电位局部等离子体提供到处理室内与工件空间分离的位置。 空间分离导致形成具有与工件接触的零/低电位的扩散等离子体。 扩散等离子体的零/低电位允许执行反应性灰化，同时减轻由正等离子体电位引起的离子轰击造成的工件损伤。

公开(公告)号：US20130104938A1

公开(公告)日：2013-05-02

申请号：US13483597

申请日：2012-05-30

Applicant: Armen Avoyan ,  Cliff La Croix ,  Hong Shih ,  John Daugherty

Inventor： Armen Avoyan ,  Cliff La Croix ,  Hong Shih ,  John Daugherty

IPC: B08B9/00

CPC classification number: H01J37/3288 ,  B08B3/04 ,  B08B3/08 ,  B08B9/0323 ,  B08B9/0328 ,  C23C16/4407 ,  H01J37/3244 ,  H01J37/32889

Abstract: In one embodiment, a method for cleaning a showerhead electrode my include sealing a showerhead electrode within a cleaning assembly such that a first cleaning volume is formed on a first side of the showerhead electrode and a second cleaning volume is formed on a second side of the showerhead electrode. An acidic solution can be loaded into the first cleaning volume on the first side of the showerhead electrode. The first cleaning volume on the first side of the showerhead electrode can be pressurized such that at least a portion of the acidic solution flows through one or more of the plurality of gas passages of the showerhead electrode. An amount of purified water can be propelled through the second cleaning volume on the second side of the showerhead electrode, and into contact with the second side of the showerhead electrode.

Abstract translation: 在一个实施例中，一种用于清洁喷头电极的方法包括将喷头电极密封在清洁组件内，使得在喷头电极的第一侧上形成第一清洁体积，并且在第二侧面上形成第二清洁体积 喷头电极 酸性溶液可以装载到喷头电极的第一侧上的第一清洁体积中。 可以对喷头电极的第一侧上的第一清洁体积进行加压，使得至少一部分酸性溶液流过喷头电极的多个气体通道中的一个或多个。 净化水的量可以通过喷头电极第二侧上的第二清洁体积推进，并与喷头电极的第二侧接触。