公开(公告)号：US08193456B2

公开(公告)日：2012-06-05

申请号：US12493732

申请日：2009-06-29

Applicant: Hiroyuki Takahashi ,  Chie Honda ,  Tatsuya Kato ,  Tomohide Yamada ,  Shigeru Taga

Inventor： Hiroyuki Takahashi ,  Chie Honda ,  Tatsuya Kato ,  Tomohide Yamada ,  Shigeru Taga

IPC: H05K1/00 ,  H05K3/02

CPC classification number: H05K3/4611 ,  G01R1/0491 ,  G01R3/00 ,  G01R31/2863 ,  H05K1/0306 ,  H05K1/113 ,  H05K3/388 ,  H05K3/4629 ,  H05K2201/0347 ,  H05K2203/025 ,  H05K2203/308 ,  Y10T29/49155

Abstract: An electrical testing substrate unit includes a multi-layer ceramic substrate formed of mullite and a borosilicate glass as predominant ceramic components. In the multi-layer ceramic substrate, the borosilicate glass contains an alkali metal oxide in an amount of 0.5 to 1.5 mass %. The multi-layer ceramic substrate has a mean coefficient of linear thermal expansion having a value of 3.0 to 4.0 ppm/° C. between −50° C. and 150° C. A thermal expansion coefficient, α1, of the multi-layer ceramic substrate as determined at a particular temperature and a thermal expansion coefficient, α2, of a to-be-tested silicon wafer as determined at the same temperature silicon satisfy a relation: 0 ppm/° C.

Abstract translation: 电测试衬底单元包括由莫来石和硼硅酸盐玻璃作为主要陶瓷组分形成的多层陶瓷衬底。 在多层陶瓷基板中，硼硅酸玻璃含有0.5〜1.5质量％的碱金属氧化物。 多层陶瓷基板在-50℃〜150℃之间具有3.0〜4.0ppm /℃的平均线性热膨胀系数。多层陶瓷的热膨胀系数α1 在相同温度下测定的待测硅晶片的特定温度下的基板和热膨胀系数α2满足关系：0ppm /℃。<α1-α2＆nlE; 2.5ppm /° C.在-50℃至150℃的温度范围内。电极形成在多层陶瓷衬底的表面上。

公开(公告)号：US20120125676A1

公开(公告)日：2012-05-24

申请号：US13362970

申请日：2012-01-31

Applicant: Daisuke Sakurai ,  Yoshihiko Yagi

Inventor： Daisuke Sakurai ,  Yoshihiko Yagi

IPC: H05K1/16 ,  H05K1/11

CPC classification number: H05K1/03 ,  H01L2224/16227 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K3/0082 ,  H05K3/207 ,  H05K3/4069 ,  H05K3/4647 ,  H05K3/4664 ,  H05K2201/0347 ,  H05K2203/0514 ,  H05K2203/056 ,  H05K2203/107 ,  Y10T29/49124

Abstract: A three-dimensional circuit board is formed by comprising a board, a first wiring-electrode group provided on a plurality of steps above the board, and a second wiring-electrode connected to the first wiring-electrode group at least in an altitude direction, in which at least a connecting portion between the first wiring-electrode group and the second wiring-electrode is integrated in a continuously identical shape.

Abstract translation: 三维电路板通过包括板，设置在板上方的多个台阶上的第一布线电极组和至少在高度方向连接到第一布线电极组的第二布线电极形成， 其中第一布线电极组和第二布线电极之间的至少一个连接部分被整合为连续相同的形状。

公开(公告)号：US08171626B1

公开(公告)日：2012-05-08

申请号：US13155375

申请日：2011-06-07

Applicant: Cheng-Po Yu ,  Chi-Min Chang

Inventor： Cheng-Po Yu ,  Chi-Min Chang

IPC: H05K3/02 ,  H05K3/10 ,  H05K3/00 ,  H01R9/00 ,  H01R43/00

CPC classification number: H05K3/465 ,  H05K3/107 ,  H05K2201/0347 ,  Y10T29/49117 ,  Y10T29/49147 ,  Y10T29/49155

Abstract: A method for forming an embedded circuit is disclosed. First, a substrate including a dielectric layer is provided. Second, the dielectric layer is entirely covered by a dummy layer. Then, the dummy layer is patterned and a trench is formed in the dielectric layer at the same time. Later, a seed layer is formed to entirely cover the dummy layer and the trench. Next, the dummy layer is removed and the seed layer covering the dummy layer is removed, too. Afterwards, a metal layer is filled in the trench to form an embedded circuit embedded in the dielectric layer.

Abstract translation: 公开了一种用于形成嵌入式电路的方法。 首先，提供包括电介质层的基板。 第二，介电层完全被虚拟层覆盖。 然后，对虚拟层进行图案化，同时在电介质层中形成沟槽。 之后，形成种子层以完全覆盖虚设层和沟槽。 接下来，去除虚拟层，并且去除覆盖虚拟层的种子层。 之后，在沟槽中填充金属层，形成嵌入电介质层的嵌入电路。

公开(公告)号：US08161635B1

公开(公告)日：2012-04-24

申请号：US12026429

申请日：2008-02-05

Applicant: Chien Te Chen

Inventor： Chien Te Chen

IPC: H01K3/10

CPC classification number: H05K1/113 ,  H05K3/427 ,  H05K2201/0347 ,  H05K2201/0959 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Novel methods are provided that results in the formation of single-cap VIPs in a substrate are described herein. As a result, fine pitch trace patterns may be formed on the substrate. The methods may include initially providing a substrate having a first and a second side, the first side being opposite of the second side. A via may then be constructed in the substrate, the via being formed within a via hole that extends from the first side to the second side of the substrate, the formed via having a first end located at the first side of the substrate, and a second end opposite the first end located at the second side of the substrate. A selective deposition may be performed of a conductive material on the second end of the via to form a conductive pad directly on the via on the second side of the substrate without depositing the conductive material onto the first side of the substrate.

Abstract translation: 本文描述了导致在底物中形成单帽VIP的新方法。 结果，可以在基板上形成精细的间距迹线图案。 所述方法可以包括最初提供具有第一和第二侧的衬底，第一侧与第二侧相对。 然后可以在衬底中构造通孔，所述通孔形成在从衬底的第一侧延伸到第二侧的通孔中，所形成的通孔具有位于衬底的第一侧的第一端，以及 第二端相对于位于基板的第二侧的第一端。 可以在通孔的第二端上执行导电材料的选择性沉积，以在衬底的第二侧上的通孔上直接形成导电焊盘，而不将导电材料沉积到衬底的第一侧上。

公开(公告)号：US08156645B2

公开(公告)日：2012-04-17

申请号：US12157021

申请日：2008-06-05

Applicant: Rajwant Singh Sidhu

Inventor： Rajwant Singh Sidhu

IPC: H01K3/10

CPC classification number: H05K3/427 ,  H05K1/116 ,  H05K3/243 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/0959 ,  H05K2203/025 ,  H05K2203/0554 ,  H05K2203/1476 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Printed circuit boards have circuit layers with one or more via filled holes with copper wraps and methods of manufacturing the same. An embodiment of the present invention provides a method to enhance the consistency of the wraparound plating of through-hole vias of printed circuit boards with (requiring) via filling to provide extra reliability to the printed circuit boards and enables the designers and/or manufacturers of printed circuit boards to design and manufacture boards with relatively fine features and/or tight geometries.

Abstract translation: 印刷电路板具有带铜箔的一个或多个通孔填充孔的电路层及其制造方法。 本发明的一个实施例提供了一种通过（需要）通过填充来增强印刷电路板的通孔通孔的环绕电镀的一致性的方法，以向印刷电路板提供额外的可靠性，并且使设计者和/或制造商 印刷电路板设计和制造具有相对精细特征和/或紧密几何形状的电路板。

公开(公告)号：US20120067633A1

公开(公告)日：2012-03-22

申请号：US13307213

申请日：2011-11-30

Applicant: Yogo KAWASAKI ,  Hiroaki Satake ,  Yutaka Iwata ,  Tetsuya Tanabe

Inventor： Yogo KAWASAKI ,  Hiroaki Satake ,  Yutaka Iwata ,  Tetsuya Tanabe

IPC: H05K1/02

CPC classification number: H05K1/113 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/3457 ,  H05K3/381 ,  H05K3/382 ,  H05K3/426 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/0209 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0796 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A multi-layer printed circuit board including a core substrate, lower interlayer resin insulating layers formed on the surfaces of the core substrate, respectively, through-hole conductors formed in penetrating holes penetrating through the core substrate and the lower interlayer resin insulating layers, conductor circuits formed on the lower interlayer resin insulating layers, respectively, upper interlayer resin insulating layers formed on the conductor circuits and the lower interlayer resin insulating layers, respectively and via hole conductors formed in the upper interlayer resin insulating layers and positioned on the through-hole conductors, respectively.

Abstract translation: 一种多层印刷电路板，包括芯基板，分别形成在芯基板的表面上的下层层间树脂绝缘层，形成在穿透芯基板的穿透孔中的通孔导体和下层间树脂绝缘层，导体 形成在下层树脂绝缘层上的电路分别形成在导体电路和下层间树脂绝缘层上的上层间树脂绝缘层和分别形成在上层间树脂绝缘层中并位于通孔上的通孔导体 导体。

公开(公告)号：US08115113B2

公开(公告)日：2012-02-14

申请号：US12216747

申请日：2008-07-10

Applicant: Hironori Tanaka

Inventor： Hironori Tanaka

IPC: H05K1/11 ,  H05K1/18

CPC classification number: H05K1/162 ,  H05K1/0269 ,  H05K1/112 ,  H05K3/205 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/0179 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/09918 ,  H05K2203/166

Abstract: A multilayer printed wiring board including a layered capacitor section provided on a first interlayer resin insulation layer and a high dielectric layer and first and second layered electrodes that sandwich the high dielectric layer. A second interlayer resin insulation layer is provided on the first insulation layer and the capacitor section, and a metal thin-film layer is provided over the capacitor section and on the second insulation layer. An outermost interlayer resin insulation layer is provided on the second insulation layer and the metal thin-film layer. A mounting section is provided on the outermost insulation layer and has first and second external terminals to mount a semiconductor element. Multiple via conductors penetrate each insulation layer. The via conductors include first via conductors that electrically connect the first layered electrode to the first external terminals. Second via conductors electrically connect the second layered electrode to the second external terminals.

Abstract translation: 一种多层印刷线路板，包括设置在第一层间树脂绝缘层和高电介质层上的层状电容器部分和夹着高电介质层的第一和第二层状电极。 在第一绝缘层和电容器部分上设置第二层间树脂绝缘层，并且在电容器部分和第二绝缘层上设置金属薄膜层。 在第二绝缘层和金属薄膜层上设置最外层的层间树脂绝缘层。 安装部分设置在最外层绝缘层上，并且具有安装半导体元件的第一和第二外部端子。 多个通孔导体穿过每个绝缘层。 通孔导体包括将第一层状电极电连接到第一外部端子的第一通孔导体。 第二通孔导体将第二层状电极电连接到第二外部端子。

公开(公告)号：US08110748B2

公开(公告)日：2012-02-07

申请号：US12614246

申请日：2009-11-06

Applicant: Hiroki Nakamura

Inventor： Hiroki Nakamura

IPC: H05K1/09

CPC classification number: H01L21/76843 ,  H01L21/76852 ,  H01L21/76874 ,  H01L21/76885 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66757 ,  H01L2221/1078 ,  H05K3/108 ,  H05K3/388 ,  H05K2201/0347 ,  H05K2203/072 ,  Y10T29/49117

Abstract: The present invention provides a wiring, a display device, and a method of manufacturing the same. A first metal diffusion-preventing layer is formed on a substrate or on a circuit element formed on the substrate. Then, a metal wiring layer is selectively formed on the first metal diffusion-preventing layer by an electroless metal plating method or a metal electroplating method. Further, the undesired portion of the first metal diffusion-preventing layer is removed. Finally, a second metal diffusion-preventing layer is formed selectively by an electroless metal plating method in a manner to cover the metal wiring layer or both a seed layer and the metal wiring layer.

Abstract translation: 本发明提供一种布线，显示装置及其制造方法。 在基板或形成在基板上的电路元件上形成第一金属防扩散层。 然后，通过无电金属电镀法或金属电镀法，在第一金属防止扩散层上选择性地形成金属布线层。 此外，去除了第一金属防扩散层的不希望的部分。 最后，以覆盖金属布线层或晶种层和金属布线层的方式，通过化学镀金属法选择性地形成第二金属防扩散层。

公开(公告)号：US08080741B2

公开(公告)日：2011-12-20

申请号：US12149522

申请日：2008-05-02

Applicant: Myung Sam Kang ,  Chin Kwan Kim

Inventor： Myung Sam Kang ,  Chin Kwan Kim

IPC: H05K1/11

CPC classification number: H05K3/4007 ,  H05K3/246 ,  H05K3/3457 ,  H05K3/4069 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09481 ,  H05K2201/09745

Abstract: A printed circuit board, which increases the contact area between an IC and a printed circuit board, thus increasing the degree of adhesion, is disclosed. The printed circuit board includes: an insulation layer which includes a first circuit pattern, including at least one via land, embedded in the upper surface of the insulation layer to be flush with the upper surface, and a second circuit pattern formed in the lower surface of the insulation layer to be flush with the lower surface; a solder resist layer formed on the insulation layer; a via hole and a bump integrally formed on the second circuit pattern through the via hole and the via land such that it protrudes from the insulation layer to be higher than the solder resist layer.

Abstract translation: 公开了一种印刷电路板，其增加了IC和印刷电路板之间的接触面积，从而增加了粘合度。 印刷电路板包括：绝缘层，其包括嵌入在绝缘层的上表面中以与上表面齐平的至少一个通孔焊盘的第一电路图案，以及形成在下表面中的第二电路图案 的绝缘层与下表面齐平; 形成在绝缘层上的阻焊层; 通孔和通过通孔和通孔焊盘一体地形成在第二电路图案上的突起，使得其从绝缘层突出成高于阻焊层。

公开(公告)号：US08003896B2

公开(公告)日：2011-08-23

申请号：US11832673

申请日：2007-08-02

Applicant: Youhong Wu

Inventor： Youhong Wu

IPC: H05K1/11

CPC classification number: H05K1/115 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/0352 ,  H05K2201/09454 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09627 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A multi-layer printed wiring board has a core substrate, a first interlayer insulation layer formed over the core substrate, a first filled via formed in the first interlayer insulation layer, a second interlayer insulation layer formed over the first interlayer insulation layer, and a second filled via formed in the second interlayer insulation layer. The first filled via has a bottom portion having a first diameter. The second filled via has a bottom portion having a second diameter smaller than the first diameter.

Abstract translation: 多层印刷线路板具有芯基板，形成在芯基板上的第一层间绝缘层，形成在第一层间绝缘层中的第一填充通孔，形成在第一层间绝缘层上的第二层间绝缘层，以及 第二填充通孔形成在第二层间绝缘层中。 第一填充通孔具有第一直径的底部。 第二填充通孔具有第二直径小于第一直径的底部。