公开(公告)号：US07287323B1

公开(公告)日：2007-10-30

申请号：US10837015

申请日：2004-04-30

Applicant: Michael Richard Ehlert ,  William Jeffrey Schaefer

Inventor： Michael Richard Ehlert ,  William Jeffrey Schaefer

IPC: H01R12/36 ,  H05K1/11 ,  H05K3/40

CPC classification number: H01L23/49827 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/10126 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K1/113 ,  H05K3/248 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/4061 ,  H05K2201/017 ,  H05K2201/035 ,  H05K2201/09909 ,  Y10T29/49149 ,  Y10T29/49165 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A ceramic circuit structure comprising a plurality of ceramic layers and at least one electronic component embedded within the plurality of ceramic layers. Within a first one of the ceramic layers is a via that passes through the ceramic layer. A contact pad is formed on a surface of the ceramic layer. A barrier cap is formed between the via and the contact pad. A dielectric ring covers a peripheral portion of the contact pad and an adjacent portion of the dielectric material layer surface immediately surrounding the contact pad, such that any solder that is applied to the contact does not contact the peripheral portion of the contact pad or the ceramic material.

Abstract translation: 一种陶瓷电路结构，包括多个陶瓷层和至少一个嵌入在所述多个陶瓷层内的电子部件。 在第一陶瓷层之中的是通过陶瓷层的通孔。 在陶瓷层的表面上形成接触垫。 在通孔和接触垫之间形成阻挡帽。 介电环覆盖接触焊盘的周边部分和电介质材料层表面的相邻部分，其紧邻围绕接触焊盘，使得施加到接触件的任何焊料不接触接触焊盘或陶瓷的周边部分 材料。

公开(公告)号：US07239027B2

公开(公告)日：2007-07-03

申请号：US11047646

申请日：2005-02-02

Applicant: Su-Tsai Lu

Inventor： Su-Tsai Lu

IPC: H01L23/48

CPC classification number: H05K3/328 ,  H01L21/563 ,  H01L23/4985 ,  H01L24/81 ,  H01L2224/16 ,  H01L2224/81012 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81232 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/83894 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/351 ,  H05K3/20 ,  H05K3/321 ,  H05K3/325 ,  H05K2201/035 ,  H05K2201/10659 ,  H05K2201/10674 ,  H05K2203/0285 ,  Y10T428/24917 ,  H01L2924/00

Abstract: A bonding structure of device packaging includes a first substrate and a second substrate. The surfaces of the first substrate have metal pads and a first bonding layer connected to the second substrate whose surfaces have a second bonding layer and electrodes. The first bonding layer is combined with the second bonding layer, and the metal pads are in electrical communications with the electrodes. The second substrate may be a flexible substrate to decrease the strain between the first substrate and the second substrate.

Abstract translation: 器件封装的结合结构包括第一衬底和第二衬底。 第一基板的表面具有金属焊盘和连接到第二基板的第一接合层，其表面具有第二接合层和电极。 第一接合层与第二接合层组合，并且金属焊盘与电极电连通。 第二衬底可以是柔性衬底，以减小第一衬底和第二衬底之间的应变。

公开(公告)号：US07213323B2

公开(公告)日：2007-05-08

申请号：US11058939

申请日：2005-02-16

Applicant: Jeffrey R. Baker ,  Carlos S. Sanchez ,  Patrick H. Bair

Inventor： Jeffrey R. Baker ,  Carlos S. Sanchez ,  Patrick H. Bair

IPC: G01R3/00

CPC classification number: H01H13/702 ,  G01L1/20 ,  G01L1/205 ,  H01H2201/036 ,  H01H2203/02 ,  H01H2239/01 ,  H05K1/0268 ,  H05K1/11 ,  H05K1/141 ,  H05K1/167 ,  H05K3/249 ,  H05K3/305 ,  H05K3/365 ,  H05K2201/035 ,  H05K2201/09663 ,  H05K2201/10151 ,  H05K2201/2036 ,  H05K2203/0278 ,  Y10T29/49002 ,  Y10T29/49007 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49146

Abstract: The cost and complexity of an electronic pressure sensitive transducer are decreased by constructing such a transducer directly on a printed circuit board containing support electronics. Conductive traces are formed on the printed circuit board to define a contact area. A flexible substrate having an inner surface is positioned over the contact area. An adhesive spacer, substantially surrounding the contact area, attaches the flexible substrate to the printed circuit board. At least one resistive layer is deposited on the flexible substrate inner surface. In use, the resistive layer contacts at least two conductive traces in response to pressure applied to the flexible substrate to produce an electrical signal indicative of applied pressure.

Abstract translation: 电子压敏传感器的成本和复杂性通过直接在包含支撑电子器件的印刷电路板上构建这样的传感器来减少。 导电迹线形成在印刷电路板上以限定接触区域。 具有内表面的柔性基板位于接触区域上方。 基本上围绕接触区域的粘合剂间隔件将柔性基板附接到印刷电路板。 至少一个电阻层沉积在柔性衬底内表面上。 在使用中，电阻层响应于施加到柔性衬底的压力而接触至少两个导电迹线，以产生指示所施加的压力的电信号。

公开(公告)号：US07122746B2

公开(公告)日：2006-10-17

申请号：US10832433

申请日：2004-04-27

Applicant: Reiji Higuchi ,  Shouji Itou ,  Osamu Nakao

Inventor： Reiji Higuchi ,  Shouji Itou ,  Osamu Nakao

IPC: H01R12/04 ,  H05K1/11 ,  H05K3/36 ,  H05K3/02

CPC classification number: H05K3/4632 ,  H05K1/0393 ,  H05K3/244 ,  H05K3/246 ,  H05K3/247 ,  H05K3/4069 ,  H05K3/4617 ,  H05K3/4652 ,  H05K2201/0129 ,  H05K2201/0347 ,  H05K2201/035 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/09481 ,  H05K2201/096 ,  H05K2203/0156 ,  H05K2203/0191 ,  H05K2203/0554 ,  H05K2203/072 ,  H05K2203/1453 ,  H05K2203/1461 ,  Y10T29/49126 ,  Y10T29/49155

Abstract: A multilayer wiring board assembly, a multilayer wiring board assembly component and a method of manufacture thereof are described in which it is possible to easily laminate together flexible FPCs having highly packing densities by via-on-via and chip-on-via. The multilayer wiring board assembly is laminated by laminating together a plurality of multilayer wiring board assembly components, each of which is made by preparing a copper plated resin film 10 made of a copper plated resin film made of a resin film having adhesivity which is provided with a copper foil bonded to one surface thereof and in which a through hole is opened through said copper foil and said resin film, and a conductive paste filler embedded by screen printing in the through hole of said copper plated resin film from said copper foil with a leading end of said conductive paste filler being projected from said resin film.

公开(公告)号：US20060216484A1

公开(公告)日：2006-09-28

申请号：US11388705

申请日：2006-03-24

Applicant: Atsushi Saita ,  Toshikazu Imaoka ,  Tetsuro Sawai

Inventor： Atsushi Saita ,  Toshikazu Imaoka ,  Tetsuro Sawai

IPC: B32B3/00 ,  B32B18/00

CPC classification number: H05K1/024 ,  B32B15/08 ,  H05K1/0242 ,  H05K1/0298 ,  H05K3/4688 ,  H05K2201/0191 ,  H05K2201/035 ,  H05K2201/0715 ,  H05K2201/098 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: A wiring board in which a line can be made narrower and/or a transmission loss can be reduced is developed. The wiring board includes a first conductor and a second conductor maintained at the same potential, a dielectric material layer provided between the first and second conductors, and a third conductor embedded in the dielectric material layer. In the wiring board, a thickness of the dielectric material layer in a first region located between the third conductor and the first conductor is larger than a thickness of the dielectric material layer in a second region located between the third conductor and the second conductor. Moreover, a cross-sectional shape of the third conductor is trapezoidal in which angles of respective ends of the third conductor on a side closer to the second conductor are obtuse.

Abstract translation: 开发了可以使线路变窄和/或可以减小传输损耗的布线板。 布线板包括保持在相同电位的第一导体和第二导体，设置在第一和第二导体之间的介电材料层和嵌入电介质材料层中的第三导体。 在布线板中，位于第三导体和第一导体之间的第一区域中的电介质材料层的厚度大于位于第三导体和第二导体之间的第二区域中的电介质材料层的厚度。 此外，第三导体的横截面形状是梯形的，其中第三导体在更靠近第二导体的一侧的各端的角度是钝的。

公开(公告)号：US20060120015A1

公开(公告)日：2006-06-08

申请号：US11002748

申请日：2004-12-02

Applicant: William Borland

Inventor： William Borland

IPC: H01G4/228

CPC classification number: H05K1/162 ,  H01L27/013 ,  H05K1/092 ,  H05K3/1291 ,  H05K3/4611 ,  H05K3/4623 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/035 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2203/1126 ,  Y10T29/435 ,  Y10T29/49128 ,  Y10T29/49156

Abstract: A method of embedding thick-film capacitors includes etching foil electrodes outside the boundary of the capacitor dielectric to prevent etching solutions from coming in contact with and damaging the capacitor dielectric layers.

Abstract translation: 嵌入厚膜电容器的方法包括在电容器电介质的边界之外蚀刻箔电极，以防止蚀刻溶液与电容器电介质层接触并损坏电容器电介质层。

公开(公告)号：US06969264B2

公开(公告)日：2005-11-29

申请号：US10850262

申请日：2004-05-20

Applicant: Shoji Fujii ,  Toshiharu Fukui ,  Tetsuo Murakami

Inventor： Shoji Fujii ,  Toshiharu Fukui ,  Tetsuo Murakami

IPC: G06F3/045 ,  G06F3/033 ,  G06F3/041 ,  H01H13/712 ,  H05K3/24 ,  H05K3/32 ,  H05K3/36 ,  H01R12/00 ,  H05K1/00

CPC classification number: G06F3/041 ,  H05K3/245 ,  H05K3/323 ,  H05K3/361 ,  H05K2201/023 ,  H05K2201/035

Abstract: A transparent touch panel is structured by forming connecting layers that contain conductive metal powder dispersed in a resin, on ends of wiring patterns on a wiring board to which upper electrodes and lower electrodes are to be bonded. This structure can provide a transparent touch panel that ensures bonding of upper and lower substrates and the wiring board and stable electrical connection.

Abstract translation: 通过在上部电极和下部电极要被接合的布线基板上的布线图案的端部上形成包含分散在树脂中的导电金属粉末的连接层来构成透明触摸面板。 该结构可以提供透明的触摸面板，确保上下基板和布线板的接合以及稳定的电连接。

公开(公告)号：US20050148165A1

公开(公告)日：2005-07-07

申请号：US11048767

申请日：2005-02-03

Applicant: Akira Mase

Inventor： Akira Mase

IPC: H01L21/60 ,  G02F1/13 ,  G02F1/1343 ,  G02F1/1345 ,  H01L21/48 ,  H05K1/09 ,  H05K3/24 ,  H01L21/44

CPC classification number: G02F1/13452 ,  G02F1/13439 ,  G02F1/1345 ,  H01L21/4867 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/81192 ,  H01L2224/83851 ,  H01L2924/00011 ,  H05K1/095 ,  H05K3/245 ,  H05K2201/0326 ,  H05K2201/035 ,  Y10T29/4913 ,  Y10T29/49137 ,  Y10T29/49155 ,  H01L2224/29075 ,  H01L2924/00014

Abstract: An improved method of forming an electrode pattern on a substrate is described. The substarate is coated with a first conductive film and subjected to baking. On the first conductive film is then overlied a second conductive film which mends possible fissures of the first conductive film which, besides, would produce open circuits in the pattern.

Abstract translation: 描述了在衬底上形成电极图案的改进方法。 该底物涂覆有第一导电膜并进行烘烤。 然后在第一导电膜上覆盖第二导电膜，该第二导电膜补偿第一导电膜的可能的裂缝，此外，该图案将产生图案中的开路。

公开(公告)号：US06899025B2

公开(公告)日：2005-05-31

申请号：US10784692

申请日：2004-02-23

Applicant: John M. Michiels ,  Darryl M. Stansbury

Inventor： John M. Michiels ,  Darryl M. Stansbury

IPC: B41M1/12 ,  B41M1/34 ,  B41M3/00 ,  H01C1/00 ,  H01J9/02 ,  H05K1/09 ,  H05K1/18 ,  H05K3/12 ,  H05K3/24 ,  H05K3/46

CPC classification number: B41M1/12 ,  B41M1/34 ,  B41M3/006 ,  H01J29/92 ,  H01L51/0004 ,  H05K1/092 ,  H05K1/181 ,  H05K3/1233 ,  H05K3/248 ,  H05K3/4664 ,  H05K2201/035 ,  H05K2201/09045 ,  H05K2201/09981 ,  H05K2203/0264

Abstract: Method for screen printing a continuous structure on a substrate wherein the screen printed structure extends from at least a first level to at least a second level. The disclosed method is particularly suitable for the fabrication of microelectronic devices and components thereof including the fabrication of field emission display devices. Preferably, a print screen of a preferred thickness having a preconfigured print pattern formed therethrough, in combination with a squeegee having a hardness within a preferred range, are used to force a screen printable substance onto a substrate while maintaining a portion of the print screen within a preferred reference angle. The resulting screen printed structure extends from at least one lower level to at least one upper level in a continuous “uphill” manner.

公开(公告)号：US06880244B2

公开(公告)日：2005-04-19

申请号：US09754133

申请日：2001-01-05

Applicant: Yuji Yagi ,  Takeo Yasuho

Inventor： Yuji Yagi ,  Takeo Yasuho

IPC: H05K1/18 ,  H01L21/48 ,  H01L21/60 ,  H01L23/12 ,  H01L23/498 ,  H05K1/09 ,  H05K3/20 ,  H05K3/22 ,  H05K3/32 ,  H05K3/34 ,  H05K3/40 ,  H05K3/46 ,  H01K3/22

CPC classification number: H05K3/4647 ,  H01L21/4867 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/092 ,  H05K1/095 ,  H05K3/207 ,  H05K3/22 ,  H05K3/323 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/4061 ,  H05K3/4069 ,  H05K3/4664 ,  H05K2201/035 ,  H05K2201/0367 ,  H05K2203/0113 ,  H05K2203/025 ,  H05K2203/0307 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49163 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Method of manufacturing a circuit board and semiconductor device wherein the circuit board has a plurality of wiring patterns and protrusions located on the wiring patterns, the method including simultaneously and unitarily forming the wiring patterns and protrusions, and alternatively coupling electrically the protrusions with electrodes on a semiconductor chip component when present.

Abstract translation: 制造电路板和半导体器件的方法，其中电路板具有位于布线图案上的多个布线图案和突起，该方法包括同时并且整体地形成布线图案和突起，以及将突起与电极电连接 半导体芯片组件存在时。