-
31.发明授权公开(公告)号：US09252593B2
公开(公告)日：2016-02-02
申请号：US13716272
申请日：2012-12-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Hao Chen
CPC classification number: H05F3/02 , G01R1/07378 , G01R1/36 , H01L2924/15174 , H01L2924/15311 , H02H9/046 , H05K1/11 , H05K1/181 , H05K2201/07 , H05K2201/10734
Abstract: The present disclosure provides a system and method for providing electrostatic discharge protection. A probe card assembly is provided which is electrically connected to a plurality of input/output channels. The probe card assembly can be contacted with a secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test. Voltage can be forced on ones of the plural input/output channels of the probe card assembly to slowly dissipate charges resident on the wafer to thereby provide electrostatic discharge protection. A socket assembly adaptable to accept a 3DIC package is also provided, the assembly having a loadboard assembly electrically connected to a plurality of input/output channels. Once the 3DIC package is placed within the socket assembly, voltage is forced on ones of the input/output channels to slowly dissipate charges resident on the 3DIC package to thereby provide electrostatic discharge protection.
Abstract translation: 本公开提供了一种用于提供静电放电保护的系统和方法。 提供一种电连接到多个输入/输出通道的探针卡组件。 探针卡组件可以与具有电连接到一个或多个晶片的插入器的次级组件接触，每个晶片具有被测器件。 可以将电压强制在探针卡组件的多个输入/输出通道中的一个上，以缓慢地耗散驻留在晶片上的电荷，从而提供静电放电保护。 还提供了适于接受3DIC封装的插座组件，该组件具有电连接到多个输入/输出通道的装载板组件。 一旦将3DIC封装放置在插座组件中，则强制在输入/输出通道之间施加电压以缓慢耗散驻留在3DIC封装上的电荷，从而提供静电放电保护。
-
32.发明申请公开(公告)号：US20140167799A1
公开(公告)日：2014-06-19
申请号：US13716272
申请日：2012-12-17
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Mill-Jer WANG , Ching-Nen PENG , Hung-Chih LIN , Hao CHEN
CPC classification number: H05F3/02 , G01R1/07378 , G01R1/36 , H01L2924/15174 , H01L2924/15311 , H02H9/046 , H05K1/11 , H05K1/181 , H05K2201/07 , H05K2201/10734
Abstract: The present disclosure provides a system and method for providing electrostatic discharge protection. A probe card assembly is provided which is electrically connected to a plurality of input/output channels. The probe card assembly can be contacted with a secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test. Voltage can be forced on ones of the plural input/output channels of the probe card assembly to slowly dissipate charges resident on the wafer to thereby provide electrostatic discharge protection. A socket assembly adaptable to accept a 3DIC package is also provided, the assembly having a loadboard assembly electrically connected to a plurality of input/output channels. Once the 3DIC package is placed within the socket assembly, voltage is forced on ones of the input/output channels to slowly dissipate charges resident on the 3DIC package to thereby provide electrostatic discharge protection.
Abstract translation: 本公开提供了一种用于提供静电放电保护的系统和方法。 提供一种电连接到多个输入/输出通道的探针卡组件。 探针卡组件可以与具有电连接到一个或多个晶片的插入器的次级组件接触，每个晶片具有被测器件。 可以将电压强制在探针卡组件的多个输入/输出通道中的一个上，以缓慢地耗散驻留在晶片上的电荷，从而提供静电放电保护。 还提供了适于接受3DIC封装的插座组件，该组件具有电连接到多个输入/输出通道的装载板组件。 一旦将3DIC封装放置在插座组件中，则强制在输入/输出通道之间施加电压以缓慢耗散驻留在3DIC封装上的电荷，从而提供静电放电保护。
-
公开(公告)号：US20240196518A1
公开(公告)日：2024-06-13
申请号：US18583199
申请日：2024-02-21
Applicant: Ampheno Corporation
Inventor： Mark W. Gailus , Marc B. Cartier, JR. , Vysakh Sivarajan , David Levine
CPC classification number: H05K1/0222 , H01R43/205 , H05K1/0216 , H05K1/0219 , H05K1/025 , H05K1/0251 , H05K1/0253 , H05K1/0298 , H05K1/115 , H05K3/0047 , H05K3/4038 , H05K3/429 , H05K2201/07 , H05K2201/09063 , H05K2201/09318 , H05K2201/09545 , H05K2201/096 , H05K2201/097 , H05K2201/09718 , H05K2201/09845 , H05K2201/09854 , H05K2201/10189
Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.
-
公开(公告)号：US11950356B2
公开(公告)日：2024-04-02
申请号：US18079956
申请日：2022-12-13
Applicant: Amphenol Corporation
Inventor： Mark W. Gailus , Marc B. Cartier, Jr. , Vysakh Sivarajan , David Levine
CPC classification number: H05K1/0222 , H01R43/205 , H05K1/0216 , H05K1/0219 , H05K1/025 , H05K1/0251 , H05K1/0253 , H05K1/0298 , H05K1/115 , H05K3/0047 , H05K3/4038 , H05K3/429 , H05K2201/07 , H05K2201/09063 , H05K2201/09318 , H05K2201/09545 , H05K2201/096 , H05K2201/097 , H05K2201/09718 , H05K2201/09845 , H05K2201/09854 , H05K2201/10189
Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.
-
公开(公告)号：US20180324941A1
公开(公告)日：2018-11-08
申请号：US16032284
申请日：2018-07-11
Applicant: Amphenol Corporation
Inventor： Mark W. Gailus , Marc B. Cartier, JR. , Vysakh Sivarajan , David Levine
CPC classification number: H05K1/0222 , H01R43/205 , H05K1/0216 , H05K1/0219 , H05K1/025 , H05K1/0251 , H05K1/0253 , H05K1/0298 , H05K1/115 , H05K3/0047 , H05K3/4038 , H05K3/429 , H05K2201/07 , H05K2201/09063 , H05K2201/09318 , H05K2201/09545 , H05K2201/096 , H05K2201/097 , H05K2201/09718 , H05K2201/09845 , H05K2201/09854 , H05K2201/10189
Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.
-
Patent Agency Ranking
公开(公告)号：US20180242467A1
公开(公告)日：2018-08-23
申请号：US15436061
申请日：2017-02-17
Applicant: International Business Machines Corporation
Inventor： Michael J. Shapiro , Brian C. Twichell , Brent W. Yardley
CPC classification number: H05K5/0217 , H05K1/11 , H05K1/181 , H05K7/20727 , H05K2201/07 , H05K2201/10371 , H05K2201/2018 , H05K2201/2027
Abstract: An apparatus for a dust guard structure includes a particle guard coupled to a top surface of a circuit board, wherein the particle guard is located along a first side of the circuit board between an edge of the circuit board and a first electronic component. The dust guard structure further includes the first electronic component electrically coupled to the circuit board via one or more electronic connections, wherein a height of the particle guard is greater than a height of each of the one or more electrical connections of the first electronic component. The dust guard structure further includes the first side of the circuit board being introduced to an external airflow.
-
公开(公告)号：US10004154B1
公开(公告)日：2018-06-19
申请号：US15722030
申请日：2017-10-02
Applicant: International Business Machines Corporation
Inventor： Michael J. Shapiro , Brian C. Twichell , Brent W. Yardley
CPC classification number: H05K5/0217 , H05K1/11 , H05K1/181 , H05K7/20727 , H05K2201/07 , H05K2201/10371 , H05K2201/2018 , H05K2201/2027 , Y02P70/611
Abstract: An apparatus for a dust guard structure includes a particle guard coupled to a top surface of a circuit board, wherein the particle guard is located along a first side of the circuit board between an edge of the circuit board and a first electronic component. The dust guard structure further includes the first electronic component electrically coupled to the circuit board via one or more electronic connections, wherein a height of the particle guard is greater than a height of each of the one or more electrical connections of the first electronic component. The dust guard structure further includes the first side of the circuit board being introduced to an external airflow.
-
公开(公告)号：US20180049312A1
公开(公告)日：2018-02-15
申请号：US15792953
申请日：2017-10-25
Applicant: Amphenol Corporation
Inventor： Mark W. Gailus , Marc B. Cartier, JR. , Vysakh Sivarajan , David Levine
CPC classification number: H05K1/0222 , H01R43/205 , H05K1/0216 , H05K1/0219 , H05K1/025 , H05K1/0251 , H05K1/0253 , H05K1/0298 , H05K1/115 , H05K3/0047 , H05K3/4038 , H05K3/429 , H05K2201/07 , H05K2201/09063 , H05K2201/09318 , H05K2201/09545 , H05K2201/096 , H05K2201/097 , H05K2201/09718 , H05K2201/09845 , H05K2201/09854 , H05K2201/10189
Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.
-
公开(公告)号：US20180006405A1
公开(公告)日：2018-01-04
申请号：US15598584
申请日：2017-05-18
Applicant: CommScope Technologies LLC
Inventor： Steven Richard Bopp , Neil Ktul Nay
IPC: H01R13/6466 , H01R13/6469 , H01R13/6461 , H05K1/11 , H05K1/02 , H01R24/64 , H01R107/00
CPC classification number: H01R13/6466 , H01R13/6461 , H01R13/6469 , H01R24/64 , H01R2107/00 , H05K1/0228 , H05K1/0239 , H05K1/11 , H05K2201/07 , H05K2201/10189
Abstract: An electrical connector that includes a circuit board having a board substrate that has opposite board surfaces and a thickness measured along an orientation axis that extends between the opposite board surfaces. The circuit board has associated pairs of input and output terminals and signal traces that electrically connect the associated pairs of input and output terminals. The input and output terminals being configured to communicatively coupled to mating and cable conductors, respectively. Each associated pair of input and output terminals is electrically connected through a corresponding signal trace that has a conductive path extending along the board substrate between the corresponding input and output terminals. At least two signal traces form a broadside-coupling region in which the conductive paths of the at least two signal traces are stacked along the orientation axis and spaced apart through the thickness and extend parallel to each other for a crosstalk-reducing distance.
-
公开(公告)号：US09807869B2
公开(公告)日：2017-10-31
申请号：US14947166
申请日：2015-11-20
Applicant: Amphenol Corporation
Inventor： Mark W. Gailus , Marc B. Cartier, Jr. , Vysakh Sivarajan , David Levine
CPC classification number: H05K1/0222 , H01R43/205 , H05K1/0216 , H05K1/0219 , H05K1/025 , H05K1/0251 , H05K1/0253 , H05K1/0298 , H05K1/115 , H05K3/0047 , H05K3/4038 , H05K3/429 , H05K2201/07 , H05K2201/09063 , H05K2201/09318 , H05K2201/09545 , H05K2201/096 , H05K2201/097 , H05K2201/09718 , H05K2201/09845 , H05K2201/09854 , H05K2201/10189
Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and via patterns formed in the plurality of layers, each of the via patterns including first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; ground vias extending through at least the attachment layers, the ground vias including ground conductors; and shadow vias located adjacent to each of the first and second signal vias, wherein the shadow vias are free of conductive material in the attachment layers. The printed circuit board may further include slot vias extending through the attachment layers and located between via patterns.
-
-
-
-
-
-
-
-
-
Search Results
48
records
(took 0.018 seconds)
