公开(公告)号：US20020187661A1

公开(公告)日：2002-12-12

申请号：US10205055

申请日：2002-07-25

Inventor： Yakov Belopolsky ,  John R. Ellis

IPC: H05K001/00

CPC classification number: H01R13/6463 ,  H01R12/7082 ,  H01R12/7088 ,  H01R13/658 ,  H05K1/148 ,  H05K2201/0792 ,  H05K2201/097 ,  H05K2201/10272 ,  H05K2201/1028 ,  H05K2203/1572 ,  Y10S439/941

Abstract: A low inductance power connector for reducing inductance in an electrical conductor is provided. An interface connector connects circuit boards together while reducing inductance and increasing current carrying capacitance. The connector for connecting circuit boards comprises a first contact having a first mating portion and a second mating portion, and a second contact having a first mating portion and a second mating portion, wherein the first and second contacts are interleaved.

Abstract translation: 提供了用于降低电导体中的电感的低电感电源连接器。 接口连接器将电路板连接在一起，同时减少电感和增加载流电容。 用于连接电路板的连接器包括具有第一配合部分和第二配合部分的第一接触件和具有第一配合部分和第二配合部分的第二接触件，其中第一和第二接触件被交错。

公开(公告)号：US06468090B2

公开(公告)日：2002-10-22

申请号：US09409530

申请日：1999-09-30

Applicant: Yakov Belopolsky ,  John R. Ellis

Inventor： Yakov Belopolsky ,  John R. Ellis

IPC: H01R1200

CPC classification number: H01R13/6463 ,  H01R12/7082 ,  H01R12/7088 ,  H01R13/658 ,  H05K1/148 ,  H05K2201/0792 ,  H05K2201/097 ,  H05K2201/10272 ,  H05K2201/1028 ,  H05K2203/1572 ,  Y10S439/941

Abstract: A low inductance power connector for reducing inductance in an electrical conductor is provided. An interface connector connects circuit boards together while reducing inductance and increasing current carrying capacitance. The connector for connecting circuit boards comprises a first contact having a first mating portion and a second mating portion, and a second contact having a first mating portion and a second mating portion, wherein the first and second contacts are interleaved.

公开(公告)号：US06459605B1

公开(公告)日：2002-10-01

申请号：US09637619

申请日：2000-08-11

Applicant: Jeffrey A. Reichard

Inventor： Jeffrey A. Reichard

IPC: H02M100

CPC classification number: H05K1/0265 ,  H05K1/144 ,  H05K2201/0792 ,  H05K2201/09672 ,  H05K2201/0979 ,  H05K2201/10166

Abstract: A switching module includes a first printed circuit board for mounting a switching element. To reduce inductance, the switching module includes a distributed bus. By electrically connecting a power bus disposed on the printed circuit board with a conducting sheet, the switching module provides a distributed bus having an inductance that is smaller than the inductance of the power bus. When the first conducting sheet is on a second printed circuit board, a plurality of conducting posts extends from the first printed circuit board to support the second printed circuit board. Alternatively, the conducting sheet and the power bus can be on the same printed circuit board, in which case a via in contact with the power bus and the conducting sheet provides electrical communication to create a distributed bus.

Abstract translation: 开关模块包括用于安装开关元件的第一印刷电路板。 为了减少电感，开关模块包括分布式总线。 通过将布置在印刷电路板上的电力总线与导电片电连接，开关模块提供具有小于电力总线电感的电感的分布式总线。 当第一导电片位于第二印刷电路板上时，多个导电柱从第一印刷电路板延伸以支撑第二印刷电路板。 或者，导电片和电源总线可以在相同的印刷电路板上，在这种情况下，与电源总线和导电片接触的通孔提供电气通信以产生分布式总线。

公开(公告)号：US5101177A

公开(公告)日：1992-03-31

申请号：US635015

申请日：1990-12-28

Applicant: Hidehiko Norimatsu

Inventor： Hidehiko Norimatsu

IPC: H03B1/00 ,  H03B5/18 ,  H05K1/00 ,  H05K1/02 ,  H05K1/18 ,  H05K3/46

CPC classification number: H05K1/025 ,  H05K1/0216 ,  H05K1/0224 ,  H05K1/0243 ,  H05K1/0298 ,  H05K1/181 ,  H05K2201/0792 ,  H05K2201/093 ,  H05K2201/0969 ,  H05K2201/10068 ,  H05K2201/10166 ,  H05K2201/10174

Abstract: A voltage-controlled oscillator (VCO) mounted on a laminated printed circuit board which has a surface layer, a plurality of intermediate layers, and a back layer. Various component parts of the VCO are arranged on the surface layer. One of the intermediate layers which underlies the surface layer constitutes a ground potential layer and is removed at locations thereof corresponding to the area where the parts of the VCO are positioned.

公开(公告)号：US4626805A

公开(公告)日：1986-12-02

申请号：US727946

申请日：1985-04-26

Applicant: Keith E. Jones

Inventor： Keith E. Jones

IPC: H01L23/12 ,  H01L23/66 ,  H05K1/02 ,  H05K1/11 ,  H05K3/34 ,  H01P5/00

CPC classification number: H01L23/66 ,  H05K1/0243 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H01L2924/3011 ,  H05K1/0219 ,  H05K1/112 ,  H05K2201/0792 ,  H05K2201/09727 ,  H05K2201/09781 ,  H05K2201/10689 ,  H05K3/3421

Abstract: A surface mountable microwave IC package uses printed transmission lines on a printed circuit board in lieu of plumbing between milled packages. A backside co-planar waveguide is connected to a topside microstrip line by a through-hole in a carrier substrate. To compensate for inductance added by the hole and transmission line ends, a gap is adjusted to provide compensation capacitance. Hermetic sealing of the package is assured by brazing a lead frame over the through-hole and using a solder sealed lid. The lid provides both a hermetic seal and shielding.

Abstract translation: 可表面安装的微波IC封装使用印刷电路板上的印刷传输线代替在铣削的封装之间的管道。 背面共面波导通过载体基板中的通孔连接到顶侧微带线。 为了补偿由孔和传输线端增加的电感，调整间隙以提供补偿电容。 通过将引线框架焊接在通孔上并使用焊接密封的盖子来确保封装的密封。 盖子提供气密密封和屏蔽。

公开(公告)号：US3555375A

公开(公告)日：1971-01-12

申请号：US3555375D

申请日：1968-11-29

Applicant: PHILIPS CORP

Inventor： HILBERS ANTONIUS HUBERTUS

IPC: H01L21/60 ,  H01L23/488 ,  H01L23/495 ,  H01L23/66 ,  H05K1/02 ,  H05K1/11 ,  H05K3/34 ,  H01L1/02 ,  H01L1/14

CPC classification number: H01L24/80 ,  H01L23/488 ,  H01L23/49562 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0216 ,  H05K1/116 ,  H05K3/3447 ,  H05K2201/0792 ,  H05K2201/09772 ,  H05K2201/10166 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A HIGH FREQUENCY TRANSISTOR IS DESCRIBED HAVING INPUT, OUTPUT AND COMMON LEADS. IN ORDER TO REDUCE THE UNDESIRED FEEDBACK EFFECT OF A STRAY SERIES INDUCTANCE IN THE COMMON LEAD, THE OUTPUT LEADS ARE ARRANGED SO AS TO CROSS ONE ANOTHER IN SUCH CLOSE PROXIMITY AS TO INDUCTIVE-

LY COUPLE THEM TOGETHER PROVIDING A FEEDBACK OPPOSITE TO THAT OF THE STRAY INDUCTANCE IN ORDER TO COMPENSATE THE LATTER.

公开(公告)号：US11950363B2

公开(公告)日：2024-04-02

申请号：US17542977

申请日：2021-12-06

Applicant: DexCom, Inc.

Inventor： Sean Frick ,  Louis Jung ,  David Lari

IPC: H05K1/09 ,  A61B5/00 ,  A61B5/1468 ,  A61B5/1495 ,  A61B5/24 ,  H01L21/768 ,  H01L21/78 ,  H01L23/36 ,  H01L23/48 ,  H01L23/50 ,  H01L23/552 ,  H05K1/02 ,  H05K1/11 ,  H05K3/02 ,  H05K3/40 ,  A61B5/145 ,  G01N27/327 ,  H05K1/14

CPC classification number: H05K1/112 ,  A61B5/6802 ,  H01L21/768 ,  H01L23/481 ,  H05K1/0262 ,  H05K3/403 ,  A61B5/14532 ,  A61B5/14546 ,  A61B5/1468 ,  A61B5/6848 ,  G01N27/327 ,  H05K1/0219 ,  H05K1/141 ,  H05K2201/0394 ,  H05K2201/049 ,  H05K2201/0792 ,  H05K2201/09063 ,  H05K2201/09181 ,  H05K2201/10151 ,  H05K2201/10378

Abstract: An example sensor interposer employing castellated through-vias formed in a PCB includes a planar substrate defining a plurality of castellated through-vias; a first electrical contact formed on the planar substrate and electrically coupled to a first castellated through-via; a second electrical contact formed on the planar substrate and electrically coupled to a second castellated through-via, the second castellated through-via electrically isolated from the first castellated through-via; and a guard trace formed on the planar substrate, the guard trace having a first portion formed on a first surface of the planar substrate and electrically coupling a third castellated through-via to a fourth castellated through-via, the guard trace having a second portion formed on a second surface of the planar substrate and electrically coupling the third castellated through-via to the fourth castellated through-via, the guard trace formed between the first and second electrical contacts to provide electrical isolation between the first and second electrical contacts.

公开(公告)号：US20140183550A1

公开(公告)日：2014-07-03

申请号：US14142257

申请日：2013-12-27

Applicant: Efficient Power Conversion Corporation

Inventor： David Reusch ,  Johan Tjeerd Strydom

IPC: H01L23/522 ,  H01L27/06

CPC classification number: H01L27/0629 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/15192 ,  H02M7/003 ,  H05K1/0231 ,  H05K1/0243 ,  H05K1/0265 ,  H05K2201/0792 ,  H05K2201/10166 ,  H01L2924/00

Abstract: A highly efficient, single sided circuit board layout design providing magnetic field self-cancellation and reduced parasitic inductance independent of board thickness. The low profile power loop extends through active and passive devices on the top layer of the circuit board, with vias connecting the power loop to a return path in an inner layer of the board. The magnetic effect of the portion of the power loop on the top layer is reduced by locating the inner layer return path directly underneath the power loop path on the top layer.

Abstract translation: 高效的单面电路板布局设计，提供磁场自消除和降低的寄生电感，而与板厚无关。 低轮廓功率回路延伸穿过电路板顶层上的有源和无源器件，其中通孔将功率回路连接到板的内层中的返回路径。 通过将内层返回路径直接定位在顶层上的功率回路路径下方，可以降低功率回路部分功率回路在顶层上的磁效应。

公开(公告)号：US08766430B2

公开(公告)日：2014-07-01

申请号：US13517654

申请日：2012-06-14

Applicant: Ralf Otremba ,  Davide Chiola ,  Erich Griebl ,  Fabio Brucchi

Inventor： Ralf Otremba ,  Davide Chiola ,  Erich Griebl ,  Fabio Brucchi

IPC: H01L23/48

CPC classification number: H01L23/49562 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/4952 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L25/11 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/4903 ,  H01L2924/00014 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/181 ,  H05K1/0296 ,  H05K3/308 ,  H05K2201/0792 ,  H05K2201/10166 ,  H05K2201/10522 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: In accordance with an embodiment of the present invention, a semiconductor module includes a first semiconductor device having a first plurality of leads including a first gate/base lead, a first drain/collector lead, and a first source/emitter lead. The module further includes a second semiconductor device and a circuit board. The second semiconductor device has a second plurality of leads including a second gate/base lead, a second drain/collector lead, and a second source/emitter lead. The circuit board has a plurality of mounting holes, wherein each of the first plurality of leads and the second plurality of leads is mounted into a respective one of the plurality of mounting holes. At the plurality of mounting holes, a first distance from the first gate/base lead to the second gate/base lead is different from a second distance from the first source/emitter lead to the second source/emitter lead.

Abstract translation: 根据本发明的实施例，半导体模块包括具有包括第一栅极/基极引线，第一漏极/集电极引线和第一源极/发射极引线的第一多个引线的第一半导体器件。 该模块还包括第二半导体器件和电路板。 第二半导体器件具有包括第二栅极/基极引线，第二漏极/集电极引线和第二源极/发射极引线的第二多个引线。 电路板具有多个安装孔，其中第一多个引线和第二多个引线中的每一个安装到多个安装孔中的相应一个安装孔中。 在多个安装孔处，从第一栅极/基极引线到第二栅极/基极引线的第一距离与从第一源极/发射极引线到第二源极/发射极引线的第二距离不同。

公开(公告)号：US08384634B2

公开(公告)日：2013-02-26

申请号：US12504220

申请日：2009-07-16

Applicant: Yongman Lee

Inventor： Yongman Lee

IPC: G09G3/36

CPC classification number: G09G3/3655 ,  G02F2001/133328 ,  G02F2001/133331 ,  G02F2201/46 ,  G09G2300/0426 ,  H05K1/0237 ,  H05K1/162 ,  H05K1/189 ,  H05K2201/0792 ,  H05K2201/10136

Abstract: Visual artifacts in a display are reduced by moving, to the extent possible, display driver components to the display surface itself, thereby shortening conductor distances and reducing the parasitic effects caused by parasitic resistance of the conductors between the display power supply and the display, and between the stabilizing capacitors and the display. To avoid interference with the device housing, low-profile driver components, including either or both of stabilizing capacitors and power supply terminals, can be provided and bonded to the surface of the display side of the outer layer of the display. Alternatively, the stabilizing capacitors can be formed on the display side in the same way that, e.g., in an LCD display, the transparent electrodes for controlling the liquid crystals are formed.

Abstract translation: 通过在可能的范围内移动显示器表面本身的显示驱动器组件来减少显示器中的视觉赝像，从而缩短导体距离并减少由于显示电源和显示器之间的导体的寄生电阻引起的寄生效应，以及 在稳定电容器和显示器之间。 为了避免与设备壳体的干涉，可以提供包括稳定电容器和电源端子中的一个或两者的低调驱动器部件并将其结合到显示器的外层的显示侧的表面。 或者，稳定化电容器可以以与例如LCD显示器相同的方式在显示器侧上形成，形成用于控制液晶的透明电极。