公开(公告)号：US20180108604A1

公开(公告)日：2018-04-19

申请号：US15538340

申请日：2016-05-16

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Liqiang CHEN ,  Weifeng ZHOU ,  Wenyue FU ,  Huiji ZHOU

IPC: H01L23/498 ,  H05K1/18

CPC classification number: H01L23/49838 ,  G09F9/30 ,  H01L23/49827 ,  H01L23/4985 ,  H01L2224/32225 ,  H05K1/118 ,  H05K1/189 ,  H05K2201/09227 ,  H05K2201/10128

Abstract: Disclosed are a chip on film and a display device. the chip on film includes a plurality of output pads independent from each other extending in the first direction on a side of a base material; correspondingly, a flexible display panel in the display device includes a plurality of input pads in one-to-one correspondance with output pads extending in the first direction in the bonding region. The chip on film can improve the bonding yield and stability of the display device.

公开(公告)号：US09936572B2

公开(公告)日：2018-04-03

申请号：US14793447

申请日：2015-07-07

Applicant: Dell Products L.P.

Inventor： Umesh Chandra ,  Henry M. Wolst

IPC: H05K7/00 ,  H05K1/02 ,  H01B7/08 ,  H02G3/04 ,  H05K1/11 ,  H05K3/34

CPC classification number: H05K1/025 ,  H05K1/0245 ,  H05K1/111 ,  H05K3/341 ,  H05K2201/09227 ,  H05K2201/09727 ,  H05K2201/10189

Abstract: A differential trace pair system includes a board having a first board structure member and a second board structure member. A differential trace pair in the board includes a first differential trace pair portion of a first width outside the board structure, and a second differential trace pair portion of a second width extending through the board structure. A first outer edge and a second outer edge of the second differential trace pair portion define the second width that is less than the first width. A first board structure member channel is defined by the first outer edge adjacent the first board structure member, a second board structure member channel is defined by the second outer edge adjacent the second board structure member and the first and second board structure member channels provide a third width of the second differential trace pair portion that is less than the second width.

公开(公告)号：US09837343B2

公开(公告)日：2017-12-05

申请号：US14754363

申请日：2015-06-29

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Joon Sung Kim ,  Yong Ho Baek ,  Jung Hyun Cho ,  Eung Suek Lee ,  Jae Hoon Choi ,  Young Gwan Ko

IPC: H05K1/18 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H05K3/46 ,  H01L23/13 ,  H05K3/30

CPC classification number: H01L23/49827 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/5389 ,  H01L24/25 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/19 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/83005 ,  H01L2224/92144 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/3511 ,  H05K1/0298 ,  H05K1/185 ,  H05K3/10 ,  H05K3/30 ,  H05K3/305 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09227 ,  H05K2203/1469 ,  H05K2203/167

Abstract: A chip embedded substrate includes: an insulating layer having outer layer circuit patterns provided on any one of an upper surface and a lower surface thereof; a chip embedded in the insulating layer; and internal circuit patterns included in the insulating layer and disposed between a height of a top surface of the chip and a height of a bottom surface thereof.

公开(公告)号：US20170290146A1

公开(公告)日：2017-10-05

申请号：US15463538

申请日：2017-03-20

Applicant: NITTO DENKO CORPORATION

Inventor： Yuu SUGIMOTO ,  Yoshito FUJIMURA ,  Hiroyuki TANABE

IPC: H05K1/02 ,  H05K1/05 ,  H05K3/46 ,  H05K3/06

CPC classification number: H05K1/0284 ,  H05K1/0274 ,  H05K1/05 ,  H05K3/0008 ,  H05K3/06 ,  H05K3/064 ,  H05K3/108 ,  H05K3/4644 ,  H05K3/4679 ,  H05K2201/09227 ,  H05K2201/09272 ,  H05K2203/0557 ,  H05K2203/056 ,  H05K2203/0562

Abstract: A method of producing a wired circuit board including an insulating layer and a conductive pattern, including: (1), an insulating layer having an inclination face, (2), a metal thin film provided at least on the inclination face, (3), a photoresist provided on the surface of the metal thin film, (4), a light shield portion of a photomask disposed so that a first portion, where the conductive pattern is to be provided in the photoresist, is shielded from light, and the photoresist is exposed to light through the photomask, (5), the first portion of the photoresist is removed to expose the metal thin film corresponding to the first portion, and (6), the conductive pattern is provided on the surface of the metal thin film exposed from the photoresist.

公开(公告)号：US20170280562A1

公开(公告)日：2017-09-28

申请号：US15079811

申请日：2016-03-24

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  David Francis Berdy ,  Daeik Daniel Kim ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Jonghae Kim

IPC: H05K1/18 ,  H05K3/10 ,  H05K3/40 ,  H03H7/01 ,  H05K3/30

CPC classification number: H05K1/181 ,  H01L21/56 ,  H01L23/12 ,  H01L23/15 ,  H01L23/28 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H03H7/0138 ,  H05K1/0218 ,  H05K1/141 ,  H05K3/10 ,  H05K3/303 ,  H05K3/4007 ,  H05K2201/042 ,  H05K2201/045 ,  H05K2201/09227 ,  H05K2201/1003 ,  H05K2201/10098 ,  H05K2201/10962 ,  H05K2201/2036

Abstract: Passive device assembly for accurate ground plane control is disclosed. A passive device assembly includes a device substrate conductively coupled to a ground plane separation control substrate. A passive device disposed on a lower surface of the device substrate is separated from an embedded ground plane mounted on a lower surface of the ground plane separation control substrate by a separation distance. The separation distance is accurately controlled to minimize undesirable interference that may occur to the passive device. The separation distance is provided inside the passive device assembly. Conductive mounting pads are disposed on the lower surface of the ground plane separation control substrate to support accurate alignment of the passive device assembly on a circuit board. By providing sufficient separation distance inside the passive device assembly, the passive device assembly can be precisely mounted onto any circuit board regardless of specific design and layout of the circuit board.

公开(公告)号：US20170261799A1

公开(公告)日：2017-09-14

申请号：US15604877

申请日：2017-05-25

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： CHONG-GUK LEE ,  JOO-YEON WON ,  SE-HUI JANG ,  SU-Ml MOON ,  DONG-WOOK LEE

IPC: G02F1/1345 ,  H01L23/498 ,  H01L27/12 ,  H05K1/02 ,  H01L23/00 ,  H05K1/18

CPC classification number: G02F1/13452 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/48 ,  H01L27/124 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/81191 ,  H01L2924/00014 ,  H01L2924/15159 ,  H05K1/028 ,  H05K1/189 ,  H05K2201/09227 ,  H05K2201/09272 ,  H05K2201/09281 ,  H05K2201/10674 ,  H01L2224/45099

Abstract: A chip on film package includes a base substrate, an input line, an integrated circuit (IC) chip and an output line. The input line is disposed on the base substrate. The IC chip is electrically connected to the input line. The output line includes a main output and a sub output line. The main output line is electrically connected to the IC chip and extends in a first direction from the IC chip. The sub output line is electrically connected to the IC chip. The sub output line includes at least six bending parts, and is extended in the first direction.

公开(公告)号：US09748193B2

公开(公告)日：2017-08-29

申请号：US14698444

申请日：2015-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-ja Kim ,  Jun-young Ko

IPC: H05K3/34 ,  H05K1/11 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L24/17 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16013 ,  H01L2224/16058 ,  H01L2224/16105 ,  H01L2224/16113 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17051 ,  H01L2224/17104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81194 ,  H01L2924/13091 ,  H01L2924/15311 ,  H05K1/111 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09227 ,  H05K2201/0989 ,  H05K2201/09909 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A printed circuit board (PCB) includes: a base substrate including a top surface including an electronic device mounting region; chip connection pads that are provided on the electronic device mounting region; a conductive pattern group that is provided on the top surface of the base substrate and includes an extended conductive pattern extending between two adjacent chip connection pads from among the chip connection pads, the extended conductive pattern being spaced apart from each of the two adjacent chip connection pads; and a solder resist layer that covers a part of the extended conductive pattern and is spaced apart from the chip connection pads.

公开(公告)号：US20170196079A1

公开(公告)日：2017-07-06

申请号：US14983829

申请日：2015-12-30

Applicant: TYCO ELECTRONICS CORPORATION ,  TYCO ELECTRONICS JAPAN G.K.

Inventor： Chad William Morgan ,  Masayuki Aizawa ,  Arash Behziz ,  Brian Patrick Costello ,  Nathan Lincoln Tracy ,  Michael David Herring

IPC: H05K1/02

CPC classification number: H05K1/0245 ,  H05K1/0222 ,  H05K1/024 ,  H05K1/0248 ,  H05K1/115 ,  H05K2201/044 ,  H05K2201/09063 ,  H05K2201/09227 ,  H05K2201/09672 ,  H05K2201/10189

Abstract: Printed circuit includes a planar substrate having opposite sides and a thickness extending therebetween. The sides extend parallel to a lateral plane. The printed circuit also includes a plurality of conductive vias extending through the planar substrate in a direction that is perpendicular to the lateral plane. The conductive vias include ground vias and signal vias. The signal vias form a plurality of quad groups in which each quad group includes a two-by-two array of the signal vias. Optionally, the printed circuit also includes signal traces that electrically couple to the signal vias. The signal traces may form a plurality of quad lines in which each quad line includes four of the signal traces. The four signal traces of each quad line may extend parallel to one another and be in a two-by-two formation.

公开(公告)号：US09664964B2

公开(公告)日：2017-05-30

申请号：US14678406

申请日：2015-04-03

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Chong-Guk Lee ,  Joo-Yeon Won ,  Se-Hui Jang ,  Su-Mi Moon ,  Dong-Wook Lee

IPC: H01L23/48 ,  G02F1/1345 ,  H01L27/12 ,  H01L23/498 ,  H05K1/02 ,  H01L23/00 ,  H05K1/18

CPC classification number: G02F1/13452 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/48 ,  H01L27/124 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/81191 ,  H01L2924/00014 ,  H01L2924/15159 ,  H05K1/028 ,  H05K1/189 ,  H05K2201/09227 ,  H05K2201/09272 ,  H05K2201/09281 ,  H05K2201/10674 ,  H01L2224/45099

Abstract: A chip on film package includes a base substrate, an input line, an integrated circuit (IC) chip and an output line. The input line is disposed on the base substrate. The IC Chip is electrically connected to the input line. The output line includes a main output and a sub output line. The main output line is electrically connected to the IC chip and extends in a first direction from the IC chip. The sub output line is electrically connected to the IC chip. The sub output line includes at least six bending parts, and is extended in the first direction.

公开(公告)号：US20170139503A1

公开(公告)日：2017-05-18

申请号：US15316465

申请日：2015-05-22

Applicant: MITSUBISHI PAPER MILLS LIMITED

Inventor： Takenobu Yoshiki

IPC: G06F3/044

CPC classification number: G06F3/044 ,  G06F2203/04103 ,  G06F2203/04107 ,  H05K1/0274 ,  H05K1/0289 ,  H05K2201/0108 ,  H05K2201/09227

Abstract: Provided is an optically transparent conductive material with which the yield in the production of touchscreens is improved can be provided. The optically transparent conductive material has, on a support, optically transparent sensor parts, optically transparent dummy parts, a terminal part, a peripheral wire part electrically connecting the sensor parts and the terminal part, and an earth part, the peripheral wire part having a parallel portion in which adjacent peripheral wires are parallel with each other, the earth part having a parallel portion in which adjacent earth wires are parallel with each other, an inequality A>B being satisfied when A is the smallest interval distance between peripheral wires in the parallel portion of the peripheral wire part and B is the smallest interval distance between earth wires in the parallel portion of the earth part.