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    TOUCH WINDOW
    31.
    发明申请
    TOUCH WINDOW 有权
    触摸窗口

    公开(公告)号：US20150223324A1

    公开(公告)日：2015-08-06

    申请号：US14483749

    申请日：2014-09-11

    Applicant: LG INNOTEK CO., LTD.

    Inventor： Byeong Seob KIM ,  Ji Sung AHN

    IPC: H05K1/02 ,  G06F1/16 ,  G06F3/044

    CPC classification number: H05K1/0259 ,  G06F1/1643 ,  G06F3/044 ,  G06F2203/04107 ,  H05K3/361 ,  H05K2201/09227 ,  H05K2201/09272 ,  H05K2201/09281 ,  H05K2201/09727

    Abstract: A touch window includes a substrate, a sensing electrode on the substrate, a wire electrically connected with the sensing electrode, a ground wire adjacent to the wire, and a printed circuit board connected with the wire and the ground wire. An overlap length between the ground wire and the printed circuit board is longer than an overlap length between the wire and the printed circuit board. Alternatively or simultaneously, a line width of the ground wire is wider than an interval or gap between the wire parallel to the printed circuit.

    Abstract translation: 触摸窗包括基板，基板上的感测电极，与感测电极电连接的导线，与导线相邻的接地线以及与导线和接地线连接的印刷电路板。 接地线和印刷电路板之间的重叠长度大于导线和印刷电路板之间的重叠长度。 或者或同时地，接地线的线宽比平行于印刷电路的线之间的间隔或间隙宽。

    IMPRINTED MULTI-LAYER MICRO-STRUCTURE
    34.
    发明申请
    IMPRINTED MULTI-LAYER MICRO-STRUCTURE 有权
    改进的多层微结构

    公开(公告)号：US20150060111A1

    公开(公告)日：2015-03-05

    申请号：US14012195

    申请日：2013-08-28

    Applicant: RONALD STEVEN COK

    Inventor： RONALD STEVEN COK

    IPC: H05K1/02

    CPC classification number: H05K1/0274 ,  H05K1/0298 ,  H05K1/097 ,  H05K3/0041 ,  H05K3/12 ,  H05K3/1258 ,  H05K3/1275 ,  H05K3/1283 ,  H05K3/1291 ,  H05K3/465 ,  H05K3/4685 ,  H05K2201/09209 ,  H05K2201/09281 ,  H05K2201/0979 ,  H05K2201/09845 ,  H05K2203/0108

    Abstract: An imprinted micro-structure includes a substrate having a first layer in relation thereto. First, second, and third micro-channels are imprinted in the first layer and have first, second, and third micro-wires respectively located therein. A second layer is adjacent to and in contact with the first layer. Imprinted first and second connecting micro-channels including first and second connecting micro-wires are in contact with the first and second micro-wires respectively and are isolated from the third micro-wire. A third layer is adjacent to and in contact with the second layer and has an imprinted bridge micro-channel with a bridge micro-wire contacting the first and second connecting micro-wires and separate from the third micro-wire so that the first and second micro-wires are electrically connected and electrically isolated from the third micro-wire.

    Abstract translation: 压印的微结构包括具有与之相关的第一层的衬底。 第一，第二和第三微通道印在第一层中，并且分别位于其中的第一，第二和第三微细线。 第二层与第一层相邻并与第一层接触。 包括第一和第二连接微线的印刷的第一和第二连接微通道分别与第一和第二微线接触并与第三微线隔离。 第三层与第二层相邻并与第二层接触，并且具有印刷桥微通道，桥接微线与第一和第二连接微线接触并与第三微线分离，使得第一和第二 微线电连接并与第三微线电隔离。

    ELECTRONIC ASSEMBLIES INCLUDING A SUBASSEMBLY FILM AND METHODS OF PRODUCING THE SAME
    35.
    发明申请
    ELECTRONIC ASSEMBLIES INCLUDING A SUBASSEMBLY FILM AND METHODS OF PRODUCING THE SAME 审中-公开
    包括底片的电子组件及其制造方法

    公开(公告)号：US20140335635A1

    公开(公告)日：2014-11-13

    申请号：US13891637

    申请日：2013-05-10

    Applicant: Sridharan Venk ,  Adam Scotch ,  David Hamby

    Inventor： Sridharan Venk ,  Adam Scotch ,  David Hamby

    IPC: H01L23/00 ,  H01L33/48

    CPC classification number: H01L24/80 ,  H01L25/0753 ,  H01L33/486 ,  H01L33/62 ,  H01L2924/12041 ,  H01L2924/12042 ,  H05K1/141 ,  H05K3/0035 ,  H05K3/281 ,  H05K3/284 ,  H05K3/305 ,  H05K3/368 ,  H05K3/4069 ,  H05K2201/041 ,  H05K2201/049 ,  H05K2201/09281 ,  H05K2201/09727 ,  H05K2201/10106 ,  H01L2924/00

    Abstract: Described herein are electronic assemblies including a subassembly film and methods for making the same. In some embodiments, a first subassembly is formed by placing an electronic die at a die placement location on a subassembly film. A second subassembly may be formed by placing the first subassembly at a subassembly placement position on a base layer, such that electrical contacts/traces on the first film overlap with electrical contacts/traces at a subassembly connection point on the base layer. Placement of the die on the subassembly film may be performed with automatic placement machinery that has a placement accuracy that is greater than that required to place the first subassembly on the base layer. As a result, the costly and time consuming manual inspection of die placement may be avoided.

    Abstract translation: 这里描述的是包括子组件膜的电子组件及其制造方法。 在一些实施例中，通过将电子管芯放置在子组件膜上的管芯放置位置来形成第一子组件。 第二子组件可以通过将第一子组件放置在基底层上的子组件放置位置而形成，使得第一膜上的电接触/迹线与基底层上的子组件连接点处的电触点/迹线重叠。 可以使用具有大于将第一子组件放置在基层上所需的放置精度的自动放置机械来执行模具在子组件薄膜上的放置。 结果，可以避免成本高且耗时的针头放置的手动检查。

    Circuit board layout method
    37.
    发明授权
    Circuit board layout method 失效
    电路板布局方法

    公开(公告)号：US08256111B2

    公开(公告)日：2012-09-04

    申请号：US12645303

    申请日：2009-12-22

    Applicant: Yu-Hsu Lin ,  Jeng-Da Wu ,  Chih-Hang Chao

    Inventor： Yu-Hsu Lin ,  Jeng-Da Wu ,  Chih-Hang Chao

    IPC: H05K3/02 ,  H05K3/10

    CPC classification number: H01L23/50 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0224 ,  H05K1/0253 ,  H05K2201/09281 ,  H05K2201/09681 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  H01L2924/00

    Abstract: A method for laying out a circuit board includes following steps. A substrate board is formed with a plurality of board sides. A ground plane, including a plurality of tiles, is provided. Each ground trace tile is defined by a plurality of ground traces. A signal plane on the substrate board has a plurality of signal traces that comprise of a plurality of straight line segments. Any one ground trace of each tile is arranged at an angle other than zero degrees relative to one determined board side. The straight line segments is applied to be mapped on the ground plane crossing one ground trace of one tile within an angle range determined by the ground traces of the tile and an adjacent diagonal line of the tile. The one ground trace and the straight line segments are applied at an angle movable in a range from 22.5° to 32.5°.

    Abstract translation: 布线电路板的方法包括以下步骤。 衬底板形成有多个板侧。 提供包括多个瓦片的接地平面。 每个接地迹线瓦片由多个接地迹线限定。 衬底板上的信号平面具有包括多个直线段的多个信号迹线。 每个瓦片的任何一个接地迹线相对于一个确定的电路板侧以非零度的角度布置。 直线段被施加以映射在跨越由瓦片的接地轨迹和瓦片的相邻对角线确定的角度范围内的一个瓦片的一个接地轨迹的接地平面上。 一个接地迹线和直线段以可在22.5°至32.5°的范围内的角度施加。

    Printed circuit boards having pads for solder balls and methods for the implementation thereof
    38.
    发明授权
    Printed circuit boards having pads for solder balls and methods for the implementation thereof 有权
    具有用于焊球的焊盘的印刷电路板及其实施方法

    公开(公告)号：US08079011B2

    公开(公告)日：2011-12-13

    申请号：US12000366

    申请日：2007-12-12

    Applicant: Cheng Siew Tay ,  Wendy Chet Ming Ngoh ,  Choi Keng Chan

    Inventor： Cheng Siew Tay ,  Wendy Chet Ming Ngoh ,  Choi Keng Chan

    IPC: G06F17/50 ,  H05K1/16

    CPC classification number: H05K1/111 ,  H05K2201/09227 ,  H05K2201/09281 ,  H05K2201/09481 ,  H05K2201/10734 ,  Y02P70/611 ,  Y10T29/49144 ,  Y10T29/5313

    Abstract: A printed circuit board includes a group of pads suitable to be soldered to a respective group of solder-balls of a device. Each pad of the group has a crack initiation point on its perimeter at a location where cracks in a solder-ball are anticipated to start after that solder-ball is soldered to that pad. For a pad of that group having a microvia located therein, a center of that microvia is located farther than a center of that pad from its crack initiation point. For a pad of that group having a trace merging along a portion of its perimeter, that portion does not include a vicinity of that crack initiation point.

    Abstract translation: 印刷电路板包括适合于焊接到装置的相应组焊球的一组焊盘。 该组的每个焊盘在其焊接球被焊接到该焊盘之后预期在焊球上的裂纹开始的位置处具有在其周边上的裂纹起始点。 对于具有位于其中的微孔的该组的垫，该微孔的中心位于比该垫的中心从其裂纹起始点更远的位置。 对于具有沿着其周边的一部分的轨迹合并的该组的焊盘，该部分不包括该裂纹起始点的附近。

    Printed circuit board
    39.
    发明授权
    Printed circuit board 失效
    印刷电路板

    公开(公告)号：US08053679B2

    公开(公告)日：2011-11-08

    申请号：US12344250

    申请日：2008-12-25

    Applicant: Fa-Ping Fan

    Inventor： Fa-Ping Fan

    IPC: H05K1/11

    CPC classification number: H05K1/111 ,  H05K1/0245 ,  H05K2201/09236 ,  H05K2201/09281 ,  Y02P70/611

    Abstract: An exemplary printed circuit board includes a substrate, a differential transmission line, and at least two weld pad pairs. The differential transmission line and the at least two weld pad pairs are disposed on the substrate. The differential transmission line includes two parallel signal conductors disposed on the substrate. Each of the two signal conductors is electrically connected to an edge of one of the weld pads of a respective pair of the at least two weld pad pairs. Thereby, the two signal conductors of the differential transmission line can extend in the same distance anywhere, particularly in the position where the two signal conductors pass the two weld pad pairs. As a result, the coupling performance and the capability of the differential transmission line to resist electromagnetic interference are both enhanced.

    Abstract translation: 示例性印刷电路板包括基板，差分传输线和至少两个焊盘对。 差分传输线和至少两个焊盘对设置在基板上。 差分传输线包括设置在基板上的两个并行信号导体。 两个信号导体中的每一个电连接到相应的一对至少两个焊盘对的焊接焊盘之一的边缘。 因此，差分传输线的两个信号导体可以在任何地方延伸相同的距离，特别是在两个信号导体通过两个焊盘对的位置。 结果，提高了耦合性能和差动传输线抵抗电磁干扰的能力。

    Printed circuit board
    40.
    发明授权
    Printed circuit board 有权
    印刷电路板

    公开(公告)号：US07973244B2

    公开(公告)日：2011-07-05

    申请号：US11765453

    申请日：2007-06-20

    Applicant: Yu-Hsu Lin ,  Chan-Fei Tai ,  Jeng-Da Wu ,  Chih-Hang Chao

    Inventor： Yu-Hsu Lin ,  Chan-Fei Tai ,  Jeng-Da Wu ,  Chih-Hang Chao

    IPC: H05K1/03

    CPC classification number: H05K1/0248 ,  H05K1/025 ,  H05K1/0366 ,  H05K2201/029 ,  H05K2201/09227 ,  H05K2201/09281

    Abstract: A printed circuit board includes a base formed from a plurality of woven fibers, and signal traces laid on the base. Each of the signal traces includes at least a straight line segment. The signal traces are laid on the base in such a manner that the line segments of the signal traces mapped on the base cross the fibers at angles not equal to zero degrees.

    Abstract translation: 印刷电路板包括由多根编织纤维形成的底座和放置在基座上的信号迹线。 每个信号迹线至少包括直线段。 信号迹线以这样的方式铺设在基座上，使得映射在基座上的信号迹线的线段以不等于零度的角度跨越光纤。

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