公开(公告)号：US08110749B2

公开(公告)日：2012-02-07

申请号：US12390168

申请日：2009-02-20

Applicant: Hideaki Yoshimura ,  Kenji Iida ,  Tomoyuki Abe ,  Yasutomo Maehara ,  Shin Hirano

Inventor： Hideaki Yoshimura ,  Kenji Iida ,  Tomoyuki Abe ,  Yasutomo Maehara ,  Shin Hirano

IPC: H05K1/16

CPC classification number: H05K3/445 ,  H05K3/4608 ,  H05K2201/0323 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/09809

Abstract: Large-sized through holes are formed in a core layer of a printed wiring board. Large-sized vias are formed in the shape of a cylinder along the inward wall surfaces of the large-sized through holes located within a specific area. A filling material fills the inner space of the large-sized via. A small-sized through hole penetrates through the corresponding filling material along the longitudinal axis of the small-sized through hole. A small-sized via is formed in the shape of a cylinder along the inward wall surface of the small-sized through hole. The filling material and the core layer are uniformly distributed within the specific area in the in-plane direction of the core substrate. This results in suppression of uneven distribution of thermal stress in the core layer in the in-plane direction of the core layer.

Abstract translation: 在印刷电路板的芯层中形成大尺寸的通孔。 大尺寸通孔沿着位于特定区域内的大尺寸通孔的内壁表面形成为圆柱体的形状。 填充材料填充大尺寸通孔的内部空间。 小尺寸的通孔穿过相应的填充材料沿着小尺寸通孔的纵向轴线。 小尺寸的通孔沿着小尺寸通孔的内壁表面形成为圆柱体的形状。 填充材料和芯层均匀地分布在芯基板的面内方向的特定区域内。 这导致抑制芯层在芯层的面内方向上的热应力的不均匀分布。

公开(公告)号：US20110068991A1

公开(公告)日：2011-03-24

申请号：US12878268

申请日：2010-09-09

Applicant: Soo-Yong JANG ,  Austin KIM ,  Jae-Ho LEE ,  Young-Soon LEE ,  Ui-Jung KIM

Inventor： Soo-Yong JANG ,  Austin KIM ,  Jae-Ho LEE ,  Young-Soon LEE ,  Ui-Jung KIM

IPC: H01Q1/00 ,  H05K1/00

CPC classification number: H05K1/024 ,  H01Q1/243 ,  H01Q1/38 ,  H01Q1/52 ,  H01Q17/00 ,  H05K1/0253 ,  H05K2201/09036 ,  H05K2201/09309 ,  H05K2201/09609

Abstract: A magnetodielectric substrate includes a first dielectric layer, a second dielectric layer, conductive patterns, and a plurality of air vias. The first dielectric layer has a predetermined height, and the second dielectric layer is stacked on the first dielectric layer. Conductive patterns are coated on an upper surface and a lower surface of one of the first and second dielectric layers. A plurality of air vias is formed with a predetermined diameter and a predetermined interval such that they pass through up to the conductive patterns of the upper and lower surfaces from the dielectric layer on which the conductive patterns are coated.

Abstract translation: 磁电介质基板包括第一电介质层，第二电介质层，导电图案和多个空气通孔。 第一电介质层具有预定的高度，并且第二电介质层堆叠在第一电介质层上。 导电图案涂覆在第一和第二电介质层之一的上表面和下表面上。 多个空气通孔以预定直径和预定间隔形成，使得它们从其上涂覆导电图案的电介质层通过到上表面和下表面的导电图案。

公开(公告)号：US20110018144A1

公开(公告)日：2011-01-27

申请号：US12813692

申请日：2010-06-11

Applicant: Michio Horiuchi ,  Yasue Tokutake ,  Yuichi Matsuda ,  Tomoo Yamasaki ,  Yuta Sakaguchi

Inventor： Michio Horiuchi ,  Yasue Tokutake ,  Yuichi Matsuda ,  Tomoo Yamasaki ,  Yuta Sakaguchi

IPC: H01L23/48 ,  H05K1/00

CPC classification number: H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H05K1/0227 ,  H05K1/162 ,  H05K3/4605 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09345 ,  H05K2201/09609

Abstract: A wiring board includes a core substrate including an insulation base member; linear conductors configured to pierce from a first surface of the insulation base member to a second surface of the insulation base member; a ground wiring group including a first ground wiring formed on the first surface of the core substrate, and a belt-shaped second ground wiring formed on the second surface of the core substrate and electrically connected to the first ground wiring by way of a part of the linear conductors; and an electric power supply wiring group including a first electric power supply wiring formed on the first surface, and a second electric power supply wiring formed on the second surface and electrically connected to the first electric power supply wiring by way of a part of the plural linear conductors.

Abstract translation: 布线基板包括：具有绝缘基体的芯基板; 构造成从所述绝缘基材的第一表面刺穿到所述绝缘基材的第二表面的线状导体; 包括形成在芯基板的第一表面上的第一接地布线的接地布线组和形成在芯基板的第二表面上的带状第二接地布线，并且通过一部分电连接到第一接地布线 线性导体; 以及电源布线组，其包括形成在第一表面上的第一电力供给布线和形成在第二表面上的第二电力供应布线，并且通过多个部分中的一部分电连接到第一电力布线 线性导体。

公开(公告)号：US20110013340A1

公开(公告)日：2011-01-20

申请号：US12833185

申请日：2010-07-09

Applicant: Michio HORIUCHI ,  Yasue Tokutake ,  Yuichi Matsuda ,  Yukio Shimizu ,  Tomoo Yamasaki ,  Yuta Sakaguchi

Inventor： Michio HORIUCHI ,  Yasue Tokutake ,  Yuichi Matsuda ,  Yukio Shimizu ,  Tomoo Yamasaki ,  Yuta Sakaguchi

IPC: H01G4/06 ,  H05K3/30

CPC classification number: H05K1/162 ,  H01G4/012 ,  H01G4/232 ,  H01G4/302 ,  H05K1/0287 ,  H05K1/0306 ,  H05K2201/09263 ,  H05K2201/09563 ,  H05K2201/09609 ,  H05K2201/097 ,  H05K2201/09945

Abstract: A capacitor includes a dielectric substrate and a large number of filamentous conductors formed to penetrate through the dielectric substrate in a thickness direction thereof. An electrode is connected to only respective one ends of a plurality of filamentous conductors constituting one of groups each composed of a plurality of filamentous conductors. The electrode is disposed in at least one position on each of both surfaces of the dielectric substrate, or in at least two positions on one of the surfaces. Further, an insulating layer is formed on each of both surfaces of the dielectric substrate so as to cover regions between the electrodes, and a conductor layer is formed on the corresponding insulating layer integrally with a desired number of electrodes.

Abstract translation: 电容器包括电介质基板和形成为在其厚度方向上穿过电介质基板的大量丝状导体。 电极仅与构成一组各自由多根丝状导体构成的多个丝状导体的相应一端连接。 电极设置在电介质基板的两个表面的每一个上的至少一个位置，或者在其中一个表面上的至少两个位置。 此外，在电介质基板的两个表面的每个表面上形成绝缘层，以覆盖电极之间的区域，并且在相应的绝缘层上形成与期望数量的电极一体的导体层。

公开(公告)号：US20110012266A1

公开(公告)日：2011-01-20

申请号：US12832177

申请日：2010-07-08

Applicant: Michio HORIUCHI ,  Yasue Tokutake ,  Yuichi Matsuda ,  Tomoo Yamasaki ,  Yuta Sakaguchi

Inventor： Michio HORIUCHI ,  Yasue Tokutake ,  Yuichi Matsuda ,  Tomoo Yamasaki ,  Yuta Sakaguchi

IPC: H01L23/538 ,  H01L21/50

CPC classification number: H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K1/185 ,  H05K3/4605 ,  H05K2201/0116 ,  H05K2201/09609 ,  H05K2201/09945 ,  H05K2201/10674 ,  H05K2203/0315 ,  H05K2203/1142 ,  H01L2924/00

Abstract: In a semiconductor device, a substrate includes a plurality of line conductors which penetrate the substrate from a top surface to a bottom surface of the substrate. A semiconductor chip is secured in a hole of the substrate. A first insulating layer is formed on the top surfaces of the substrate and the semiconductor chip. A first wiring layer is formed on the first insulating layer and electrically connected via through holes of the first insulating layer to the semiconductor chip and some line conductors exposed to one of the through holes. A second insulating layer is formed on the bottom surfaces of the substrate and the semiconductor chip. A second wiring layer is formed on the second insulating layer and electrically connected via a through hole of the second insulating layer to some line conductors exposed to the through hole.

Abstract translation: 在半导体器件中，衬底包括从衬底的顶表面到底表面穿透衬底的多个线导体。 半导体芯片固定在基板的孔中。 在衬底和半导体芯片的顶表面上形成第一绝缘层。 第一布线层形成在第一绝缘层上，并且经由第一绝缘层的通孔与半导体芯片电连接，一些线导体暴露于一个通孔。 在基板和半导体芯片的底面上形成第二绝缘层。 第二布线层形成在第二绝缘层上，并且经由第二绝缘层的通孔与暴露于通孔的一些线导体电连接。

公开(公告)号：US20100307808A1

公开(公告)日：2010-12-09

申请号：US12792334

申请日：2010-06-02

Applicant: Michio HORIUCHI ,  Yasue TOKUTAKE ,  Yuichi MATSUDA ,  Masao NAKAZAWA

Inventor： Michio HORIUCHI ,  Yasue TOKUTAKE ,  Yuichi MATSUDA ,  Masao NAKAZAWA

IPC: H05K1/11

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H05K1/0287 ,  H05K1/0306 ,  H05K3/4605 ,  H05K3/4644 ,  H05K2201/09609 ,  H05K2201/09945 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A wiring board includes a core substrate having a structure including an insulating base material and a large number of filamentous conductors densely provided in the insulating base material and piercing the insulating base material in a thickness direction thereof. Pads made of portions of wiring layers are oppositely disposed on both surfaces of the core substrate and electrically connected to opposite ends of a plurality of filamentous conductors in such a manner that the pads share the filamentous conductors. A wiring connection between one surface side and the other surface side of the core substrate is made through the pads. The insulating base material is made of an inorganic dielectric. Pads made of portions of the wiring layers are disposed on both surfaces of the core substrate and electrically connected only to corresponding one end sides of different groups each formed of a plurality of filamentous conductors.

Abstract translation: 布线基板包括芯基板，该芯基板具有密封地设置在绝缘基材中的绝缘基材和大量丝状导体，并且在其厚度方向上刺穿绝缘基材。 由布线层部分构成的垫相对地设置在芯基板的两个表面上，并且以多个丝状导体的相对端电连接，使得焊盘共享丝状导体。 通过焊盘制造芯基板的一个表面侧和另一个表面侧之间的布线连接。 绝缘基材由无机电介质制成。 由布线层的一部分制成的垫片设置在芯基板的两个表面上，并且仅电连接到由多个丝状导体形成的不同组的相应一端侧。

公开(公告)号：US20100307798A1

公开(公告)日：2010-12-09

申请号：US12477853

申请日：2009-06-03

Applicant: Jamal S. Izadian

Inventor： Jamal S. Izadian

IPC: H05K1/03

CPC classification number: H05K1/142 ,  H01L23/642 ,  H01L23/66 ,  H01L24/16 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L2224/02379 ,  H01L2224/2402 ,  H01L2224/2405 ,  H01L2224/24101 ,  H01L2224/24145 ,  H01L2224/24226 ,  H01L2224/48101 ,  H01L2224/48227 ,  H01L2224/49173 ,  H01L2224/82203 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01056 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/3025 ,  H01R12/523 ,  H05K1/024 ,  H05K1/0245 ,  H05K1/025 ,  H05K1/14 ,  H05K2201/044 ,  H05K2201/0715 ,  H05K2201/09609 ,  H05K2201/097 ,  H01L2924/00

Abstract: Traditional High Speed Electronic Systems Interconnect experience several bandwidth bottlenecks along the multiplicity of signal paths that limits the information throughput. Here we build upon the cellular interconnect concept of PMTL, the Periodic Micro Transmission Line which was introduced in an earlier patent application, and provide a new type of transmission line VMPL, as the Vertical Micro Transmission Line approach to make all the elements of a high speed interconnect wideband, unified, scalable, and practical for high volume manufacturing. This provides total connectivity improvements from end-to-end of electronic systems that demands higher bandwidth, and increased information throughput, thermal management, and impeccable signal integrity. The technologies introduced here provide solutions for any level of the fan out from chips to systems, in CMOS, or Packages, and PCB's.

Abstract translation: 传统的高速电子系统互连经历了多种信号路径的带宽瓶颈，限制了信息吞吐量。 在这里，我们建立在早期专利申请中介绍的PMTL（即周期性微输电线路）的蜂窝互连概念的基础之上，并提供了一种新型的传输线VMPL，作为垂直微型传输线路的方法，使所有元素的高度 高速互连宽带，统一，可扩展，实用于大批量生产。 这提供了从端到端的电子系统的全面连接性改进，其要求更高的带宽，增加的信息吞吐量，热管理和无可挑剔的信号完整性。 这里介绍的技术为芯片到系统，CMOS或封装以及PCB中的任何级别的风扇提供了解决方案。

公开(公告)号：US20100244871A1

公开(公告)日：2010-09-30

申请号：US12709619

申请日：2010-02-22

Applicant: James L. Blair ,  David W. Waite ,  Ashish Lohiya ,  Saritha Narra ,  Jeffrey T. Smith ,  Arvid G. Sammuli

Inventor： James L. Blair ,  David W. Waite ,  Ashish Lohiya ,  Saritha Narra ,  Jeffrey T. Smith ,  Arvid G. Sammuli

IPC: G01R31/02 ,  H01R12/14

CPC classification number: H05K1/112 ,  G01R1/07378 ,  G01R31/2889 ,  H05K1/0219 ,  H05K2201/0314 ,  H05K2201/09309 ,  H05K2201/09418 ,  H05K2201/09609 ,  H05K2201/10378 ,  H05K2201/10719 ,  H05K2203/167

Abstract: Space transformer connectors for coupling printed circuit boards and/or other electrical connections are disclosed. A scalar design of a multilayer space transformer connector allows for a variety of pad-array field connections. A conductive elastomer interface provides for repeated and consistent coupling and decoupling of the space transformer connector.

Abstract translation: 公开了用于耦合印刷电路板和/或其它电连接的空间变压器连接器。 多层空间变压器连接器的标量设计允许各种焊盘阵列现场连接。 导电弹性体接口提供空间变压器连接器的重复和一致的耦合和去耦。

公开(公告)号：US07670144B2

公开(公告)日：2010-03-02

申请号：US11563311

申请日：2006-11-27

Applicant: Eiichi Ito ,  Koji Tsuda ,  Tadashi Minakuchi ,  Mitsuhiro Matsumoto

Inventor： Eiichi Ito ,  Koji Tsuda ,  Tadashi Minakuchi ,  Mitsuhiro Matsumoto

IPC: H01R33/00

CPC classification number: H05K3/103 ,  H05K1/0287 ,  H05K2201/0715 ,  H05K2201/09263 ,  H05K2201/09609 ,  H05K2201/10287 ,  H05K2201/10598

Abstract: There is provided a method of manufacturing a conductive layer of in a signal transmission substrate. The method includes sewing conductive thread in sheet-like material having an insulating property so as to form one of a plurality of low resistance regions using the conductive thread in a high resistance region formed by the sheet-like material, moving the conductive thread from an end point of a previously sewed low resistance region to a start point of a low resistance region to be sewed subsequently, repeating the sewing and moving steps to form the plurality of low resistance regions in the high resistance region, and forming a plurality of holes in the conductive layer by press working so that an electrical component attached to at least one of the plurality of holes is able to transmit a signal between neighboring ones of the plurality of low resistance regions.

Abstract translation: 提供了一种在信号传输基板中制造导电层的方法。 该方法包括将具有绝缘性的片状材料中的导电线缝合，以便在由片状材料形成的高电阻区域中使用导电线形成多个低电阻区域中的一个，将导电线从 先前缝合的低电阻区域的终点到随后要缝制的低电阻区域的起始点，重复缝合和移动步骤以在高电阻区域中形成多个低电阻区域，并且形成多个孔 所述导电层通过冲压加工使得附接到所述多个孔中的至少一个孔的电气部件能够在所述多个低电阻区域中的相邻电阻区域之间传输信号。

公开(公告)号：US20100044876A1

公开(公告)日：2010-02-25

申请号：US12613413

申请日：2009-11-05

Applicant: Mark S. Johnson

Inventor： Mark S. Johnson

IPC: H01L23/498

CPC classification number: H05K3/428 ,  H01L21/4857 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/16227 ,  H05K1/0287 ,  H05K3/108 ,  H05K2201/09609 ,  H05K2201/10378

Abstract: Methods for fabricating conductive structures on and/or in interposing devices and microfeature devices that are formed using such methods are disclosed herein. In one embodiment, a method for fabricating interposer devices having substrates includes forming a plurality of conductive sections on a first substrate in a first pattern. The method continues by forming a plurality of conductive sections on a second substrate in a second pattern. The method further includes constructing a plurality of conductive lines in a common third pattern on both the first substrate and the second substrate. The conductive lines can be formed on the first and second substrates either before or after forming the first pattern of conductive sections on the first substrate and/or forming the second pattern of conductive sections on the second substrate.

Abstract translation: 在此公开了使用这种方法形成的在和/或介入装置和微特征装置之间的导电结构的制造方法。 在一个实施例中，一种用于制造具有衬底的插入器器件的方法包括以第一图案在第一衬底上形成多个导电部分。 该方法通过在第二图案的第二基板上形成多个导电部分来继续。 该方法还包括在第一基板和第二基板上在公共第三图案中构造多条导线。 导电线可以在形成第一衬底上的第一导电部分图案之前或之后形成在第一衬底和第二衬底上，和/或在第二衬底上形成导电部分的第二图案。