公开(公告)号：US08745863B2

公开(公告)日：2014-06-10

申请号：US13169674

申请日：2011-06-27

Applicant: Motoo Asai ,  Dongdong Wang ,  Takahiro Mori

Inventor： Motoo Asai ,  Dongdong Wang ,  Takahiro Mori

IPC: H01K3/10

CPC classification number: H05K3/423 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/036 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/381 ,  H05K3/385 ,  H05K3/387 ,  H05K3/388 ,  H05K3/426 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/0315 ,  H05K2203/0733 ,  H05K2203/0773 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599

Abstract: A method of manufacturing a multi-layer printed circuit board includes the following steps (A) and (B). (A) Providing penetrating openings which are formed into through holes and each of which has a small diameter for a core substrate, and (B) providing penetrating openings which are formed into through holes each having a large diameter for the core substrate.

Abstract translation: 制造多层印刷电路板的方法包括以下步骤（A）和（B）。 （A）提供穿透开口，其形成为通孔，并且每个具有用于芯基板的小直径，以及（B）提供形成为具有用于芯基板的大直径的通孔的穿透开口。

公开(公告)号：US08683684B2

公开(公告)日：2014-04-01

申请号：US13200920

申请日：2011-10-05

Applicant: Suk-Hyeon Cho ,  Je-Gwang Yoo ,  Byung-Moon Kim ,  Han-Seo Cho

Inventor： Suk-Hyeon Cho ,  Je-Gwang Yoo ,  Byung-Moon Kim ,  Han-Seo Cho

IPC: H05K3/30

CPC classification number: H05K1/185 ,  H01L24/97 ,  H01L31/0203 ,  H01L33/486 ,  H01L33/64 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H05K1/056 ,  H05K1/181 ,  H05K1/186 ,  H05K3/108 ,  H05K2201/0108 ,  H05K2201/0352 ,  H05K2201/09736 ,  H05K2201/10106 ,  H05K2201/10121 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/92247 ,  H01L2224/0401

Abstract: A method of manufacturing an optical component embedded printed circuit board, the method including: stacking a first insulation layer on one side of a metal core; embedding an optical component in a cavity formed in the metal core; stacking a second insulation layer of a transparent material on the other side of the metal core; and forming a circuit pattern on the first insulation layer, the circuit pattern electrically connected with the optical component.

Abstract translation: 一种制造光学部件嵌入式印刷电路板的方法，所述方法包括：在金属芯的一侧上堆叠第一绝缘层; 将光学部件嵌入形成在所述金属芯中的空腔中; 在金属芯的另一侧堆叠透明材料的第二绝缘层; 以及在所述第一绝缘层上形成电路图案，所述电路图案与所述光学部件电连接。

公开(公告)号：US08664534B2

公开(公告)日：2014-03-04

申请号：US11915097

申请日：2006-05-19

Applicant: Kazumasa Takeuchi ,  Nozomu Takano ,  Masaki Yamaguchi ,  Makoto Yanagida

Inventor： Kazumasa Takeuchi ,  Nozomu Takano ,  Masaki Yamaguchi ,  Makoto Yanagida

IPC: H05K1/00

CPC classification number: H05K1/0281 ,  H05K1/0265 ,  H05K1/056 ,  H05K2201/0352 ,  H05K2201/09736

Abstract: It is an object of the present invention to provide a printed circuit board that can be housed at high density in the enclosures of electronic devices. The printed circuit board (40) according to a preferred embodiment of the invention has a construction with a substrate (1), a conductor (7) formed in a flexible region (36) and conductors (8,9) formed in non-flexible regions (46). The conductor (7) formed in the flexible region (36) has a total thickness of 1-30 μm, and the conductors (8,9) formed in the non-flexible regions (46) have a total thickness of 30-150 μm.

Abstract translation: 本发明的目的是提供一种能够以高密度容纳在电子设备的外壳中的印刷电路板。 根据本发明的优选实施例的印刷电路板（40）具有基底（1），形成在柔性区域（36）中的导体（7）和形成为非柔性的导体（8,9）的结构 地区（46）。 形成在柔性区域（36）中的导体（7）具有1-30μm的总厚度，并且形成在非柔性区域（46）中的导体（8,9）的总厚度为30-150μm 。

公开(公告)号：US08531023B2

公开(公告)日：2013-09-10

申请号：US13383895

申请日：2010-06-25

Applicant: Akinobu Shibuya ,  Akira Ouchi

Inventor： Akinobu Shibuya ,  Akira Ouchi

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L21/563 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/498 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01004 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K1/0242 ,  H05K1/0243 ,  H05K2201/09736 ,  H05K2201/09845 ,  H05K2201/10674 ,  H01L2924/00

Abstract: Disclosed is a substrate for a semiconductor package in which leakage of radiation noise from a gap between a semiconductor element and a mounting substrate can be prevented. The substrate for the semiconductor package includes a coplanar waveguide including a signal and ground electrodes on the mounting substrate, the signal electrode flip-chip connected to the semiconductor element, the ground electrodes arranged on both sides of the signal electrode with intervals therebetween. A step part is formed in the ground electrodes in an outer circumferential part of a mounting region of the semiconductor element, the step part having a larger distance between upper surfaces of the mounting substrate and the ground electrode in the outer circumferential part of the mounting region than such distance in the mounting region, and an insulator for covering the signal electrode in the outer circumferential part of the mounting region is formed.

Abstract translation: 公开了一种用于半导体封装的衬底，其中可以防止辐射噪声从半导体元件和安装衬底之间的间隙泄漏。 用于半导体封装的衬底包括共面波导，其包括安装衬底上的信号和接地电极，连接到半导体元件的信号电极倒装芯片，布置在信号电极的两侧上的接地电极，间隔。 在半导体元件的安装区域的外周部的接地电极中形成台阶部，台阶部在安装基板的上表面与安装区域的外周部的接地电极之间具有较大的距离 形成安装区域的距离，并且形成用于覆盖安装区域的外周部分中的信号电极的绝缘体。

公开(公告)号：US20130134586A1

公开(公告)日：2013-05-30

申请号：US13727116

申请日：2012-12-26

Applicant: STATS ChipPAC, Ltd.

Inventor： KiYoun Jang ,  SungSoo Kim ,  YongHee Kang

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L21/4846 ,  H01L21/6835 ,  H01L23/498 ,  H01L23/49827 ,  H01L24/06 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2224/0401 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K3/108 ,  H05K3/205 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/097 ,  H05K2201/09736 ,  H05K2203/049 ,  H05K2203/1476 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate, a first recessed conductive layer embedded and recessed into a first surface of the substrate, and a first raised conductive layer disposed above the first surface. A first vertical offset exists between an upper surface of the first recessed conductive layer and an upper surface of the first raised conductive layer. The device includes a second recessed conductive layer embedded and recessed into a second surface of the substrate. The second surface of the substrate is opposite the first surface. The device includes a second raised conductive layer disposed beneath the second surface and an interconnect structure disposed on the first recessed and raised conductive layers and the second recessed and raised conductive layers. A second vertical offset exists between a lower surface of the second recessed conductive layer and a lower surface of the second recessed conductive layer.

Abstract translation: 半导体器件包括衬底，嵌入并凹入到衬底的第一表面中的第一凹陷导电层和设置在第一表面上方的第一凸起导电层。 在第一凹陷导电层的上表面和第一凸起导电层的上表面之间存在第一垂直偏移。 该器件包括嵌入并凹入到衬底的第二表面中的第二凹陷导电层。 基板的第二表面与第一表面相对。 该装置包括设置在第二表面下方的第二凸起导电层和设置在第一凹入和凸起导电层上的互连结构和第二凹入和凸起导电层。 在第二凹陷导电层的下表面和第二凹陷导电层的下表面之间存在第二垂直偏移。

公开(公告)号：US08426739B2

公开(公告)日：2013-04-23

申请号：US12745667

申请日：2008-12-01

Applicant: Kwang Tae Lee ,  Sung Gue Lee ,  Jae Bong Choi

Inventor： Kwang Tae Lee ,  Sung Gue Lee ,  Jae Bong Choi

IPC: H05K1/03

CPC classification number: H05K3/0097 ,  H05K1/0271 ,  H05K3/0052 ,  H05K2201/09354 ,  H05K2201/09736 ,  H05K2201/09781 ,  H05K2201/2009 ,  H05K2203/0169

Abstract: Disclosed is a printed circuit board including an insulation member on which a first region and a second region are defined, a circuit pattern formed on the first region, and a support member formed on the second region.

Abstract translation: 公开了一种印刷电路板，包括：绝缘部件，其上限定有第一区域和第二区域;形成在第一区域上的电路图案;以及形成在第二区域上的支撑部件。

公开(公告)号：US08410374B2

公开(公告)日：2013-04-02

申请号：US12582050

申请日：2009-10-20

Applicant: Toru Furuta ,  Kotaro Takagi ,  Michio Ido ,  Fumitaka Takagi

Inventor： Toru Furuta ,  Kotaro Takagi ,  Michio Ido ,  Fumitaka Takagi

IPC: H05K1/11

CPC classification number: H05K1/111 ,  H01L2224/16225 ,  H01L2224/73204 ,  H05K3/108 ,  H05K3/243 ,  H05K3/323 ,  H05K3/4602 ,  H05K2201/0949 ,  H05K2201/09736 ,  H05K2201/10674 ,  H05K2203/0369 ,  H05K2203/0574 ,  Y02P70/611

Abstract: A printed wiring board has an insulative board having a first surface and a second surface on the opposite side of the first surface, a wiring formed on the first surface of the insulative board and having a pad and a conductive circuit contiguous to the pad, and a metal film formed on the pad. The pad is provided to mount an electronic component having a gold bump. The pad has a thickness which is greater than a thickness of the conductive circuit.

Abstract translation: 印刷电路板具有绝缘板，其具有在第一表面的相对侧上的第一表面和第二表面，在绝缘板的第一表面上形成的布线，并具有与该焊盘相邻的焊盘和导电电路，以及 形成在垫上的金属膜。 提供垫以安装具有金凸块的电子部件。 焊盘的厚度大于导电电路的厚度。

公开(公告)号：US20130068754A1

公开(公告)日：2013-03-21

申请号：US13674828

申请日：2012-11-12

Applicant: Watlow Electric Manufacturing Company

Inventor： Kevin Ptasienski ,  James McMillin ,  Thomas T. Nagl ,  Rolando O. Juliano

IPC: H05B3/20

CPC classification number: H05B3/20 ,  H05B3/26 ,  H05B3/28 ,  H05B2203/003 ,  H05B2203/013 ,  H05B2203/017 ,  H05B2203/037 ,  H05K1/0263 ,  H05K1/0265 ,  H05K1/167 ,  H05K3/1241 ,  H05K2201/09736 ,  H05K2203/0126 ,  Y10T29/49099

Abstract: A layered heater is provided that includes at least one resistive layer having a resistive circuit pattern, the resistive circuit pattern defining a length, a width, and a thickness, wherein the thickness varies along the length of the resistive circuit pattern and/or the width of the resistive circuit pattern for a variable watt density. The present disclosure also provides layered heaters having a resistive circuit pattern with a variable thickness along with a variable width and/or spacing of the resistive circuit pattern in order to produce a variable watt density.

Abstract translation: 提供了层状加热器，其包括具有电阻电路图案的至少一个电阻层，电阻电路图案限定长度，宽度和厚度，其中厚度沿电阻电路图案的长度和/或宽度 的电阻电路图案用于可变瓦特密度。 本公开还提供了具有可变厚度的电阻电路图案以及电阻电路图案的可变宽度和/或间隔以便产生可变瓦特密度的分层加热器。

公开(公告)号：US20120291272A1

公开(公告)日：2012-11-22

申请号：US13472937

申请日：2012-05-16

Applicant: Kyung Ho LEE ,  Se Min Oh ,  Chang Hwan Choi ,  Choon Keun Lee ,  Jeong Yeol Moon ,  Jong Rip Kim

Inventor： Kyung Ho LEE ,  Se Min Oh ,  Chang Hwan Choi ,  Choon Keun Lee ,  Jeong Yeol Moon ,  Jong Rip Kim

IPC: H05K3/00

CPC classification number: H05K1/028 ,  H05K1/0218 ,  H05K2201/0191 ,  H05K2201/0352 ,  H05K2201/0715 ,  H05K2201/09736 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126

Abstract: An FPCB and a method of manufacturing the same, in which an electrical signal-conductive portion of the FPCB is subjected to little stress so as not to be broken by fatigue in spite of repeated bending of the FPCB, thereby increasing the lifetime of the FPCB.

公开(公告)号：US20120273254A1

公开(公告)日：2012-11-01

申请号：US13217626

申请日：2011-08-25

Applicant: HUA-LI ZHOU ,  CHIA-NAN PAI ,  SHOU-KUO HSU

Inventor： HUA-LI ZHOU ,  CHIA-NAN PAI ,  SHOU-KUO HSU

IPC: H01B5/00

CPC classification number: H05K1/111 ,  H05K1/0242 ,  H05K1/025 ,  H05K2201/09736 ,  Y02P70/611

Abstract: A pad includes a first mating section and a second mating section. The first mating section includes a first horizontal plane and a first inclined plane. The second mating section includes a second horizontal plane and a second inclined plane. The first mating section is a copper foil capable of being connected to a wire. The second mating section is made of insulating material. The first inclined plane and the second inclined plane are bonded together.

Abstract translation: 垫包括第一配合部分和第二配合部分。 第一配合部分包括第一水平面和第一倾斜平面。 第二配合部分包括第二水平面和第二倾斜平面。 第一配合部分是能够连接到电线的铜箔。 第二配合部分由绝缘材料制成。 第一倾斜平面和第二倾斜平面结合在一起。