公开(公告)号：US20220157602A1

公开(公告)日：2022-05-19

申请号：US16951495

申请日：2020-11-18

Applicant: Applied Materials, Inc.

Inventor： Madhu Santosh Kumar Mutyala ,  Deenesh Padhi ,  Hang Yu

IPC: H01L21/02 ,  H01L21/67 ,  C23C16/455 ,  H01L21/3065

Abstract: Exemplary deposition methods may include introducing a precursor into a processing region of a semiconductor processing chamber via a faceplate of the semiconductor processing chamber. The methods may include flowing an oxygen-containing precursor into the processing region from beneath a pedestal of the semiconductor processing chamber. The pedestal may support a substrate. The substrate may define a trench in a surface of the substrate. The methods may include forming a first plasma of the precursor in the processing region of the semiconductor processing chamber. The methods may include depositing a first oxide film within the trench. The methods may include forming a second plasma in the processing region. The methods may include etching the first oxide film, while flowing the oxygen-containing precursor. The methods may include re-forming the first plasma in the processing region. The methods may also include depositing a second oxide film over the etched oxide film.

公开(公告)号：US20220122872A1

公开(公告)日：2022-04-21

申请号：US17073071

申请日：2020-10-16

Applicant: Applied Materials, Inc.

Inventor： Akhil Singhal ,  Allison Yau ,  Zeqiong Zhao ,  Sang-Jin Kim ,  Zhijun Jiang ,  Deenesh Padhi ,  Ganesh Balasubramanian

IPC: H01L21/683 ,  C25D7/00 ,  H02N13/00

Abstract: Semiconductor processing systems and method are described that may include flowing deposition precursors into a substrate processing region of a semiconductor processing chamber, where the substrate processing region includes an electrostatic chuck. The methods may further include depositing a seasoning layer on the electrostatic chuck from the deposition precursors to form a seasoned electrostatic chuck. The seasoning layer may be characterized by a dielectric constant greater than or about 3.5. The methods may still further include applying a voltage to the seasoned electrostatic chuck of greater than or about 500 V. The seasoned electrostatic chuck may be characterized by a leakage current of less than or about 25 mA when the voltage is applied.

公开(公告)号：US20220119952A1

公开(公告)日：2022-04-21

申请号：US17074961

申请日：2020-10-20

Applicant: Applied Materials, Inc.

Inventor： Rana Howlader ,  Hang Yu ,  Madhu Santosh Kumar Mutyala ,  Zheng John Ye ,  Abhigyan Keshri ,  Sanjay Kamath ,  Daemian Raj Benjamin Raj ,  Deenesh Padhi

IPC: C23C16/50 ,  C23C16/40 ,  H01L21/02 ,  C23C16/458 ,  C23C16/455

Abstract: Exemplary deposition methods may include electrostatically chucking a semiconductor substrate at a first voltage within a processing region of a semiconductor processing chamber. The methods may include performing a deposition process. The deposition process may include forming a plasma within the processing region of the semiconductor processing chamber. The methods may include halting formation of the plasma within the semiconductor processing chamber. The methods may include, simultaneously with the halting, increasing the first voltage of electrostatic chucking to a second voltage. The methods may include purging the processing region of the semiconductor processing chamber.

公开(公告)号：US20220102179A1

公开(公告)日：2022-03-31

申请号：US17036048

申请日：2020-09-29

Applicant: Applied Materials, Inc.

Inventor： Zheng John Ye ,  Daemian Raj Benjamin Raj ,  Rana Howlader ,  Abhigyan Keshri ,  Sanjay G. Kamath ,  Dmitry A. Dzilno ,  Juan Carlos Rocha-Alvarez ,  Shailendra Srivastava ,  Kristopher R. Enslow ,  Xinhai Han ,  Deenesh Padhi ,  Edward P. Hammond

IPC: H01L21/683 ,  H01L21/67 ,  H01J37/32

Abstract: Exemplary semiconductor processing systems may include a processing chamber and an electrostatic chuck disposed at least partially within the processing chamber. The electrostatic chuck may include at least one electrode and a heater. A semiconductor processing system may include a power supply to provide a signal to the electrode to provide electrostatic force to secure a substrate to the electrostatic chuck. The system may also include a filter communicatively coupled between the power supply and the electrode. The filter is configured to remove or reduce noise introduced into the chucking signal by operating the heater while the electrostatic force on the substrate is maintained. The filter may include active circuitry, passive circuitry, or both, and may include an adjustment circuit to set the gain of the filter so that an output signal level from the filter corresponds to an input signal level for the filter.

公开(公告)号：US11276569B2

公开(公告)日：2022-03-15

申请号：US16515230

申请日：2019-07-18

Applicant: Applied Materials, Inc.

Inventor： Yongjing Lin ,  Tza-Jing Gung ,  Masaki Ogata ,  Yusheng Zhou ,  Xinhai Han ,  Deenesh Padhi ,  Juan Carlos Rocha ,  Amit Kumar Bansal ,  Mukund Srinivasan

IPC: H01L21/02

Abstract: Embodiments described herein relate to manufacturing layer stacks of oxide/nitride (ON) layers with minimized in-plane distortion (IPD) and lithographic overlay errors. A method of forming a layer stack ON layers includes flowing a first silicon-containing gas, an oxygen-containing gas, and a first dilution gas. A RF power is symmetrically applied to form a first material layer of SiO2. A second silicon-containing gas, a nitrogen-containing gas, and a second dilution gas are flowed. A second RF power is symmetrically applied to form a second material layer of Si3N4. The flowing the first silicon-containing gas, the oxygen-containing gas, and the first dilution gas, the symmetrically applying the first RF power, the flowing the second silicon-containing gas, the nitrogen-containing gas, and the second dilution gas, and the symmetrically applying the second RF power is repeated until a desired number of first material layers and second material layers make up a layer stack.

公开(公告)号：US11136665B2

公开(公告)日：2021-10-05

申请号：US16259011

申请日：2019-01-28

Applicant: Applied Materials, Inc.

Inventor： Dale Du Bois ,  Mohamad A. Ayoub ,  Robert Kim ,  Amit Kumar Bansal ,  Mark Fodor ,  Binh Nguyen ,  Siu F. Cheng ,  Hang Yu ,  Chiu Chan ,  Ganesh Balasubramanian ,  Deenesh Padhi ,  Juan Carlos Rocha

IPC: C23C16/04 ,  H01J37/32 ,  C23C14/04 ,  H01J37/34 ,  C30B25/12 ,  H01L21/687 ,  C23C16/44 ,  C23C16/455 ,  C23C16/458

Abstract: Embodiments of the invention contemplate a shadow ring that provides increased or decreased and more uniform deposition on the edge of a wafer. By removing material from the top and/or bottom surfaces of the shadow ring, increased edge deposition and bevel coverage can be realized. In one embodiment, the material on the bottom surface is reduced by providing a recessed slot on the bottom surface. By increasing the amount of material of the shadow ring, the edge deposition and bevel coverage is reduced. Another approach to adjusting the deposition at the edge of the wafer includes increasing or decreasing the inner diameter of the shadow ring. The material forming the shadow ring may also be varied to change the amount of deposition at the edge of the wafer.

公开(公告)号：US20210183678A1

公开(公告)日：2021-06-17

申请号：US16717245

申请日：2019-12-17

Applicant: Applied Materials, Inc.

Inventor： Madhu Santosh Kumar Mutyala ,  Sanjay Kamath ,  Deenesh Padhi

IPC: H01L21/683 ,  H01L21/67

Abstract: Exemplary semiconductor processing chambers may include a pedestal comprising a platen configured to support a semiconductor substrate across a surface of the platen. The chambers may include a first conductive mesh incorporated within the platen and configured to operate as a first chucking mesh. The first conductive mesh may extend radially across the platen. The chambers may include a second conductive mesh incorporated within the platen and configured to operate as a second chucking mesh. The second conductive mesh may be characterized by an annular shape. The second conductive mesh may be disposed between the first conductive mesh and the surface of the platen.

公开(公告)号：US20210047730A1

公开(公告)日：2021-02-18

申请号：US16986438

申请日：2020-08-06

Applicant: Applied Materials, Inc.

Inventor： Sai Susmita Addepalli ,  Yue Chen ,  Zhijun Jiang ,  Shailendra Srivastava ,  Nikhil Sudhindrarao Jorapur ,  Daemian Raj Benjamin Raj ,  Greg Chichkanoff ,  Qiang Ma ,  Abhigyan Keshri ,  Xinhai Han ,  Ganesh Balasubramanian ,  Deenesh Padhi

IPC: C23C16/458 ,  H01L21/02 ,  H01J37/32 ,  C23C16/455 ,  C23C16/52

Abstract: Exemplary semiconductor processing chambers may include a showerhead. The chambers may also include a substrate support characterized by a first surface facing the showerhead. The first surface may be configured to support a semiconductor substrate. The substrate support may define a recessed pocket centrally located within the first surface. The recessed pocket may be defined by an outer radial wall characterized by a height from the first surface within the recessed pocket that is greater than or about 150% of a thickness of the semiconductor substrate.

公开(公告)号：US20210035843A1

公开(公告)日：2021-02-04

申请号：US16936042

申请日：2020-07-22

Applicant: Applied Materials, Inc.

Inventor： Jian Li ,  Juan C. Rocha ,  Zheng J. Ye ,  Daemian Raj Benjamin Raj ,  Shailendra Srivastava ,  Xinhai Han ,  Deenesh Padhi ,  Kesong Hu ,  Chuan-Ying Wang

IPC: H01L21/683 ,  H02N13/00 ,  H01L21/50

Abstract: Exemplary support assemblies may include an electrostatic chuck body defining a substrate support surface. The assemblies may include a support stem coupled with the electrostatic chuck body. The assemblies may include a heater embedded within the electrostatic chuck body. The assemblies may also include an electrode embedded within the electrostatic chuck body between the heater and the substrate support surface. The substrate support assemblies may be characterized by a leakage current through the electrostatic chuck body of less than or about 4 mA at a temperature of greater than or about 500° C. and a voltage of greater than or about 600 V.

公开(公告)号：US10707122B2

公开(公告)日：2020-07-07

申请号：US16140342

申请日：2018-09-24

Applicant: APPLIED MATERIALS, INC.

Inventor： Sree Rangasai V. Kesapragada ,  Kevin Moraes ,  Srinivas Guggilla ,  He Ren ,  Mehul Naik ,  David Thompson ,  Weifeng Ye ,  Yana Cheng ,  Yong Cao ,  Xianmin Tang ,  Paul F. Ma ,  Deenesh Padhi

IPC: H01L21/768 ,  H01L21/32 ,  H01L21/02 ,  H01L21/3105

Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.