公开(公告)号：US20090035913A1

公开(公告)日：2009-02-05

申请号：US11832995

申请日：2007-08-02

Applicant: Lijie Bao ,  Zhigang Rick Li ,  Damien F. Reardon ,  James F. Ryley ,  Cengiz Ahmet Palanduz

Inventor： Lijie Bao ,  Zhigang Rick Li ,  Damien F. Reardon ,  James F. Ryley ,  Cengiz Ahmet Palanduz

IPC: H01L21/20

CPC classification number: H01G4/1227 ,  H01G4/12 ,  H01L21/31691 ,  H01L28/55 ,  H05K1/162 ,  H05K3/1291 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355 ,  H05K2203/1105 ,  H05K2203/1126

Abstract: Deposited thin-film dielectrics having columnar grains and high dielectric constants are formed on heat treated and polished metal foil. The sputtered dielectrics are annealed at low oxygen partial pressures.

Abstract translation: 在热处理和抛光的金属箔上形成具有柱状晶粒和高介电常数的沉积的薄膜电介质。 溅射电介质在低氧分压下进行退火。

公开(公告)号：US07485411B2

公开(公告)日：2009-02-03

申请号：US11700864

申请日：2007-02-01

Applicant: Hyung Mi Jung ,  Yul Kyo Chung ,  Hyung Dong Kang

Inventor： Hyung Mi Jung ,  Yul Kyo Chung ,  Hyung Dong Kang

IPC: G03C5/00

CPC classification number: H05K1/162 ,  H05K3/16 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09763

Abstract: In a method for manufacturing a printed circuit board with a thin film capacitor embedded therein, a conductive metal is sputtered via a first mask to form a lower electrode. A dielectric material is sputtered via a second mask to form a dielectric layer. The conductive metal is sputtered via a third mask to form an upper electrode. An insulating layer is stacked on a stack body with the upper electrode formed therein and via holes are perforated from a top surface of the insulating layer to a top surface of the lower electrode and from the top surface of the insulating layer to a top surface of the upper electrode formed on the substrate. Also, the stack body with the via holes formed therein is electrolytically and electrolessly plated.

Abstract translation: 在其中嵌入有薄膜电容器的印刷电路板的制造方法中，通过第一掩模溅射导电金属以形成下电极。 通过第二掩模溅射介电材料以形成电介质层。 通过第三掩模溅射导电金属以形成上电极。 绝缘层堆积在堆叠体上，上电极形成在其中，并且通孔从绝缘层的顶表面穿孔到下电极的顶表面，并从绝缘层的顶表面到 上电极形成在基板上。 此外，其中形成有通孔的堆叠体是电解和无电镀的。

公开(公告)号：US20090015364A1

公开(公告)日：2009-01-15

申请号：US12233553

申请日：2008-09-18

Applicant: Ronald W. Whittaker ,  Joe D. Guerra ,  Ciprian Marcoci

Inventor： Ronald W. Whittaker ,  Joe D. Guerra ,  Ciprian Marcoci

IPC: H01F27/28

CPC classification number: H01F17/0033 ,  H01F17/062 ,  H01F19/04 ,  H01F27/266 ,  H01F27/2804 ,  H01F41/046 ,  H01F2017/002 ,  H05K1/165 ,  H05K1/189 ,  H05K3/389 ,  H05K3/429 ,  H05K3/4644 ,  H05K2201/0179 ,  H05K2201/086 ,  H05K2201/097 ,  H05K2201/09809 ,  H05K2201/10416

Abstract: Miniature circuitry and inductor components in which multiple levels of printed circuitry are formed on each side of a support panel, typically a printed circuit board or rigid flex. Magnetic members are embedded in one or more cavities in said support panel. Electrical connection between the plural levels of circuitry and multiple windings around the magnetic members are provided by plural plated through hole conductors. Small through hole openings accommodate a plurality of the plated through hole conductors since each is insulated from the others by a very thin layer of vacuum deposited organic layer such as parylene having a high dielectric strength. Adhesion of this plated copper to the organic layer is provided by first applying an adhesive promotor to the surface of the organic layer followed by the vacuum deposition of the organic layer.

Abstract translation: 微型电路和电感器部件，其中在支撑面板的每一侧，通常是印刷电路板或刚性柔性件上形成多层印刷电路。 磁性构件嵌入在所述支撑面板中的一个或多个空腔中。 由多个电镀通孔导体提供多层电路与磁性构件周围的多个绕组之间的电连接。 小的通孔开口容纳多个电镀通孔导体，因为它们通过非常薄的真空沉积的有机层（例如具有高介电强度的聚对二甲苯）绝缘。 通过首先在有机层的表面上施加粘合剂促进剂，然后真空沉积有机层来提供该镀铜的有机层的附着力。

公开(公告)号：US07470865B2

公开(公告)日：2008-12-30

申请号：US11429103

申请日：2006-05-08

Applicant: Takashi Fushie ,  Takeshi Kagatsume ,  Shigekazu Matsui

Inventor： Takashi Fushie ,  Takeshi Kagatsume ,  Shigekazu Matsui

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H05K3/426 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K3/388 ,  H05K3/4602 ,  H05K3/4605 ,  H05K3/467 ,  H05K2201/0154 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/068 ,  H05K2201/09536 ,  H05K2201/0959 ,  Y10T29/49165 ,  Y10T428/24926 ,  H01L2924/00

Abstract: A multilayer printed wiring board which permits the formation of fine wiring patterns, thereby increasing the density of wiring patterns. Using photosensitive glass having a coefficient of thermal expansion close to that of a copper film as a core substrate, a through hole is formed in the photosensitive glass by photolithography, a sputtering silicon oxide layer and a sputtering silicon nitride layer are formed to prevent leak of alkali metal ions from the photosensitive glass, a sputtering chromium layer, a sputtering chromium-copper layer and a sputtering copper layer are formed to enhance the adhesion strength between the copper film and the sputtering silicon oxide layer, and a copper film of 1 to 20 μm thick is formed. With resin filled into the interior of the through hole, a wiring layer is patterned by etching, an insulating layer is formed, and the surface is covered with a surface treatment layer and a cover coat.

Abstract translation: 允许形成精细布线图案的多层印刷布线板，从而增加布线图案的密度。 使用具有与铜膜接近的热膨胀系数的感光性玻璃作为芯基板，通过光刻在感光性玻璃中形成通孔，形成溅射氧化硅层和溅射氮化硅层，以防止泄漏 形成来自感光玻璃的碱金属离子，溅射铬层，溅射铬 - 铜层和溅射铜层，以提高铜膜和溅射氧化硅层之间的粘合强度，并使铜膜为1〜20 形成了厚厚的妈妈。 当树脂填充到通孔的内部时，通过蚀刻对布线层进行图案化，形成绝缘层，并且表面被表面处理层和覆盖层覆盖。

公开(公告)号：US20080289178A1

公开(公告)日：2008-11-27

申请号：US11753996

申请日：2007-05-25

Applicant: Michael Nashner ,  Jeff Howerton

Inventor： Michael Nashner ,  Jeff Howerton

IPC: H05K5/02 ,  H01Q1/00

CPC classification number: H05K3/445 ,  H05K1/053 ,  H05K3/4061 ,  H05K5/0247 ,  H05K2201/0179 ,  H05K2201/09581 ,  H05K2201/09827 ,  H05K2203/0315 ,  H05K2203/0323 ,  H05K2203/107 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method of forming an isolated electrically conductive contact through a metal substrate by creating at least one via through the substrate. The at least one sidewall of the via is cleaned and coated with a non-conductive layer. In one example, the non-conductive layer is formed by anodizing the sidewall(s) of the via. In another example, the non-conductive layer may be formed by thin film deposition of a dielectric on the sidewall(s). An electrically conductive filler is then placed into the via. In the examples disclosed, the filler may be a conductive ink or a conductive epoxy.

Abstract translation: 通过形成至少一个通孔穿过衬底，通过金属衬底形成隔离的导电接触的方法。 通孔的至少一个侧壁被清洁并涂覆有非导电层。 在一个示例中，非导电层通过阳极氧化通孔的侧壁而形成。 在另一示例中，非导电层可以通过在侧壁上的电介质的薄膜沉积来形成。 然后将导电填料放入通孔中。 在所公开的实施例中，填料可以是导电油墨或导电环氧树脂。

公开(公告)号：US07446388B2

公开(公告)日：2008-11-04

申请号：US11284704

申请日：2005-11-21

Applicant: Michael D. Casper ,  William B. Mraz

Inventor： Michael D. Casper ,  William B. Mraz

IPC: H01L21/00

CPC classification number: H01L21/4846 ,  H01L23/15 ,  H01L23/49822 ,  H01L25/16 ,  H01L27/016 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/19011 ,  H01Q21/061 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K3/002 ,  H05K3/4644 ,  H05K3/467 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09763 ,  H01L2924/00

Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).

Abstract translation: 公开了用于在各种薄膜混合基板表面（0501）上制造高可靠性电容器（1011），电感器（1012）和多层互连（1013）（包括电阻器（1014））的系统和方法。 所公开的方法首先采用在衬底（0501）上沉积和图案化的薄金属层（0502）。 该薄图案层（0502）用于为上电极组件之间的电容器结构（0603）和互连（0604）提供两个下电极。 接下来，在薄的图案化层（0502）上沉积电介质层（0705），并且对电介质层（0705）进行图案化以将薄的图案化层的接触孔（0806）打开。 然后将上电极层（0907,0908,1009,1010）沉积并图案化在电介质（0705）的顶部。

公开(公告)号：US20080257487A1

公开(公告)日：2008-10-23

申请号：US12213321

申请日：2008-06-18

Applicant: Takeshi Shioga ,  Yoshikatsu Ishizuki ,  John David Baniecki ,  Kazuaki Kurihara

Inventor： Takeshi Shioga ,  Yoshikatsu Ishizuki ,  John David Baniecki ,  Kazuaki Kurihara

IPC: B32B38/10

CPC classification number: H01G4/30 ,  H01G4/232 ,  H01L21/6835 ,  H01L2221/68345 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H05K1/112 ,  H05K1/141 ,  H05K1/162 ,  H05K3/007 ,  H05K3/4602 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0191 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599

Abstract: An interposer 2 comprising a base 10 formed of a plurality of resin layers 26, 34, 42, 52, 56; a thin-film capacitor 12 buried in the base 10, including a lower electrode 20, a capacitor dielectric film 22 and an upper electrode 24; a first through-electrode 14b formed through the base 10 and electrically connected to the upper electrode 24 of the thin-film capacitor 12; and a second through-electrode 14a formed through the base 10 and electrically connected to the lower electrode 20 of the thin-film capacitor 12, further comprising: an interconnection 48 buried in the base 10 and electrically connected to the respective upper electrodes 24 of a plurality of the thin-film capacitors 12, a plurality of the first through-electrodes 14b being electrically connected to the upper electrodes 24 of said plurality of the thin-film capacitors 12 via the interconnection 48, and said plurality of the first through-electrodes 14b being electrically interconnected by the interconnections 48.

Abstract translation: 插入件2包括由多个树脂层26,34,42,52,56形成的基座10; 埋在基座10中的薄膜电容器12，包括下电极20，电容器电介质膜22和上电极24; 通过基底10形成并与薄膜电容器12的上部电极24电连接的第一贯通电极14b; 以及通过基底10形成并电连接到薄膜电容器12的下电极20的第二贯通电极14a，还包括：埋入基座10中并电连接到薄膜电容器12的各个上电极24的互连件48 多个薄膜电容器12，多个第一贯通电极14b经由互连件48与所述多个薄膜电容器12的上部电极24电连接，所述多个第一贯通电极 - 电极14b通过互连48电互连。

公开(公告)号：US07436282B2

公开(公告)日：2008-10-14

申请号：US11774180

申请日：2007-07-06

Applicant: Ronald W. Whittaker ,  Joe D. Guerra ,  Ciprian Marcoci

Inventor： Ronald W. Whittaker ,  Joe D. Guerra ,  Ciprian Marcoci

IPC: H01F5/00

CPC classification number: H01F17/0033 ,  H01F17/062 ,  H01F19/04 ,  H01F27/266 ,  H01F27/2804 ,  H01F41/046 ,  H01F2017/002 ,  H05K1/165 ,  H05K1/189 ,  H05K3/389 ,  H05K3/429 ,  H05K3/4644 ,  H05K2201/0179 ,  H05K2201/086 ,  H05K2201/097 ,  H05K2201/09809 ,  H05K2201/10416

Abstract: Miniature circuitry and inductor components in which multiple levels of printed circuitry are formed on each side of a support panel, typically a printed circuit board or rigid flex. Magnetic members are embedded in one or more cavities in said support panel. Electrical connection between the plural levels of circuitry and multiple windings around the magnetic members are provided by plural plated through hole conductors. Small through hole openings accommodate a plurality of the plated through hole conductors since each is insulated from the others by a very thin layer of vacuum deposited organic layer such as parylene having a high dielectric strength. Adhesion of this plated copper to the organic layer is provided by first applying an adhesive promotor to the surface of the organic layer followed by the vacuum deposition of the organic layer.

Abstract translation: 微型电路和电感器部件，其中在支撑面板的每一侧，通常是印刷电路板或刚性柔性件上形成多层印刷电路。 磁性构件嵌入在所述支撑面板中的一个或多个空腔中。 由多个电镀通孔导体提供多层电路与磁性构件周围的多个绕组之间的电连接。 小的通孔开口容纳多个电镀通孔导体，因为它们通过非常薄的真空沉积的有机层（例如具有高介电强度的聚对二甲苯）绝缘。 通过首先在有机层的表面上施加粘合剂促进剂，然后真空沉积有机层来提供该镀铜的有机层的附着力。

公开(公告)号：US07420130B2

公开(公告)日：2008-09-02

申请号：US11812124

申请日：2007-06-15

Applicant: Keishiro Okamoto ,  Tomoyuki Abe ,  Motoaki Tani ,  Nobuyuki Hayashi

Inventor： Keishiro Okamoto ,  Tomoyuki Abe ,  Motoaki Tani ,  Nobuyuki Hayashi

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H05K3/445 ,  H05K1/056 ,  H05K3/426 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2201/0323 ,  H05K2201/09581 ,  H05K2203/135 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: The wiring board comprises a plate-shaped conductive core material 10 with a through-hole 12 formed in, an insulation layer 14 formed on the surface of the conductive core material 10 and on the inside wall of the through-hole 12, a resin 18 buried in the through-hole 12 with the insulation layer 14 formed in, wirings 22a, 22b formed on the upper surface and the undersurface of the conductive core material 10 with the insulation layer 14 formed on, and an wiring 22d formed in the through-hole 20 formed in the resin 18 and electrically connected to the wirings 22a, 22b.

Abstract translation: 布线板包括具有形成在其中的通孔12的板状导电芯材10，形成在导电芯材10的表面上的绝缘层14和通孔12的内壁上的树脂18 埋置在通孔12中，其中形成有绝缘层14，形成在形成有绝缘层14的导电芯材10的上表面和下表面上的布线22a，22b以及形成在其中的布线22d 通孔20形成在树脂18中并电连接到布线22a，22b。

公开(公告)号：US20080185173A1

公开(公告)日：2008-08-07

申请号：US11848891

申请日：2007-08-31

Applicant: John M. Bedinger ,  Michael A. Moore

Inventor： John M. Bedinger ,  Michael A. Moore

IPC: H05K3/30 ,  H05K1/00 ,  H05K3/00

CPC classification number: H05K3/284 ,  H01L23/3192 ,  H01L23/4821 ,  H01L24/83 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2224/8592 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/0781 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/19041 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2203/1322 ,  Y10T29/49124 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49982 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/29075 ,  H01L2924/00014

Abstract: According to one embodiment of the disclosure, an environmental protection coating comprises a circuit assembly having a first protective dielectric layer and a second dielectric layer. The circuit assembly has an outer surface on which a plurality of discrete electrical components are attached. The first protective dielectric layer overlays the circuit assembly. The second dielectric layer overlays the first protective dielectric layer and is made of a dielectric material having modulus of elasticity less than 3.5 Giga-Pascal (GPa), dielectric constant less than 2.7, dielectric loss less than 0.008, breakdown voltage strength in excess of 2 million volts/centimeter (MV/cm), temperature stability to 3000 Celsius, defect densities less than 0.5/centimeter, pinhole free in films greater than 50 Angstroms, capable of being deposited conformally over and under 3D structures with thickness uniformity less than or equal to 10%.

Abstract translation: 根据本公开的一个实施例，环境保护涂层包括具有第一保护介电层和第二介电层的电路组件。 电路组件具有附接有多个分立电气部件的外表面。 第一保护介电层覆盖电路组件。 第二电介质层覆盖第一保护介电层，并由弹性模量小于3.5千兆帕（GPa），介电常数小于2.7，介电损耗小于0.008的电介质材料制成，击穿电压强度超过2 百万伏/厘米（MV /厘米），温度稳定至3000摄氏度，缺陷密度小于0.5厘米，薄膜中无针孔大于50埃，能够平滑地沉积在三维结构之下，厚度均匀度小于或等于 至10％。