公开(公告)号：US20170064822A1

公开(公告)日：2017-03-02

申请号：US15235363

申请日：2016-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doh Won JUNG ,  Yoon Chul SON ,  Woojin LEE ,  Jongmin LEE

IPC: H05K1/09 ,  H05K3/22

CPC classification number: H05K1/09 ,  H05K1/028 ,  H05K1/0393 ,  H05K3/22 ,  H05K3/24 ,  H05K2201/0326 ,  H05K2201/0338 ,  H05K2203/0108 ,  H05K2203/0257 ,  H05K2203/1105

Abstract: An electrical conductor includes a first conductive layer including a plurality of metal oxide nanosheets, wherein a metal oxide nanosheet of the plurality of metal oxide nanosheets includes a proton bonded to a the surface of the metal oxide nanosheet, wherein the metal oxide is represented by Chemical Formula 1: MO2   Chemical Formula 1 wherein M is Re, V, Os, Ru, Ta, Ir, Nb, W, Ga, Mo, In, Cr, Rh, or Mn, wherein the plurality of metal oxide nanosheets has a content of hydrogen atoms of less than about 100 atomic percent, with respect to 100 atomic percent of metal atoms as measured by Rutherford backscattering spectrometry, and wherein the plurality of metal oxide nanosheets includes an electrical connection between contacting metal oxide nanosheets.

Abstract translation: 其中M是Re，V，Os，Ru，Ta，Ir，Nb，W，Ga，Mo，In，Cr，Rh或Mn，其中多个金属氧化物纳米片的氢原子含量小于约100 原子百分比，相对于通过卢瑟福背散射光谱法测量的100原子％的金属原子，并且其中多个金属氧化物纳米片包括在接触金属氧化物纳米片之间的电连接。

公开(公告)号：US09565775B2

公开(公告)日：2017-02-07

申请号：US14469782

申请日：2014-08-27

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Noriyoshi Shimizu ,  Wataru Kaneda ,  Hiromu Arisaka ,  Akio Rokugawa

IPC: H05K1/11 ,  H05K3/42 ,  H05K1/00 ,  H05K1/18 ,  H05K7/10 ,  H05K3/38 ,  H05K3/46

CPC classification number: H05K3/421 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/115 ,  H05K1/116 ,  H05K3/38 ,  H05K3/4644 ,  H05K2201/0338 ,  H05K2201/0352 ,  H05K2201/09381 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/0979 ,  H05K2201/09827 ,  H05K2201/09854 ,  H05K2201/2072 ,  H05K2203/0789 ,  H01L2924/00

Abstract: A wiring board includes a first insulating layer coating a first wiring layer. A first through hole is opened in a surface of the first insulating layer and exposes a surface of the first wiring layer. A first via arranged in the first through hole includes an end surface exposed to the surface of the first insulating layer. A gap is formed between the first insulating layer and the first via in the first through hole. A second wiring layer is stacked on the surface of the first insulating layer and the end surface of the first via. The second wiring layer includes a pad filling the gap. The pad is greater in planar shape than the first through hole.

Abstract translation: 布线板包括涂覆第一布线层的第一绝缘层。 第一通孔在第一绝缘层的表面上开放，并露出第一布线层的表面。 布置在第一通孔中的第一通孔包括暴露于第一绝缘层的表面的端表面。 在第一通孔中的第一绝缘层和第一通孔之间形成间隙。 在第一绝缘层的表面和第一通孔的端面上堆叠第二布线层。 第二布线层包括填充间隙的垫。 该垫的平面形状大于第一通孔。

公开(公告)号：US20160249445A1

公开(公告)日：2016-08-25

申请号：US15050606

申请日：2016-02-23

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Tae-Hong MIN ,  Myung-Sam KANG ,  Jung-Han LEE ,  Young-Gwan KO

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0206 ,  H05K1/0203 ,  H05K1/0204 ,  H05K1/0207 ,  H05K1/0218 ,  H05K1/111 ,  H05K1/181 ,  H05K1/183 ,  H05K3/4608 ,  H05K2201/0323 ,  H05K2201/0338 ,  H05K2201/066 ,  H05K2201/10416

Abstract: A circuit board is disclosed. In addition to insulating layers, the circuit board includes a structure for heat transfer that includes a first layer that is formed of graphite or graphene, a second layer that is formed of metallic material and disposed on one surface of the first layer, and a third layer that is formed of metallic material and disposed on the other surface of the first layer, and at least a portion of the structure for heat transfer is inserted into an insulation layer. Such a circuit board provides improved heat management. Also disclosed is a method of manufacturing the circuit board.

Abstract translation: 公开了一种电路板。 除了绝缘层之外，电路板还包括用于传热的结构，其包括由石墨或石墨烯形成的第一层，由金属材料形成并设置在第一层的一个表面上的第二层，以及第三层 层，其由金属材料形成并且设置在第一层的另一表面上，并且用于传热的结构的至少一部分插入绝缘层中。 这种电路板提供改进的热管理。 还公开了一种制造电路板的方法。

公开(公告)号：US20160242285A1

公开(公告)日：2016-08-18

申请号：US15044380

申请日：2016-02-16

Applicant: IBIDEN CO., LTD.

Inventor： Takayuki Katsuno ,  Yuki Ito ,  Takeshi Furusawa ,  Takema Adachi

IPC: H05K1/11 ,  H05K1/09

CPC classification number: H05K1/0271 ,  H05K3/007 ,  H05K3/025 ,  H05K3/188 ,  H05K3/244 ,  H05K2201/0338 ,  H05K2201/0344 ,  H05K2201/098 ,  H05K2203/1184

Abstract: A printed wiring board includes a resin insulating layer having recess portions formed on first surface, a first conductor layer formed in the recess portions and including pads positioned to mount an electronic component, conductive pillars formed on the pads, respectively, and formed to mount the electronic component onto the resin insulating layer, a second conductor layer formed on second surface of the resin insulating layer on the opposite side with respect to the first surface, and a via conductor formed in the resin insulating layer such that the via conductor is penetrating through the resin insulating layer and connecting the first and second conductor layers. The pillars is formed such that each of the pads has an exposed surface exposed from a respective one of the conductive pillars, and the pads are formed such that the exposed surface is recessed from the first surface of the resin insulating layer.

Abstract translation: 印刷电路板包括具有形成在第一表面上的凹部的树脂绝缘层，形成在凹部中的第一导体层，并且包括分别安装电子部件的焊盘，形成在焊盘上的导电柱，并形成为安装 电子部件到树脂绝缘层上，在相对于第一表面的相对侧的树脂绝缘层的第二表面上形成的第二导体层和形成在树脂绝缘层中的通孔导体，使得通孔导体穿透 树脂绝缘层并连接第一和第二导体层。 柱形成为使得每个焊盘具有从相应的一个导电柱露出的暴露表面，并且焊盘被形成为使得暴露的表面从树脂绝缘层的第一表面凹陷。

公开(公告)号：US20160190076A1

公开(公告)日：2016-06-30

申请号：US14980404

申请日：2015-12-28

Applicant: ROHM CO., LTD.

Inventor： Takuma SHIMOICHI ,  Yasuhiro KONDO

IPC: H01L23/66 ,  H01L49/02

CPC classification number: H01L23/66 ,  H01L27/016 ,  H01L28/10 ,  H01L28/20 ,  H01L28/60 ,  H01L2223/6672 ,  H01L2924/0002 ,  H05K1/0289 ,  H05K1/029 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/107 ,  H05K3/146 ,  H05K2201/0317 ,  H05K2201/0338 ,  H05K2201/0376 ,  H05K2201/0391 ,  H05K2201/09263 ,  H05K2201/09981 ,  H05K2201/10181 ,  H05K2203/0353 ,  H05K2203/1338 ,  H01L2924/00

Abstract: A chip part includes a substrate, a first electrode and a second electrode which are formed apart from each other on the substrate and a circuit network which is formed between the first electrode and the second electrode. The circuit network includes a first passive element including a first conductive member embedded in a first trench formed in the substrate and a second passive element including a second conductive member formed on the substrate outside the first trench.

Abstract translation: 芯片部分包括在基板上彼此分开形成的基板，第一电极和第二电极以及形成在第一电极和第二电极之间的电路网络。 电路网络包括第一无源元件，第一无源元件包括嵌入在衬底中形成的第一沟槽中的第一导电构件和第二无源元件，第二无源元件包括形成在第一沟槽外部的衬底上的第二导电构件。

公开(公告)号：US20160174386A1

公开(公告)日：2016-06-16

申请号：US14907590

申请日：2014-07-22

Applicant: FERRO CORPORATION

Inventor： George E. Sakoske ,  Phil Maitland ,  Dietrich Speer ,  Frank Walter ,  Robert P. Blonski ,  Srinivasan Sridharan

IPC: H05K3/12 ,  H05K1/11 ,  H05K1/02 ,  H05K1/03

CPC classification number: H05K3/1291 ,  H05K1/0296 ,  H05K1/0306 ,  H05K1/092 ,  H05K1/115 ,  H05K3/282 ,  H05K3/388 ,  H05K3/389 ,  H05K2201/0338 ,  H05K2203/1126

Abstract: The present subject matter provides for a multi-layer conductive trace. The trace can be formed by digital printing the individual layers and firing. The individual layers each impart functional characteristics to the conductive trace and each layer has components that can be adjusted to affect the performance characteristics of that particular layer without detrimentally affecting the performance characteristics of the remaining layers.

Abstract translation: 本主题提供多层导电迹线。 痕迹可以通过数字印刷单独的层和烧制形成。 各个层各自赋予导电迹线功能特征，并且每个层具有可被调整以影响该特定层的性能特征的组分，而不会有害地影响剩余层的性能特征。

公开(公告)号：US20160047767A1

公开(公告)日：2016-02-18

申请号：US14460598

申请日：2014-08-15

Applicant: John Andrew Lebens ,  Ronald Steven Cok ,  Yongcal Wang

Inventor： John Andrew Lebens ,  Ronald Steven Cok ,  Yongcal Wang

IPC: G01N27/12

CPC classification number: G01N27/126 ,  G01N27/07 ,  G02F1/13439 ,  G06F3/044 ,  G06F2203/04103 ,  H05K3/0014 ,  H05K3/1258 ,  H05K2201/0108 ,  H05K2201/0112 ,  H05K2201/0257 ,  H05K2201/0269 ,  H05K2201/0272 ,  H05K2201/0338 ,  H05K2201/0376 ,  H05K2201/2054 ,  H05K2203/0108 ,  H05K2203/1131 ,  H05K2203/1476

Abstract: A method of operating an imprinted electronic sensor to sense an environmental factor includes providing spatially separated micro-channels in a cured layer on a substrate. A multi-layer micro-wire is formed in each micro-channel. Each multi-layer micro-wire includes at least a conductive layer and a reactive layer exposed to the environmental factor. The conductive layer is a cured electrical conductor located only within the micro-channel and at least a portion of the reactive layer responds to the environmental factor. A controller is provided for electrically controlling first and second groups of multi-layer micro-wires, each first and second group including one or more multi-layer micro-wires. The reactive layer is exposed to the environment. The controller measures the electrical response of the first and second groups of multi-layer micro-wires. The electrical response includes at least one of the amperometric response, the resistance, the capacitance, the impedance, the complex impedance, or the inductance.

Abstract translation: 操作印刷电子传感器以感测环境因素的方法包括在基板上的固化层中提供空间分离的微通道。 在每个微通道中形成多层微线。 每个多层微线包括至少暴露于环境因素的导电层和反应层。 导电层是仅位于微通道内的固化电导体，并且反应层的至少一部分响应于环境因素。 提供一种用于电控制第一组和第二组多层微线的控制器，每个第一组和第二组包括一个或多个多层微线。 反应层暴露于环境中。 控制器测量第一组和第二组多层微线的电响应。 电响应包括电流响应，电阻，电容，阻抗，复阻抗或电感中的至少一个。

公开(公告)号：US09232646B2

公开(公告)日：2016-01-05

申请号：US14102832

申请日：2013-12-11

Applicant: International Business Machines Corporation

Inventor： Jinwoo Choi ,  Daniel M. Dreps ,  Rohan U. Mandrekar

IPC: H01L23/528 ,  H05K1/02 ,  C04B37/00 ,  H05K1/03 ,  H05K3/46 ,  H01L21/48 ,  H05K3/12 ,  H01L23/522 ,  H05K1/09 ,  H01L23/13 ,  H01L23/498 ,  H05K3/00 ,  H05K3/24

CPC classification number: H05K1/0298 ,  B32B18/00 ,  C04B37/006 ,  C04B2237/34 ,  C04B2237/343 ,  C04B2237/366 ,  C04B2237/68 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4867 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L2924/0002 ,  H05K1/0245 ,  H05K1/0306 ,  H05K1/092 ,  H05K3/005 ,  H05K3/1216 ,  H05K3/1233 ,  H05K3/1291 ,  H05K3/245 ,  H05K3/4667 ,  H05K2201/0338 ,  H05K2201/035 ,  H05K2201/09272 ,  H05K2201/09709 ,  H05K2203/0126 ,  H05K2203/063 ,  Y10T156/10 ,  H01L2924/00

Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating differential wiring patterns in multilayer glass-ceramic (MLC) modules. A structure and method of forming a MLC having layers with staggered, or offset, pairs of lines formed directly on one another are disclosed. In addition, a structure and method of forming a MLC having layers with staggered, or offset, pairs of lines that periodically reverse polarity are disclosed.

公开(公告)号：US09232645B2

公开(公告)日：2016-01-05

申请号：US14087341

申请日：2013-11-22

Applicant: International Business Machines Corporation

Inventor： Jinwoo Choi ,  Daniel M. Dreps ,  Rohan U. Mandrekar

IPC: H01L23/528 ,  H05K1/02 ,  C04B37/00 ,  H05K1/03 ,  H05K3/46 ,  H01L21/48 ,  H05K3/12 ,  H01L23/522 ,  H05K1/09 ,  H01L23/13 ,  H01L23/498 ,  H05K3/00 ,  H05K3/24

CPC classification number: H05K1/0298 ,  B32B18/00 ,  C04B37/006 ,  C04B2237/34 ,  C04B2237/343 ,  C04B2237/366 ,  C04B2237/68 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4867 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L2924/0002 ,  H05K1/0245 ,  H05K1/0306 ,  H05K1/092 ,  H05K3/005 ,  H05K3/1216 ,  H05K3/1233 ,  H05K3/1291 ,  H05K3/245 ,  H05K3/4667 ,  H05K2201/0338 ,  H05K2201/035 ,  H05K2201/09272 ,  H05K2201/09709 ,  H05K2203/0126 ,  H05K2203/063 ,  Y10T156/10 ,  H01L2924/00

Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating differential wiring patterns in multilayer glass-ceramic (MLC) modules. A structure and method of forming a MLC having layers with staggered, or offset, pairs of lines formed directly on one another are disclosed. In addition, a structure and method of forming a MLC having layers with staggered, or offset, pairs of lines that periodically reverse polarity are disclosed.

Abstract translation: 本发明的实施例一般涉及集成电路的制造，更具体地涉及用于在多层玻璃 - 陶瓷（MLC）模块中制造差分布线图案的结构和方法。 公开了一种形成具有彼此直接形成的交错或偏移成对的层的MLC的结构和方法。 另外，公开了一种形成具有周期性反转极性的具有交错或偏移的线对的层的MLC的结构和方法。

公开(公告)号：US20150380273A1

公开(公告)日：2015-12-31

申请号：US14763891

申请日：2014-04-09

Applicant: MITSUBISHI GAS CHEMICAL COMPANY, INC.

Inventor： Satoshi TAMAI ,  Kunio YUBE

IPC: H01L21/4763 ,  H01L27/12 ,  C23F1/18

CPC classification number: H01L21/47635 ,  C09K13/00 ,  C23F1/02 ,  C23F1/18 ,  C23F1/26 ,  C23F1/44 ,  H01L21/32134 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/7869 ,  H05K3/067 ,  H05K2201/0338

Abstract: The present invention provides a liquid composition used for etching a multilayer film containing copper and molybdenum, an etching method for etching a multilayer film containing copper and molybdenum, and a substrate. The present invention further provides a liquid composition for etching a multilayer-film wiring substrate which has an oxide layer (IGZO) including indium, gallium and zinc laminated on the substrate, and further a multilayer film including at least a layer containing molybdenum and a layer containing copper provided thereon, a method for etching a multilayer film containing copper and molybdenum from the substrate, and a substrate. According to the present invention, a liquid composition comprising (A) a maleic acid ion source, (B) a copper ion source, and (C) at least one type of amine compound selected from the group consisting of 1-amino-2-propanol, 2-(methylamino)ethanol, 2-(ethylamino)ethanol, 2-(butylamino)ethanol, 2-(dimethylamino)ethanol, 2-(diethylamino)ethanol, 2-methoxyethylamine, 3-methoxypropylamine, 3-amino-1-propanol, 2-amino-2-methyl-1-propanol, 1-dimethylamino-2-propanol, 2-(2-aminoethoxyl)ethanol, morpholine and 4-(2-hydroxyethyl)morpholine and having a pH value of 4-9 is used.

Abstract translation: 本发明提供用于蚀刻含有铜和钼的多层膜的液体组合物，蚀刻含有铜和钼的多层膜的蚀刻方法以及基板。 本发明还提供了一种用于蚀刻多层膜布线基板的液体组合物，该多层膜布线基板具有层叠在基板上的包含铟，镓和锌的氧化物层（IGZO），还包括至少包含含钼层和层 含有铜的铜，从基板上蚀刻含有铜和钼的多层膜的方法以及基板。 根据本发明，一种液体组合物，其包含（A）马来酸离子源，（B）铜离子源和（C）至少一种选自以下的胺化合物：1-氨基-2- 丙醇，2-（甲基氨基）乙醇，2-（乙基氨基）乙醇，2-（丁基氨基）乙醇，2-（二甲基氨基）乙醇，2-（二乙基氨基）乙醇，2-甲氧基乙胺，3-甲氧基丙胺，3-氨基-1 丙醇，2-氨基-2-甲基-1-丙醇，1-二甲基氨基-2-丙醇，2-（2-氨基乙氧基）乙醇，吗啉和4-（2-羟乙基）吗啉，pH值为4- 使用9。