公开(公告)号：US20050247481A1

公开(公告)日：2005-11-10

申请号：US10935870

申请日：2004-09-07

Applicant: Chien-Te Chen ,  Chih-Hao Chang

Inventor： Chien-Te Chen ,  Chih-Hao Chang

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/24 ,  H05K3/40 ,  H05K3/46 ,  H05K10/00

CPC classification number: H05K1/0269 ,  H05K3/0052 ,  H05K3/242 ,  H05K3/403 ,  H05K3/4602 ,  H05K2201/0919 ,  H05K2201/09781 ,  H05K2203/163 ,  H05K2203/175 ,  Y10T29/49128

Abstract: A circuit board with a quality-indicator mark and a method for indicating quality of the circuit board. The circuit board includes a plurality of circuit board units. A plating bus is formed around each circuit board unit and extended to form a plating trace in an inner-layer circuit structure of each circuit board unit. The inner-layer circuit structure is inspected in quality to maintain or break connection between the plating trace and plating bus if the quality is good or not. At least one circuit structure is formed on the inner-layer circuit structure and electrically connected to the plating trace to form a conductive mark on each circuit board unit. A metal protection layer is formed on the at least one circuit structure via the plating bus, and the conductive mark with the metal protection layer indicates that the inner-layer circuit structure of the circuit board unit is good.

Abstract translation: 具有质量指示标记的电路板和用于指示电路板的质量的方法。 电路板包括多个电路板单元。 在每个电路板单元周围形成电镀母线，并延伸以在每个电路板单元的内层电路结构中形成电镀痕迹。 如果质量好，内层电路结构的质量将被检查以维持或断开电镀痕迹和电镀母线之间的连接。 在内层电路结构上形成至少一个电路结构，并电连接到电镀迹线，以在每个电路板单元上形成导电标记。 金属保护层通过电镀母线形成在至少一个电路结构上，金属保护层的导电标记表示电路板单元的内层电路结构良好。

公开(公告)号：US06963209B1

公开(公告)日：2005-11-08

申请号：US10897638

申请日：2004-07-23

Applicant: Mark W. Gailus ,  Marc B. Cartier, Jr.

Inventor： Mark W. Gailus ,  Marc B. Cartier, Jr.

IPC: G01R31/02 ,  G01R35/00 ,  H05K1/00 ,  H05K1/02 ,  H05K3/40 ,  H05K3/42

CPC classification number: G01R35/007 ,  H05K1/0268 ,  H05K1/0298 ,  H05K3/403 ,  H05K3/429 ,  H05K2201/0919 ,  H05K2201/092 ,  H05K2201/09981

Abstract: Calibration standards for accurate high frequency or wide bandwidth calibration measurements. A “short” or “reflect” standard is formed in a printed circuit board from a conductive coating on a generally planar surface. The conductive coating connects a signal trace to one or more ground planes. The generally planar surface is at least as wide as the signal trace and is preferably several times wider than the signal trace to provide a short standard with properties uniform over a wide frequency range. The short standard is incorporated into a printed circuit upon which a device under test is to be mounted. Connections to the short standard are made through components equivalent to components used to connect a device under test. When a through and line standard are added to the same board, the test board contains all the standards needed for a TRL calibration.

Abstract translation: 精确的高频或宽带宽校准测量的校准标准。 在大体上平坦的表面上由导电涂层形成印刷电路板中的“短”或“反射”标准。 导电涂层将信号迹线连接到一个或多个接地层。 通常平面的表面至少与信号迹线一样宽，并且优选地比信号迹线宽数倍，以提供具有在宽频率范围内均匀的特性的短标准。 短标准被并入印刷电路中，在该印刷电路中将安装被测器件。 与短标准的连接通过与用于连接被测设备的组件相当的组件进行。 当通过和线路标准被添加到同一个板上时，测试板包含TRL校准所需的所有标准。

公开(公告)号：US06951778B2

公开(公告)日：2005-10-04

申请号：US10284825

申请日：2002-10-31

Applicant: Mohammad Akhavain ,  Stanley G. Markwell ,  Janis Horvath ,  Joseph E. Scheffelin

Inventor： Mohammad Akhavain ,  Stanley G. Markwell ,  Janis Horvath ,  Joseph E. Scheffelin

IPC: B41J2/01 ,  B41J2/16 ,  H05K1/00 ,  H05K1/03 ,  H05K3/24 ,  H05K3/28 ,  H01L21/48

CPC classification number: H05K3/28 ,  B41J2/16 ,  B41J2/1623 ,  H01L2224/48091 ,  H01L2224/48227 ,  H05K1/0298 ,  H05K1/0306 ,  H05K3/242 ,  H05K2201/0919 ,  H05K2203/1147 ,  H01L2924/00014

Abstract: Methods and systems of protecting substrates that are intended for use in fluidic devices are described. In accordance with one embodiment, sealant material is applied over one or more edges of at least one multi-chip module substrate that is intended for use in a fluidic device. At least one edge has an exposed electrical interconnect and the sealant material is applied over less than an entirety of the substrate and sufficiently to cover the exposed electrical interconnect. The sealant material is exposed to conditions effective to seal the one or more edges.

Abstract translation: 描述了保护用于流体装置的基板的方法和系统。 根据一个实施例，将密封剂材料施加到旨在用于流体装置的至少一个多芯片模块基板的一个或多个边缘上。 至少一个边缘具有暴露的电互连，并且将密封剂材料施加在小于整个基底上并充分覆盖暴露的电互连。 密封剂材料暴露于有效地密封一个或多个边缘的条件。

公开(公告)号：US20050168917A1

公开(公告)日：2005-08-04

申请号：US11095588

申请日：2005-04-01

Applicant: Seok Jun ,  Myoung Moon ,  Duk Lee

Inventor： Seok Jun ,  Myoung Moon ,  Duk Lee

IPC: H05K1/11 ,  H01L23/498 ,  H05K1/03 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  H01G4/06

CPC classification number: H05K3/403 ,  H01L23/49805 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/16195 ,  H05K1/0306 ,  H05K3/0052 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/09181 ,  H05K2201/0919 ,  H05K2201/09454 ,  H05K2203/1476 ,  H01L2924/00

Abstract: The A ceramic multilayer substrate includes a plurality of ceramic substrates being stacked vertically, each substrate having a designated thickness; pattern layers formed on surfaces of the ceramic substrates so as to form circuit elements; external terminals vertically formed on side surfaces of the stacked ceramic substrates; and internal connection parts, each of which is formed on a part of one of the pattern layers, is connected to one of the external terminal terminals so as to exchange signals with the outside, and be is broad enough to surround at least partially the connected external terminal.

Abstract translation: A陶瓷多层基板包括垂直堆叠的多个陶瓷基板，每个基板具有指定的厚度; 形成在陶瓷基板的表面上的图案层，以形成电路元件; 垂直形成在堆叠的陶瓷基板的侧表面上的外部端子; 并且每个形成在一个图案层的一部分上的内部连接部分连接到外部端子之一，以便与外部交换信号，并且足够宽以至少部分地包围连接的 外部终端。

公开(公告)号：US20040194999A1

公开(公告)日：2004-10-07

申请号：US10816485

申请日：2004-04-01

Applicant: Matsushita Electric Industrial Co., Ltd.

Inventor： Yoshihiro Tomita ,  Tadashi Nakamura ,  Yukihiro Ishimaru ,  Yasuhiro Sugaya ,  Kazuyoshi Honda ,  Sadayuki Okazaki

IPC: H05K001/11 ,  H05K007/06

CPC classification number: H05K3/4007 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/117 ,  H05K3/243 ,  H05K3/28 ,  H05K3/4069 ,  H05K3/467 ,  H05K2201/0367 ,  H05K2201/0919 ,  H05K2201/09436 ,  H05K2201/09709 ,  H05K2201/09736 ,  H05K2201/09845 ,  H05K2203/0733 ,  H01L2224/0401

Abstract: A wiring board that allows the high-density connection with a plurality of circuit boards within a limited area, a manufacturing method for the same and electronic equipment using the same are provided. A wiring board includes: a plurality of conductive layers each including one or more wirings for transmitting signals; and a plurality of insulation layers for insulating the respective conductive layers. The conductive layers and the insulation layers are laminated alternately, and each of the plurality of conductive layers is provided with a terminal at at least one of both ends. The terminals are formed stepwise and separated by the insulation layers in a cross-sectional shape of a lamination structure of the conductive layers and the insulation layers.

Abstract translation: 提供了允许在有限区域内与多个电路板进行高密度连接的布线板，其制造方法以及使用该布线板的电子设备。 布线板包括：多个导电层，每个导电层包括用于传输信号的一个或多个布线; 以及用于绝缘各导电层的多个绝缘层。 导电层和绝缘层交替层叠，并且多个导电层中的每一个在两端中的至少一个处设置有端子。 端子形成为阶梯状，并以导电层和绝缘层的叠层结构的横截面形状由绝缘层隔开。

公开(公告)号：US20040134685A1

公开(公告)日：2004-07-15

申请号：US10744142

申请日：2003-12-22

Applicant: International Business Machines Corporation

Inventor： Kenneth Fallon ,  Miguel A. Jimarez ,  Ross W. Keesler ,  John M. Lauffer ,  Roy H. Magnuson ,  Voya R. Markovich ,  Irv Memis ,  Jim P. Paoletti ,  Marybeth Perrino ,  John A. Welsh ,  William E. Wilson

IPC: G03G009/00 ,  H05K001/11 ,  H01R012/04

CPC classification number: H05K3/445 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/056 ,  H05K1/113 ,  H05K3/0023 ,  H05K3/0052 ,  H05K3/0094 ,  H05K3/06 ,  H05K3/108 ,  H05K3/426 ,  H05K3/429 ,  H05K3/44 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0919 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/096 ,  H05K2201/10734 ,  H05K2203/0323 ,  H05K2203/0574 ,  H05K2203/0733 ,  H05K2203/1394 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method of forming a printed circuit board with a metal power plane layer between two photoimageable dielectric layers is provided. Photoformed metal filled vias and plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials connected to the vias and plated through holes. A border may be around the board including a metal layer terminating in from the edge of one of the dielectric layers. Copper foil with clearance holes is provided. First and second layers of photoimageable curable dielectric material are on opposite sides of the copper. Patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. Through holes are developed where holes were patterned in both dielectric layers. The surfaces of the photoimageable material, vias and through holes are metallized by copper plating, preferably using photoresist.

Abstract translation: 提供了一种在两个可光成像的电介质层之间形成具有金属功率平面层的印刷电路板的方法。 光刻图形的金属填充通孔和电镀通孔位于光图案化材料中，信号电路位于连接到通孔和电镀通孔的每个介电材料的表面上。 边界可以在板的周围，包括从一个电介质层的边缘终止的金属层。 提供带有间隙孔的铜箔。 第一层和第二层可光成像的可固化电介质材料位于铜的相对两侧。 在可光成像材料的第一层和第二层上形成图案以通过通孔显露金属层。 开发了通孔，在两个电介质层中对其进行图案化。 可光成像材料，通孔和通孔的表面通过镀铜进行金属化，优选使用光致抗蚀剂。

公开(公告)号：US20040104044A1

公开(公告)日：2004-06-03

申请号：US10604744

申请日：2003-08-14

Inventor： SUNG-MAO WU

IPC: H05K007/06

CPC classification number: H01L23/49805 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/3011 ,  H05K1/0298 ,  H05K1/183 ,  H05K3/403 ,  H05K2201/0919 ,  H05K2201/09645 ,  H05K2201/09827 ,  H01L2924/00014

Abstract: A printed circuit board comprises a plurality of patterned circuit layers, a plurality of insulation layers and a plurality of circuits. Each insulation layer is located between a pair of neighboring patterned circuit layers for isolating the patterned circuit layers. The insulation layer and the patterned circuit layers together form a laminated layer. The circuits are formed on the sidewalls of the printed circuit board or the interior sidewalls of a cavity or an opening within the printed circuit board for interconnecting various patterned circuit layers electrically.

Abstract translation: 印刷电路板包括多个图案化电路层，多个绝缘层和多个电路。 每个绝缘层位于一对相邻的图案化电路层之间，用于隔离图案化的电路层。 绝缘层和图案化的电路层一起形成层压层。 电路形成在印刷电路板的侧壁或印刷电路板内的空腔或开口的内侧壁上，用于电连接各种图案化的电路层。

公开(公告)号：US06680218B2

公开(公告)日：2004-01-20

申请号：US10371659

申请日：2003-02-21

Applicant: Chee-Yee Chung ,  David G. Figueroa ,  Robert L. Sankman

Inventor： Chee-Yee Chung ,  David G. Figueroa ,  Robert L. Sankman

IPC: H01L2144

CPC classification number: H05K1/141 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/0231 ,  H05K1/0298 ,  H05K3/3436 ,  H05K3/366 ,  H05K2201/0919 ,  H05K2201/10446 ,  H05K2201/10454 ,  H05K2201/10674 ,  H05K2201/10719 ,  H01L2224/05599

Abstract: An electronic circuit package includes a vertical package section (304, FIG. 3) electrically connected to a horizontal package section (306, FIG. 3). The vertical package section includes multiple conductive layers (512, 514, 516, FIG. 5) oriented in parallel with a vertical plane. A first set of bond pads (606, FIG. 6) on the vertical section's horizontal top surface (608, FIG. 6) can be connected to the bond pads (602, FIG. 6) of an integrated circuit (302, FIG. 3). A second set of bond pads (612, FIG. 6) on the vertical section's horizontal bottom surface (614, FIG. 6) can be connected to bond pads (616, FIG. 6) on the horizontal package section. The conductive layers of the vertical section perform a bond pad pitch conversion in a first direction, and conductive structures (906, 908, 910, FIG. 9) within the horizontal package section perform a bond pad pitch conversion in a second direction.

Abstract translation: 电子电路封装包括电连接到水平封装部分（图3的306）的垂直封装部分（304，图3）。 垂直封装部分包括与垂直平面平行取向的多个导电层（512,514,516，图5）。 垂直部分的水平顶面（图6中的608）上的第一组接合焊盘（606，图6）可以连接到集成电路（图6的302）的接合焊盘（602，图6）。 3）。 垂直部分的水平底面（图6中的614）上的第二组接合焊盘（612，图6））可以连接到水平封装部分上的接合焊盘（616，图6）。 垂直部分的导电层在第一方向上进行接合焊盘间距转换，并且水平封装部分内的导电结构（906,908,910，图9）在第二方向上执行接合焊盘间距转换。

公开(公告)号：US20030131472A1

公开(公告)日：2003-07-17

申请号：US10050621

申请日：2002-01-15

Applicant: Mitac international Corp.

Inventor： Yu-Chiang Cheng ,  Jong-Kuei Chen

IPC: H05K003/36 ,  H05K003/34

CPC classification number: H05K3/403 ,  H05K3/3405 ,  H05K3/368 ,  H05K3/4614 ,  H05K2201/09181 ,  H05K2201/0919 ,  H05K2201/096 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49144

Abstract: In a method of fabricating a multi-layer circuit board assembly, at least two multi-layer circuit board modules are provided. Each of the modules has a lateral edge provided with a plurality of solder pads that are connected electrically with module interconnect circuit traces on a respective one of the modules. The modules are stacked one upon the other, and are bonded together such that the solder pads of one of the modules are connected to registered ones of the solder pads of the other one of the modules, thereby establishing electrical connection among the circuit traces on the modules.

Abstract translation: 在制造多层电路板组件的方法中，提供至少两个多层电路板模块。 每个模块具有设置有多个焊盘的横向边缘，该多个焊盘在相应的一个模块上与模块互连电路迹线电连接。 这些模块一个接一个堆叠，并且结合在一起，使得其中一个模块的焊盘连接到另一个模块的注册的焊盘，从而在模块的电路迹线之间建立电连接 模块。

公开(公告)号：US20030081387A1

公开(公告)日：2003-05-01

申请号：US10044055

申请日：2001-11-01

Inventor： Jurgen Schulz

IPC: H05K007/00

CPC classification number: H05K1/117 ,  H05K3/4611 ,  H05K2201/09163 ,  H05K2201/0919

Abstract: A module and a corresponding connector that include multiple rows of contacts is described. In one embodiment, the module may include a channel formed in a bottom edge of the module. A plurality of contacts may be disposed on the inner surface of the channel and the outer surface of the module. A complementary connector is also described.

Abstract translation: 描述了包括多行触点的模块和对应的连接器。 在一个实施例中，模块可以包括形成在模块的底部边缘中的通道。 多个触点可以设置在通道的内表面和模块的外表面上。 还描述了互补连接器。