公开(公告)号：US5272600A

公开(公告)日：1993-12-21

申请号：US939228

申请日：1992-09-02

Applicant: David H. Carey

Inventor： David H. Carey

IPC: H01L23/538 ,  H01L23/64 ,  H05K1/00 ,  H05K1/11 ,  H05K1/16 ,  H05K1/14

CPC classification number: H05K1/162 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/64 ,  H01L23/642 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0289 ,  H05K1/115 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/09345

Abstract: The invention relates to an electrical interconnect device with power and ground lines interwoven about signal line layers and capacitive vias between signal layers so as to make efficient use of otherwise undedicated area between signal lines and signal layers and to reduce or eliminate the need for separate power and ground layers while providing decoupling capacitance within the wiring structure.

Abstract translation: 本发明涉及一种具有电源和地线的电互连装置，其中信号线层和信号层之间的电容通孔交织在一起，以便有效地利用信号线和信号层之间的未被接合的区域，并减少或消除对分离电力的需要 和接地层，同时在布线结构内提供去耦电容。

公开(公告)号：US09236189B2

公开(公告)日：2016-01-12

申请号：US14014773

申请日：2013-08-30

Applicant: SAMHWA CAPACITOR CO., LTD.

Inventor： Young Joo Oh ,  Jung Rag Yoon ,  Kyung Min Lee ,  Young Min Yoo

IPC: H01G4/38 ,  H01G4/40 ,  H01G2/06 ,  H05K1/02 ,  H05K1/11 ,  H05K3/30 ,  H05K3/46

CPC classification number: H01G4/38 ,  H01G2/06 ,  H01G4/40 ,  H05K1/0231 ,  H05K1/116 ,  H05K3/306 ,  H05K3/4641 ,  H05K2201/09309 ,  H05K2201/09345 ,  H05K2201/09718 ,  H05K2201/1034 ,  Y02T10/7022

Abstract: A direct current (DC) link capacitor module includes a printed circuit board (PCB) formed by sequentially disposing a first electrode substrate, an insulation substrate, a second electrode substrate, a third electrode substrate; a plurality of DC link capacitors connected in parallel to each of the first electrode substrate and the second electrode substrate; a plurality of first Y-capacitors connected in series to each of the first electrode substrate and the third electrode substrate, and connected in parallel to the DC link capacitors; and a plurality of second Y-capacitors connected in series to each of the first electrode substrate and the third electrode substrate, and connected in parallel to the first Y-capacitors, thereby achieving a miniaturization and facilitating a fabrication by connecting the plurality of DC link capacitors using the PCB.

Abstract translation: 直流（DC）链路电容器模块包括通过顺序地布置第一电极基板，绝缘基板，第二电极基板，第三电极基板形成的印刷电路板（PCB） 与第一电极基板和第二电极基板中的每一个并联连接的多个DC链路电容器; 多个第一Y电容器，与第一电极基板和第三电极基板中的每一个串联连接，并联连接到直流链路电容器; 以及与第一电极基板和第三电极基板中的每一个串联连接并与第一Y电容器并联连接的多个第二Y电容器，从而实现小型化，并且通过将多个DC链路 电容使用PCB。

公开(公告)号：US08743560B2

公开(公告)日：2014-06-03

申请号：US13198224

申请日：2011-08-04

Applicant: Yonghoon Kim ,  Hyunki Kim ,  Heeseok Lee

Inventor： Yonghoon Kim ,  Hyunki Kim ,  Heeseok Lee

IPC: H05K7/00 ,  H05K1/18

CPC classification number: H05K1/0231 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/19105 ,  H05K1/185 ,  H05K3/4608 ,  H05K2201/09345 ,  H05K2201/10015 ,  H01L2924/00014

Abstract: In one embodiment, a circuit board is disclosed. The circuit board includes a first metal core; a second metal core spaced apart from the first metal core in a first direction when viewed as a cross section, such that a first side of the first metal core faces a first side of the second metal core; a first electrode electrically connected to the first side of the first metal core; a second electrode electrically connected to the first side of the second metal core facing the first metal core; and a dielectric layer between the first and second electrodes.

Abstract translation: 在一个实施例中，公开了电路板。 电路板包括第一金属芯; 第一金属芯与第一金属芯沿第一方向间隔开，当第一金属芯作为横截面时，第一金属芯的第一面朝向第二金属芯的第一侧; 电连接到第一金属芯的第一侧的第一电极; 电连接到所述第二金属芯的面向所述第一金属芯的所述第一侧的第二电极; 以及在第一和第二电极之间的介电层。

公开(公告)号：US08716851B2

公开(公告)日：2014-05-06

申请号：US13417879

申请日：2012-03-12

Applicant: Francesco Preda ,  Lloyd A. Walls

Inventor： Francesco Preda ,  Lloyd A. Walls

IPC: H01L23/02

CPC classification number: H01L23/50 ,  H01L23/5383 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0253 ,  H05K1/0298 ,  H05K1/181 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/10522 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A mechanism for continuously referencing signals over multiple layers in laminate packages provides a continuous path for signals from one layer to another while using the ideal voltage reference for all areas of the package and still avoiding discontinuities in the voltage reference. A reference plane adjustment engine analyzes a package design and identifies an ideal top plane for all areas of the package, including areas under particular chip die(s) and areas that are not under a chip die. The reference plane adjustment engine then modifies the package design to reposition ground planes, source voltage planes, signal planes, and vias between layers to maintain a continuous voltage reference regardless of the top layer. The reference plane adjustment engine provides the resulting mixed voltage plane package design to a design analysis engine. A package fabrication system fabricates the package.

Abstract translation: 用于在层压封装中连续地参考多层信号的机构提供了用于从一层到另一层的信号的连续路径，同时使用用于封装的所有区域的理想电压基准并且仍避免电压基准中的不连续性。 参考平面调整引擎分析封装设计，并为封装的所有区域（包括特定芯片裸片下的区域）和不在芯片裸片下的区域识别理想的顶层平面。 参考平面调整引擎然后修改封装设计以重新定位层之间的接地层，源电压平面，信号面和通孔，以保持连续的电压基准，而不管顶层如何。 参考平面调整引擎将所得到的混合电压平面封装设计提供给设计分析引擎。 包装制造系统制造包装。

公开(公告)号：US20130294075A1

公开(公告)日：2013-11-07

申请号：US13995996

申请日：2011-12-09

Applicant: Hugo Johan Cornelissen ,  Giovanni Cennini ,  Tim Dekker

Inventor： Hugo Johan Cornelissen ,  Giovanni Cennini ,  Tim Dekker

IPC: F21V7/00 ,  H05K3/10

CPC classification number: F21V7/0083 ,  F21S8/00 ,  F21V7/00 ,  F21Y2105/10 ,  F21Y2115/10 ,  H05K1/162 ,  H05K1/189 ,  H05K3/10 ,  H05K2201/09345 ,  H05K2201/10106 ,  Y10T29/49155

Abstract: A lighting system comprises a circuit board (30) which carries a lighting circuit comprising a plurality of lighting elements (72). The surface of the circuit board (30) carrying the lighting elements is at least partially reflective. A spacer layer (70) is over the circuit board and a top reflector (82) is over the spacer layer. The spacer layer defines a light cavity air gap between the circuit board and the top reflector, and the top reflector and/or the circuit board is provided with an array of light out-coupling structures.

Abstract translation: 照明系统包括电路板（30），其承载包括多个照明元件（72）的照明电路。 携带照明元件的电路板（30）的表面至少是部分反射的。 间隔层（70）在电路板上方，顶部反射器（82）在间隔层上方。 间隔层限定了电路板和顶部反射器之间的光腔气隙，并且顶部反射器和/或电路板设置有一个出光耦合结构的阵列。

公开(公告)号：US08497567B2

公开(公告)日：2013-07-30

申请号：US13523301

申请日：2012-06-14

Applicant: Shinji Rokuhara

Inventor： Shinji Rokuhara

IPC: H01L27/08

CPC classification number: H01G4/33 ,  H01G4/228 ,  H01G4/385 ,  H01L23/50 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/025 ,  H05K1/162 ,  H05K2201/09345 ,  H05K2201/09663 ,  H01L2924/00

Abstract: A thin-film capacitor with first capacitative elements each having an electrode layer with a first polarity on an upper surface of a dielectric layer and an electrode layer with a second polarity on a lower surface of the dielectric layer; second capacitative elements each having an electrode layer with the second polarity on the upper surface and an electrode layer with the first polarity on the lower surface and arranged around a specific position alternately with the first capacitative elements; a single common connection hole at the specific position connecting all electrode layers with the first polarity of the first and second capacitative elements; and individual connection holes around the common connection hole connecting each electrode layer with the second polarity of the adjacent and second capacitative elements.

Abstract translation: 一种具有第一电容元件的薄膜电容器，每个电介质层在电介质层的上表面上具有第一极性的电极层和在介电层的下表面上具有第二极性的电极层; 第二电容元件各自具有在上表面上具有第二极性的电极层和在下表面上具有第一极性的电极层，并且与第一电容元件交替地布置在特定位置周围; 在所述第一和第二电容元件的第一极性连接所有电极层的特定位置处的单个公共连接孔; 以及连接每个电极层与相邻和第二电容元件的第二极性的公共连接孔周围的各个连接孔。

公开(公告)号：US08237055B2

公开(公告)日：2012-08-07

申请号：US12564734

申请日：2009-09-22

Applicant: Wang-Jia Chen ,  Wei Zhou ,  Yu-Hsu Lin ,  Feng Zhang

Inventor： Wang-Jia Chen ,  Wei Zhou ,  Yu-Hsu Lin ,  Feng Zhang

IPC: H05K1/00

CPC classification number: H05K1/025 ,  H05K1/0245 ,  H05K2201/09236 ,  H05K2201/09318 ,  H05K2201/09345 ,  H05K2201/09727

Abstract: A circuit board includes an insulation layer, a signal layer disposed on one side of the insulation layer, and a ground plane and a power plane disposed on the insulation layer at a side opposite to the signal layer. The insulation layer forms a separating area arranged between the ground plane and the power plane. At least two signal traces parallel to each other are arranged on the signal layer at one side corresponding to one of the ground plane and the power plane. A width of the signal trace close to the separating area is wider than that of the signal trace away from the separating area.

Abstract translation: 电路板包括绝缘层，设置在绝缘层的一侧的信号层，以及设置在与信号层相对的一侧的绝缘层上的接地面和电源面。 绝缘层形成布置在接地平面和电源平面之间的分离区域。 彼此平行的至少两条信号迹线在对应于接地平面和电源平面之一的一侧上布置在信号层上。 靠近分离区域的信号迹线的宽度比远离分离区域的信号迹线宽。

公开(公告)号：US20120063108A1

公开(公告)日：2012-03-15

申请号：US13198224

申请日：2011-08-04

Applicant: Yonghoon Kim ,  Hyunki Kim ,  Heeseok Lee

Inventor： Yonghoon Kim ,  Hyunki Kim ,  Heeseok Lee

IPC: H05K1/18 ,  H05K1/02

CPC classification number: H05K1/0231 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/19105 ,  H05K1/185 ,  H05K3/4608 ,  H05K2201/09345 ,  H05K2201/10015 ,  H01L2924/00014

Abstract: In one embodiment, a circuit board is disclosed. The circuit board includes a first metal core; a second metal core spaced apart from the first metal core in a first direction when viewed as a cross section, such that a first side of the first metal core faces a first side of the second metal core; a first electrode electrically connected to the first side of the first metal core; a second electrode electrically connected to the first side of the second metal core facing the first metal core; and a dielectric layer between the first and second electrodes.

Abstract translation: 在一个实施例中，公开了电路板。 电路板包括第一金属芯; 第一金属芯与第一金属芯沿第一方向间隔开，当第一金属芯作为横截面时，第一金属芯的第一面朝向第二金属芯的第一侧; 电连接到第一金属芯的第一侧的第一电极; 电连接到所述第二金属芯的面向所述第一金属芯的所述第一侧的第二电极; 以及在第一和第二电极之间的介电层。

公开(公告)号：US20100307795A1

公开(公告)日：2010-12-09

申请号：US12564734

申请日：2009-09-22

Applicant: WANG-JIA CHEN ,  WEI ZHOU ,  YU-HSU LIN ,  FENG ZHANG

Inventor： WANG-JIA CHEN ,  WEI ZHOU ,  YU-HSU LIN ,  FENG ZHANG

IPC: H05K1/00

CPC classification number: H05K1/025 ,  H05K1/0245 ,  H05K2201/09236 ,  H05K2201/09318 ,  H05K2201/09345 ,  H05K2201/09727

Abstract: A circuit board includes an insulation layer, a signal layer disposed on one side of the insulation layer, and a ground plane and a power plane disposed on the insulation layer at a side opposite to the signal layer. The insulation layer forms a separating area arranged between the ground plane and the power plane. At least two signal traces parallel to each other are arranged on the signal layer at one side corresponding to one of the ground plane and the power plane. A width of the signal trace close to the separating area is wider than that of the signal trace away from the separating area.

Abstract translation: 电路板包括绝缘层，设置在绝缘层的一侧的信号层，以及设置在与信号层相对的一侧的绝缘层上的接地面和电源面。 绝缘层形成布置在接地平面和电源平面之间的分离区域。 彼此平行的至少两条信号迹线在对应于接地平面和电源平面之一的一侧上布置在信号层上。 靠近分离区域的信号迹线的宽度比远离分离区域的信号迹线宽。

公开(公告)号：US07797824B2

公开(公告)日：2010-09-21

申请号：US10906073

申请日：2005-02-02

Applicant: Thonas Su

Inventor： Thonas Su

IPC: H05K1/02 ,  H05K3/00

CPC classification number: H05K1/0237 ,  H05K1/0227 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09345 ,  H05K2201/09663 ,  Y10T29/49155

Abstract: A method for decreasing impedance of a power source in a printed circuit board includes: (a) forming a first metal plane over a first layer of the printed circuit board; (b) forming a second metal plane and a third metal plane over a second layer of the printed circuit board; (c) forming a dielectric layer between the first layer and the second layer of the printed circuit board for insulating the first layer from the second layer; and (d) connecting the second metal plane to an electric potential different from an electric potential of the first metal plane and the third metal plane.

Abstract translation: 一种用于降低印刷电路板中的电源的阻抗的方法包括：（a）在印刷电路板的第一层上形成第一金属平面; （b）在所述印刷电路板的第二层上形成第二金属平面和第三金属平面; （c）在印刷电路板的第一层和第二层之间形成绝缘层，用于使第一层与第二层绝缘; 和（d）将第二金属平面连接到不同于第一金属平面和第三金属平面的电位的电位。