-
公开(公告)号：US07508069B2
公开(公告)日：2009-03-24
申请号：US11436946
申请日：2006-05-18
Applicant: James Douglas Wehrly, Jr. , Ron Orris , Leland Szewerenko , Tim Roy , Julian Partridge , David L. Roper
Inventor： James Douglas Wehrly, Jr. , Ron Orris , Leland Szewerenko , Tim Roy , Julian Partridge , David L. Roper
IPC: H01L23/34
CPC classification number: H01L25/18 , H01L23/5387 , H01L25/105 , H01L2224/49175 , H01L2924/15311 , H05K1/147 , H05K1/189 , H05K3/326 , H05K3/3421 , H05K3/3436 , H05K3/3447 , H05K2201/055 , H05K2201/091 , H05K2201/09463 , H05K2201/10515 , H05K2201/10689
Abstract: The present invention provides a system and method for combining a leaded package IC and a semiconductor die using a flex circuitry to reduce footprint for the combination. A leaded IC package is disposed along the obverse side of a flex circuit. In a preferred embodiment, leads of the leaded IC package are configured to allow the lower surface of the body of the leaded IC package to contact the surface of the flex circuitry either directly or indirectly through an adhesive. A semiconductor die is connected to the reverse side of the flex circuit. In one embodiment, the semiconductor die is disposed on the reverse side of the flex while, in an alternative embodiment, the semiconductor die is disposed into a window in the flex circuit to rest directly or indirectly upon the body of the leaded IC package. Module contacts are provided in a variety of configurations. In a preferred embodiment, the leaded IC package is a flash memory and the semiconductor die is a controller.
Abstract translation: 本发明提供一种用于使用柔性电路组合引线封装IC和半导体管芯以减少组合的覆盖区的系统和方法。 引线IC封装沿柔性电路的正面设置。 在优选实施例中，引线IC封装的引线被配置为允许引线IC封装的主体的下表面通过粘合剂直接或间接地接触柔性电路的表面。 半导体管芯连接到柔性电路的反面。 在一个实施例中，半导体管芯设置在柔性反面的另一侧，而在替代实施例中，将半导体管芯设置在柔性电路中的窗口中，以直接或间接地安置在引线IC封装体上。 模块触点以各种配置提供。 在优选实施例中，引线IC封装是闪存，半导体管芯是控制器。
-
公开(公告)号：US20080284535A1
公开(公告)日：2008-11-20
申请号：US11975753
申请日：2007-10-22
Applicant: Takeshi Uchida , Manabu Ito , Tomotaka Kuroda
Inventor： Takeshi Uchida , Manabu Ito , Tomotaka Kuroda
CPC classification number: H01R43/0256 , H01R12/52 , H05K1/141 , H05K3/3447 , H05K3/368 , H05K2201/09036 , H05K2201/09463 , H05K2201/10303 , H05K2201/1084 , H05K2201/10871 , H05K2203/1178 , Y10T428/24612
Abstract: The present invention relates to a two-level mounting board in which a second substrate is supported horizontally by a metal pin above a first substrate having a mounting electrode on an outer base surface, the free, lower end of the metal pin is inserted in a hole provided in the surface of the first substrate, and the metal pin is affixed by solder to an annular electrode land provided on the surface of the first substrate to form an outer periphery of the hole, wherein part of the ring of the annular electrode land is cut away to open the same. This provides a two-level mounting board in which metal pins can be connected reliably to the first substrate to support the second substrate horizontally, and a crystal oscillator using the same.
Abstract translation: 本发明涉及一种二级安装板，其中第二基板由位于外基座表面上的具有安装电极的第一基板上的金属销水平支撑，金属销的自由下端插入 并且所述金属销通过焊料固定到设置在所述第一基板的表面上的环形电极焊盘，以形成所述孔的外周，其中所述环形电极的环的一部分 被切开打开一样。 这提供了两级安装板，其中金属引脚可以可靠地连接到第一基板以水平地支撑第二基板，以及使用其的晶体振荡器。
-
公开(公告)号：US20070108619A1
公开(公告)日：2007-05-17
申请号：US11274016
申请日：2005-11-15
Applicant: Jun Hsu
Inventor： Jun Hsu
IPC: H01L29/40
CPC classification number: H05K1/112 , H01L24/10 , H01L24/13 , H01L2224/13 , H01L2224/13099 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H05K1/116 , H05K3/244 , H05K3/421 , H05K2201/09436 , H05K2201/09463 , H05K2201/09509 , H05K2201/09545 , H05K2201/09663 , H01L2924/00
Abstract: A bonding pad with high bonding strength to a solder ball and a bump includes a carrier, a wiring layer formed on the carrier, a protection layer formed on top of the wiring layer and a solder mask layer surrounded around the protection layer and the wiring layer to form a bonding pad opening. The protection layer is extended outside the bonding pad opening such that when solder are extended into the bonding pad opening, the solder balls engage with side faces defining the bump pad opening as well as the protection layer outside the bump pad opening and a bonding strength between the bonding pad and the solder performance is increased.
Abstract translation: 具有对焊球和凸块具有高结合强度的接合焊盘包括载体，形成在载体上的布线层，形成在布线层顶部的保护层和围绕保护层和布线层围绕的焊料掩模层 以形成接合焊盘开口。 保护层延伸到接合焊盘开口的外部，使得当焊料延伸到焊盘开口中时，焊球与限定凸块焊盘开口的侧面以及凸块焊盘开口之外的保护层接合， 焊盘和焊料性能提高。
-
公开(公告)号：US07126061B2
公开(公告)日：2006-10-24
申请号：US10861455
申请日：2004-06-07
Applicant: Yung-Jen Lin
Inventor： Yung-Jen Lin
IPC: H05K1/16
CPC classification number: H05K3/403 , H05K1/116 , H05K3/0052 , H05K3/42 , H05K2201/09463 , H05K2201/09663
Abstract: A printed circuit board for avoiding producing burrs, the printed circuit board includes a packaging substrate, at least one plated through hole, at least one first conductive portion, at least one non-conductive portion, at least one second conductive portion and at least one cut section. The plated through hole is formed on the packaging substrate. The first conductive portion and the second conductive portion respectively are adjacent to two sides of a peripheral of the plated through hole and separated by the non-conductive portion. Furthermore, the cut section is arranged on the non-conductive portion, thus the packaging substrate is cut without passing through the first conductive portion, and it will not cause the burrs on the first conductive portion.
Abstract translation: 一种用于避免产生毛刺的印刷电路板，印刷电路板包括封装基板，至少一个电镀通孔，至少一个第一导电部分，至少一个非导电部分，至少一个第二导电部分和至少一个第二导电部分 切割部分。 电镀通孔形成在封装基板上。 第一导电部分和第二导电部分分别与电镀通孔的周边的两侧相邻并且被非导电部分分开。 此外，切断部配置在非导电部分上，因此封装基板被切割而不穿过第一导电部分，并且不会在第一导电部分上引起毛刺。
-
公开(公告)号：US20050072596A1
公开(公告)日：2005-04-07
申请号：US10861455
申请日：2004-06-07
Applicant: Yung-Jen Lin
Inventor： Yung-Jen Lin
CPC classification number: H05K3/403 , H05K1/116 , H05K3/0052 , H05K3/42 , H05K2201/09463 , H05K2201/09663
Abstract: A printed circuit board for avoiding producing burrs, the printed circuit board includes a packaging substrate, at least one plated through hole, at least one first conductive portion, at least one non-conductive portion, at least one second conductive portion and at least one cut section. The plated through hole is formed on the packaging substrate. The first conductive portion and the second conductive portion respectively are adjacent to two sides of a peripheral of the plated through hole and separated by the non-conductive portion. Furthermore, the cut section is arranged on the non-conductive portion, thus the packaging substrate is cut without passing through the first conductive portion, and it will not cause the burrs on the first conductive portion.
Abstract translation: 一种用于避免产生毛刺的印刷电路板，印刷电路板包括封装基板，至少一个电镀通孔，至少一个第一导电部分，至少一个非导电部分，至少一个第二导电部分和至少一个第二导电部分 切割部分。 电镀通孔形成在封装基板上。 第一导电部分和第二导电部分分别与电镀通孔的周边的两侧相邻并且被非导电部分分开。 此外，切断部配置在非导电部分上，因此封装基板被切割而不穿过第一导电部分，并且不会在第一导电部分上引起毛刺。
-
Patent Agency Ranking
公开(公告)号：US20010045444A1
公开(公告)日：2001-11-29
申请号：US09912311
申请日：2001-07-26
Applicant: FUJI PHOTO FILM., LTD.
Inventor： Masayoshi Muramatsu , Kenichi Watanabe
IPC: B23K037/02
CPC classification number: B23K1/0016 , B23K2101/42 , H05K1/116 , H05K3/3447 , H05K3/3468 , H05K2201/09463 , H05K2201/09854 , H05K2201/10969
Abstract: A pair of soldering irons are fixed to a sliding plate at a predetermined interval. The soldering irons are integrally moved so as to reciprocate in a rectangular direction relative to a conveyor belt. One of the soldering irons is conveyed to a working position of the conveyor belt and the other of them is separated from the conveyor belt. While one of the soldering irons solders a circuit board, the other is cleaned. The circuit board has a slit into which a metal plate is inserted and soldered. For the slit, a soldering land constituted of a main-land and a sub-land is provided. The main-land is formed along one of longer sides of the slit. The sub-land is elongated from the main-land along a shorter side of the slit. The soldering land is not formed all around the slit so that the slit is not closed by solder when the circuit board is dip-soldered.
-
47.发明授权
公开(公告)号：US4851614A
公开(公告)日：1989-07-25
申请号：US238983
申请日：1988-08-24
Applicant: Wayne P. Duncan, Jr.
Inventor： Wayne P. Duncan, Jr.
CPC classification number: H05K3/0094 , H05K1/0215 , H05K1/116 , H05K3/3468 , H05K1/115 , H05K2201/09463 , H05K2201/0979 , H05K2201/099 , H05K2201/10409 , H05K2203/044 , H05K2203/045 , H05K3/325 , H05K3/429 , Y10T29/49149 , Y10T29/49169
Abstract: A novel solder pad configuration for printed circuit boards is disclosed which is resistant to solder occlusion upon wave soldering. On the solder side of the circuit board the solder pad is substantially C-shaped and partially surrounds a non-plated through-hole. Via holes prvide electrical connection between the pad on the solder side of the board and the corresponding pad on the component side of the circuit boards. The invention is particularly applicable to the chassis ground mounting holes of PCB's.
Abstract translation: 公开了一种用于印刷电路板的新型焊盘配置，其在波峰焊时耐焊接阻塞。 在电路板的焊料侧，焊盘基本上是C形的，并且部分地围绕着未镀覆的通孔。 通孔在电路板的焊料侧的焊盘和电路板的组件侧的相应焊盘之间提供电连接。 本发明特别适用于PCB的底盘接地安装孔。
-
公开(公告)号：US20180184514A1
公开(公告)日：2018-06-28
申请号：US15807648
申请日：2017-11-09
Applicant: FUJITSU LIMITED
Inventor： Tetsuro Yamada , AKIKO MATSUI , Mitsuhiko Sugane , Takahide Mukoyama , YOSHIYUKI HIROSHIMA , Kohei Choraku
IPC: H05K1/02 , H05K1/18 , H05K1/11 , H01L23/498 , H01L23/00
CPC classification number: H05K1/0213 , H01L23/49816 , H01L24/16 , H01L2224/16235 , H01L2924/15311 , H05K1/0265 , H05K1/113 , H05K1/115 , H05K1/116 , H05K1/181 , H05K2201/09463 , H05K2201/09609 , H05K2201/0979 , H05K2201/10378 , H05K2201/10734
Abstract: A printed circuit board includes a power feeding layer to which a power supply voltage is applied, a plurality of power feeding terminals that is disposed in an area, in which an electronic component is mounted, and supplies current based on the power supply voltage to the electronic component, and a plurality of vias that electrically interconnects the plurality of power feeding terminals and the power feeding layer, and is formed such that a via coupled to a power feeding terminal disposed closer to an end of the area has a smaller via-diameter.
-
公开(公告)号：US20170280568A1
公开(公告)日：2017-09-28
申请号：US15621403
申请日：2017-06-13
Applicant: Intel Corporation
Inventor： Brandon M. Rawlings , Henning Braunisch
CPC classification number: H05K3/0082 , H05K1/116 , H05K3/422 , H05K3/424 , H05K3/4647 , H05K3/4679 , H05K2201/09463 , H05K2201/09854 , H05K2203/0505
Abstract: A photoresist is deposited on a seed layer on a substrate. A first region of the photoresist is removed to expose a first portion of the seed layer to form a via-pad structure. A first conductive layer is deposited onto the first portion of the seed layer. A second region of the photoresist adjacent to the first region is removed to expose a second portion of the seed layer to form a line. A second conductive layer is deposited onto the first conductive layer and the second portion of the seed layer.
-
公开(公告)号：US20160183370A1
公开(公告)日：2016-06-23
申请号：US14576107
申请日：2014-12-18
Applicant: Intel Corporation
Inventor： Brandon M. Rawlings , Henning BRAUNISCH
CPC classification number: H05K3/0082 , H05K1/116 , H05K3/422 , H05K3/424 , H05K3/4647 , H05K3/4679 , H05K2201/09463 , H05K2201/09854 , H05K2203/0505
Abstract: A photoresist is deposited on a seed layer on a substrate. A first region of the photoresist is removed to expose a first portion of the seed layer to form a via-pad structure. A first conductive layer is deposited onto the first portion of the seed layer. A second region of the photoresist adjacent to the first region is removed to expose a second portion of the seed layer to form a line. A second conductive layer is deposited onto the first conductive layer and the second portion of the seed layer.
Abstract translation: 光致抗蚀剂沉积在基底上的种子层上。 去除光致抗蚀剂的第一区域以暴露种子层的第一部分以形成通孔垫结构。 第一导电层沉积在种子层的第一部分上。 去除与第一区域相邻的光致抗蚀剂的第二区域以暴露种子层的第二部分以形成线。 第二导电层沉积在第一导电层和籽晶层的第二部分上。
-
-
-
-
-
-
-
-
-
Search Results
62
records
(took 0.012 seconds)
