公开(公告)号：US20100117245A1

公开(公告)日：2010-05-13

申请号：US12691255

申请日：2010-01-21

Applicant: Chonghua Zhong

Inventor： Chonghua Zhong

IPC: H01L23/488 ,  H05K1/11

CPC classification number: H01L23/5382 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0293 ,  H05K3/321 ,  H05K3/3452 ,  H05K2201/0305 ,  H05K2201/09381 ,  H05K2201/09809 ,  H05K2201/0989 ,  H05K2201/10674 ,  H05K2203/173 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Methods, systems, and apparatuses for integrated circuit package substrates, integrated circuit packages, and processes for assembling the same, are provided. A substrate for a flip chip integrated circuit package includes a substrate body having opposing first and second surfaces. A solder mask layer covers at least a portion of the first surface of the substrate body. First and second electrically conductive features are formed on the substrate body. The first electrically conductive feature is a portion of a first electrical signal net, and the second electrically conductive feature is a portion of a second electrical signal net. The first and second electrically conductive features are configured to be selectively electrically coupled together by application of an electrically conductive material. The electrically conductive material may be a conductive epoxy, a jumper, a solder paste, a solder ball, or a solder bump that couples a flip chip die to the substrate.

Abstract translation: 提供了用于集成电路封装基板，集成电路封装以及用于组装其的工艺的方法，系统和装置。 用于倒装芯片集成电路封装的衬底包括具有相对的第一和第二表面的衬底本体。 焊接掩模层覆盖基板主体的第一表面的至少一部分。 第一和第二导电特征形成在衬底主体上。 第一导电特征是第一电信号网的一部分，第二导电特征是第二电信号网的一部分。 第一和第二导电特征被配置为通过施加导电材料选择性地电耦合在一起。 导电材料可以是导电环氧树脂，跳线，焊膏，焊球或将倒装芯片裸片耦合到衬底的焊料凸块。

公开(公告)号：US07691745B1

公开(公告)日：2010-04-06

申请号：US12187578

申请日：2008-08-07

Applicant: Akito Yoshida ,  Mahmoud Dreiza

Inventor： Akito Yoshida ,  Mahmoud Dreiza

IPC: H01L21/44 ,  H01L21/28

CPC classification number: H01L21/565 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49838 ,  H01L25/105 ,  H01L2924/0002 ,  H01L2924/1433 ,  H05K3/3452 ,  H05K2201/094 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A semiconductor device has a substrate and an encapsulation area on a first surface of the substrate. A first plurality of metal lands is on the first surface of the substrate around a periphery of the encapsulation area. Solder mask coverers portions of the first plurality of metal lands closest to the encapsulation area. Remaining portions of the first plurality of metal lands are exposed areas having no solder mask.

Abstract translation: 半导体器件在衬底的第一表面上具有衬底和封装区域。 第一多个金属焊盘位于衬底周围的封装区域的第一表面上。 焊接掩模覆盖最靠近封装区域的第一多个金属焊盘的部分。 第一多个金属焊盘的剩余部分是没有焊接掩模的暴露区域。

公开(公告)号：US20100078662A1

公开(公告)日：2010-04-01

申请号：US12239494

申请日：2008-09-26

Applicant: Wei Shi ,  Alex Shaikevitch

Inventor： Wei Shi ,  Alex Shaikevitch

IPC: H01L33/00

CPC classification number: H01L33/62 ,  H01L25/0753 ,  H01L33/54 ,  H01L33/60 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49175 ,  H05K1/0274 ,  H05K3/28 ,  H05K2201/0989 ,  H05K2201/10106 ,  H05K2201/2054 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A substrate for an LED assembly can have a plurality of cups formed therein. At least one cup can be formed within another cup. The cups can be co-axial with respect to one another, for example. A machined surface of the substrate can enhance reflectivity of the LED assembly. A transparent and/or non-global solder mask can enhance reflectivity of the LED assembly. A transparent ring can enhance reflectivity of the LED assembly. By enhancing reflectivity of the LED assembly, the brightness of the LED assembly can be increased. Brighter LED assemblies can be used in applications such as flashlights, displays, and general illumination.

Abstract translation: 用于LED组件的基板可以具有形成在其中的多个杯。 至少一杯可以在另一杯内形成。 例如，杯可以相对于彼此共轴。 衬底的加工表面可以增强LED组件的反射率。 透明和/或非全局焊接掩模可以增强LED组件的反射率。 透明环可以增强LED组件的反射率。 通过提高LED组件的反射率，可以提高LED组件的亮度。 较亮的LED组件可用于手电筒，显示屏和一般照明等应用中。

公开(公告)号：US20100046185A1

公开(公告)日：2010-02-25

申请号：US12544156

申请日：2009-08-19

Applicant: Hideaki Hirasawa

Inventor： Hideaki Hirasawa

IPC: H05K1/18 ,  H05K1/11 ,  H05K1/00

CPC classification number: H05K1/11 ,  H05K1/0203 ,  H05K1/111 ,  H05K3/3421 ,  H05K3/3452 ,  H05K3/3468 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/0989 ,  H05K2201/10522 ,  H05K2201/10659 ,  H05K2201/10689 ,  H05K2203/046 ,  Y02P70/611

Abstract: A printed circuit board has a first solder land, a second solder land, and a signal line pattern. The first solder land is configured to be soldered with an electronic part. The second solder land is configured to accumulate solder, the second solder land being disposed on a downstream side of the first solder land as viewed in a direction in which the printed circuit is carried. The signal line pattern includes an exposed part that is not covered with a resist, the exposed part being disposed between the solder land and the solder bridge prevention land.

Abstract translation: 印刷电路板具有第一焊盘焊盘，第二焊盘焊盘和信号线图案。 第一焊盘被配置为与电子部件焊接。 第二焊盘被构造为蓄积焊料，第二焊盘位于沿着印刷电路的携带方向设置在第一焊盘的下游侧。 信号线图案包括未被抗蚀剂覆盖的暴露部分，暴露部分设置在焊接区域和防止桥接防止焊盘之间。

公开(公告)号：US07647694B2

公开(公告)日：2010-01-19

申请号：US10560849

申请日：2004-05-05

Applicant: Misao Konishi ,  Hidetsugu Namiki ,  Jyunji Shinozaki

Inventor： Misao Konishi ,  Hidetsugu Namiki ,  Jyunji Shinozaki

IPC: H05K3/30 ,  H05K3/34

CPC classification number: H05K13/0469 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29399 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/14 ,  H05K3/323 ,  H05K3/3452 ,  H05K2201/0989 ,  H05K2201/10674 ,  H05K2203/1105 ,  H05K2203/1178 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method for mounting through an anisotropic conductive film defined as an adhesive sheet an electronic component on a printed circuit board (flexible board) provided with a wiring pattern. The anisotropic conductive film is bonded to an area of the flexible board to be mounted with the electronic component in a state where air intervening between the anisotropic conductive film and the flexible board is heated. Since the air confined between the anisotropic conductive film and the flexible board reduces in volume upon cooled down, occurrence of voids, exposure of the wiring pattern, or the like is avoided. Consequently, reliability can be enhanced without complicating the mounting.

Abstract translation: 一种在设置有布线图案的印刷电路板（柔性基板）上安装通过定义为粘合片的电子部件的各向异性导电膜的方法。 各向异性导电膜在各向异性导电膜和柔性基板之间的空气被加热的状态下与电子部件安装的柔性基板的区域接合。 由于在各向异性导电膜和柔性基板之间限制的空气在冷却时体积减小，因此避免了空隙的发生，布线图案的曝光等。 因此，可以提高可靠性，而不会使安装复杂化。

公开(公告)号：US20100005653A1

公开(公告)日：2010-01-14

申请号：US12563849

申请日：2009-09-21

Applicant: Makoto Murai ,  Yasuhiro Kohara ,  Ryosuke Usui

Inventor： Makoto Murai ,  Yasuhiro Kohara ,  Ryosuke Usui

IPC: H05K3/10

CPC classification number: H05K3/243 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L2224/05553 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/49171 ,  H01L2224/81801 ,  H01L2224/85444 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/351 ,  H05K3/284 ,  H05K3/3452 ,  H05K3/382 ,  H05K2201/0989 ,  H05K2203/049 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49222 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: The likelihood of exfoliation of a sealing resin layer at a pad electrode part is reduced so that the reliability of a circuit apparatus is improved. A circuit apparatus includes a wiring layer, a gold plating layer, an insulating resin layer, a circuit element, a conductive member and sealing resin layer. The gold plating layer is formed in an wiring layer area for the pad electrode. The surface outside the area is roughened. The insulating resin layer is formed so as to cover the wiring layer and to have an opening in an area in which the pad electrode is formed. The circuit element is mounted on a predetermined area on the insulating resin layer. The sealing resin layer is formed on the insulating resin layer so as to entirely cover the circuit element and the opening for the pad electrode. The sealing resin layer, in the area for the pad electrode, is in contact with the gold plating layer and the wiring layer.

Abstract translation: 密封树脂层在焊盘电极部分的剥离的可能性降低，从而提高了电路设备的可靠性。 电路装置包括布线层，镀金层，绝缘树脂层，电路元件，导电构件和密封树脂层。 金电镀层形成在焊盘电极的布线层区域中。 该地区外面的表面粗糙。 绝缘树脂层形成为覆盖布线层，并且在形成焊盘电极的区域中具有开口。 电路元件安装在绝缘树脂层上的预定区域上。 密封树脂层形成在绝缘树脂层上，以完全覆盖电路元件和焊盘电极的开口。 用于焊盘电极的区域中的密封树脂层与镀金层和布线层接触。

公开(公告)号：US20090288858A1

公开(公告)日：2009-11-26

申请号：US12181556

申请日：2008-07-29

Applicant: Chih-Peng Fan ,  Yen-Ti Chia

Inventor： Chih-Peng Fan ,  Yen-Ti Chia

IPC: H05K3/02 ,  H05K1/00

CPC classification number: H05K1/111 ,  H01L2224/16225 ,  H05K3/108 ,  H05K3/243 ,  H05K3/3452 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0989 ,  H05K2201/10674 ,  H05K2203/0574 ,  Y02P70/611 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A manufacturing method of a circuit structure is provided as follows. Firstly, a base conductive layer is formed on the carrier board and a first patterned plating-resistant layer having at least one trench for exposing a part of the base conductive layer is formed on the base conductive layer. A first patterned conductive layer is then formed in the trench and a second patterned plating-resistant layer is formed which covers a part of the first patterned conductive layer and a part of the first patterned plating-resistant layer. A second patterned conductive layer is formed on the exposed first patterned conductive layer. The first and the second patterned plating-resistant layers and the base conductive layer exposed by the first patterned conductive layer are removed. Then, a patterned solder mask is formed for covering a part of the first patterned conductive layer.

Abstract translation: 电路结构的制造方法如下所述。 首先，在载体板上形成基底导电层，在基底导电层上形成具有至少一个露出基底导电层的一部分的沟槽的第一图案化电镀层。 然后在沟槽中形成第一图案化导电层，并且形成覆盖第一图案化导电层的一部分和第一图案化电镀层的一部分的第二图案化电镀层。 在暴露的第一图案化导电层上形成第二图案化导电层。 去除第一和第二图案化电镀层和由第一图案化导电层暴露的基底导电层。 然后，形成图案化的焊料掩模以覆盖第一图案化导电层的一部分。

公开(公告)号：US20090278249A1

公开(公告)日：2009-11-12

申请号：US12458429

申请日：2009-07-13

Applicant: Ky-hyun Jung ,  Heui-seog Kim ,  Sang-jun Kim ,  Wha-su Sin ,  Ho-geon Song ,  Jun-young Ko

Inventor： Ky-hyun Jung ,  Heui-seog Kim ,  Sang-jun Kim ,  Wha-su Sin ,  Ho-geon Song ,  Jun-young Ko

IPC: H01L23/498 ,  H05K1/11 ,  H01B5/00

CPC classification number: H05K3/282 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/16503 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83102 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/243 ,  H05K3/3457 ,  H05K2201/0391 ,  H05K2201/0989 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A printed circuit board and method thereof and a solder ball land and method thereof. The example printed circuit board (PCB) may include a first solder ball land having a first surface treatment portion configured for a first type of resistance and a second solder ball land having a second surface treatment portion configured for a second type of resistance. The example solder ball land may include a first surface treatment portion configured for a first type of resistance and a second surface treatment portion configured for a second type of resistance. A first example method may include first treating a first surface of a first solder ball land to increase a first type of resistance and second treating a second surface of a second solder ball land to increase a second type of resistance other than the first type of resistance. A second example method may include first treating a solder ball land to increase a first type of resistance and second treating the solder ball land to increase a second type of resistance other than the first type of resistance.

Abstract translation: 一种印刷电路板及其方法和焊球地及其方法。 示例性印刷电路板（PCB）可以包括具有构造成用于第一类型电阻的第一表面处理部分的第一焊球焊盘和具有被配置为用于第二类型电阻的第二表面处理部分的第二焊球焊盘。 示例性焊球焊盘可以包括被配置为用于第一类型电阻的第一表面处理部分和被配置用于第二类型电阻的第二表面处理部分。 第一示例性方法可以包括首先处理第一焊球焊盘的第一表面以增加第一类型的电阻，并且第二处理第二焊球焊盘的第二表面以增加除第一类型电阻之外的第二类型的电阻 。 第二示例性方法可以包括首先处理焊球焊盘以增加第一类型的电阻，并且第二次处理焊球焊盘以增加除第一类型电阻之外的第二类型的电阻。

公开(公告)号：US07615162B2

公开(公告)日：2009-11-10

申请号：US11522960

申请日：2006-09-19

Applicant: Motoo Asai ,  Yasuji Hiramatsu ,  Yoshinori Wakihara ,  Kazuhito Yamada

Inventor： Motoo Asai ,  Yasuji Hiramatsu ,  Yoshinori Wakihara ,  Kazuhito Yamada

IPC: H01B13/00

CPC classification number: H05K3/108 ,  H05K1/0269 ,  H05K3/067 ,  H05K3/244 ,  H05K3/3452 ,  H05K3/382 ,  H05K3/384 ,  H05K3/4661 ,  H05K2201/0989 ,  H05K2201/09918 ,  H05K2203/0307 ,  H05K2203/072 ,  Y10S428/901 ,  Y10T29/49002 ,  Y10T29/49156 ,  Y10T29/49167 ,  Y10T156/1056 ,  Y10T428/24917

Abstract: A printed circuit board is by formed by laminating an interlaminar insulating layer on a conductor circuit of a substrate, in which the conductor circuit is comprised of an electroless plated film and an electrolytic plated film and a roughened layer is formed on at least a part of the surface of the conductor circuit.

公开(公告)号：US20090211795A1

公开(公告)日：2009-08-27

申请号：US12394889

申请日：2009-02-27

Applicant: Noriyuki SHIRASAWA

Inventor： Noriyuki SHIRASAWA

IPC: H05K1/16

CPC classification number: H05K3/305 ,  H01L21/563 ,  H01L23/13 ,  H01L23/498 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/92125 ,  H05K3/3452 ,  H05K2201/09063 ,  H05K2201/0989 ,  H05K2201/09909 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y02P70/613 ,  Y10T29/49121 ,  Y10T29/49126 ,  H01L2924/00

Abstract: A printed board comprising a packaging surface on which an electronic component is packaged, an adhesion prohibited portion which is provided at a region of the printed board different from a region where the electronic component is provided, and to which adhesion of the adhesive material is prohibited, and a blocking step portion which is formed at a region between the region where the electronic component is provided and the region where the adhesion prohibited portion is provided, which blocks any adhesive material which has spilled out from between the bottom surface of the electronic component and the packaging surface from reaching the adhesion prohibited portion.

Abstract translation: 一种印刷电路板，包括封装有电子部件的封装表面，设置在与设置有电子部件的区域不同的印刷电路板的区域的粘合禁止部分，并且粘合剂材料的粘合被禁止 以及形成在设置电子部件的区域与设置有防粘连部的区域之间的区域的阻挡台阶部，其阻挡从电子部件的底面之间溅出的任何粘合材料 并且包装表面到达不粘附部分。