公开(公告)号：US20130309456A1

公开(公告)日：2013-11-21

申请号：US13943968

申请日：2013-07-17

Applicant: Elwha LLC

Inventor： Jeffrey A. Bowers ,  Alistair K. Chan ,  Geoffrey F. Deane ,  Nathan Kundtz ,  Nathan P. Myhrvold ,  David R. Smith ,  Lowell L. Wood, JR. ,  Roderick A. Hyde

IPC: H05K1/02 ,  H05K3/00 ,  B32B37/14

CPC classification number: H01G4/008 ,  B32B5/18 ,  B32B9/007 ,  B32B37/14 ,  B32B2266/04 ,  B32B2266/057 ,  B32B2266/126 ,  B32B2307/202 ,  B32B2457/08 ,  B82Y30/00 ,  H01G4/002 ,  H01G4/005 ,  H01L27/12 ,  H01L29/1606 ,  H01L29/78603 ,  H05K1/02 ,  H05K1/0274 ,  H05K1/0306 ,  H05K1/032 ,  H05K1/09 ,  H05K1/097 ,  H05K1/181 ,  H05K3/00 ,  H05K2201/0323 ,  H05K2201/10007 ,  H05K2201/10121 ,  Y10S977/734 ,  Y10T29/49128 ,  Y10T29/49826 ,  Y10T156/10 ,  Y10T428/24331 ,  Y10T428/24777 ,  Y10T428/24996 ,  Y10T428/249981 ,  Y10T428/24999 ,  Y10T428/30

Abstract: An apparatus having reduced phononic coupling between a graphene monolayer and a substrate is provided. The apparatus includes an aerogel substrate and a monolayer of graphene coupled to the aerogel substrate.

Abstract translation: 提供了一种在石墨烯单层和基底之间具有减小的声子耦合的装置。 该装置包括气凝胶基底和耦合到气凝胶基底的单层石墨烯。

公开(公告)号：US20090008765A1

公开(公告)日：2009-01-08

申请号：US11815580

申请日：2006-12-12

Applicant: Takaharu Yamano ,  Hajime Iizuka ,  Hideaki Sakaguchi ,  Toshio Kobayashi ,  Tadashi Arai ,  Tsuyoshi Kobayashi ,  Tetsuya Koyama ,  Kiyoaki Iida ,  Tomoaki Mashima ,  Koichi Tanaka ,  Yuji Kunimoto ,  Takashi Yanagisawa

Inventor： Takaharu Yamano ,  Hajime Iizuka ,  Hideaki Sakaguchi ,  Toshio Kobayashi ,  Tadashi Arai ,  Tsuyoshi Kobayashi ,  Tetsuya Koyama ,  Kiyoaki Iida ,  Tomoaki Mashima ,  Koichi Tanaka ,  Yuji Kunimoto ,  Takashi Yanagisawa

IPC: H01L23/48 ,  H01L21/00

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L25/162 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/207 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/185 ,  H05K1/186 ,  H05K3/20 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4644 ,  H05K2201/10007 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  H01L2924/00

Abstract: A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip.

Abstract translation: 公开了一种制造芯片嵌入式基板的方法。 该方法包括将半导体芯片安装在其上形成有第一布线的第一基板上的第一步骤; 以及将第一基板与形成有第二布线的第二基板接合的第二步骤。 在第二步骤中，将半导体芯片封装在第一基板和第二基板之间，并且在第一布线和第二布线之间形成电连接，以形成连接到半导体芯片的多层布线。

公开(公告)号：US20230262906A1

公开(公告)日：2023-08-17

申请号：US17670394

申请日：2022-02-11

Applicant: Alibaba (China) Co., Ltd.

Inventor： Hui LIU

IPC: H05K3/42 ,  H05K1/02 ,  H05K1/05

CPC classification number: H05K3/429 ,  H05K1/0298 ,  H05K1/05 ,  H05K2201/0959 ,  H05K2201/09981 ,  H05K2201/10007

Abstract: A substrate, a chip, a circuit package and a process of fabricating a substrate are presented. The substrate is provided between an integrated circuit and a printed circuit board, and comprises a core insulating and a buildup insulating layer. The first plated through hole is operable to provide ground through from the printed circuit board to the integrated circuit. The second plated through hole is operable to provide electrical communication carrying signals or power between the integrated circuit and the printed circuit board through the buildup insulating layers. The first plated through hole is formed in tubular shape defined an outer wall and an inner wall, and the second plated through hole is formed in the inner wall and is insulated with the first plated through hole.

公开(公告)号：US20180261578A1

公开(公告)日：2018-09-13

申请号：US15975758

申请日：2018-05-09

Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.

Inventor： Shih-Ping HSU ,  Chao-Tsung TSENG

IPC: H01L25/065 ,  H05K1/18 ,  H01L21/683 ,  H05K3/46 ,  H01L25/00 ,  H01L23/00 ,  H01L25/16 ,  H01L23/538 ,  H05K3/00 ,  H05K1/16 ,  H05K1/02 ,  H01L23/50 ,  H01L23/498 ,  H01L21/48 ,  H05K3/28 ,  H05K3/34

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16112 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2924/15153 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/0231 ,  H05K1/162 ,  H05K1/183 ,  H05K1/185 ,  H05K3/0032 ,  H05K3/0044 ,  H05K3/284 ,  H05K3/3431 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/10 ,  H05K2201/10007 ,  H05K2201/10015 ,  H05K2201/1003 ,  H05K2201/10037 ,  H05K2201/10545 ,  Y10T29/49131 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A method of manufacturing a package structure is provided, including forming a first wiring layer on a carrier board, forming a plurality of first conductors on the first wiring layer, forming a first insulating layer that encapsulates the first wiring layer and the first conductors, forming a second wiring layer on the first insulating layer, forming a plurality of second conductors on the second wiring layer, forming a second insulating layer that encapsulates the second wiring layer and the second conductors, and forming at least an opening on the second insulating layer for at least one electronic component to be disposed therein. Since the first and second insulating layers are formed before the opening, there is no need of stacking or laminating a substrate that already has an opening, and the electronic component will not be laminated and make a displacement. Therefore, the package structure thus manufactured has a high yield rate. The present invention further provides the package structure.

公开(公告)号：US09955604B2

公开(公告)日：2018-04-24

申请号：US14640873

申请日：2015-03-06

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Seiji Tokii ,  Manabu Tasaki

IPC: H05K1/18 ,  H05K7/02 ,  H05K3/30 ,  H05K13/04 ,  H05K7/00 ,  H05K1/16 ,  H05K3/28 ,  H05K3/34

CPC classification number: H05K7/02 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K1/181 ,  H05K1/182 ,  H05K3/284 ,  H05K3/301 ,  H05K3/3447 ,  H05K13/04 ,  H05K2201/10007 ,  H05K2201/10159 ,  H05K2201/10583 ,  H05K2201/10674

Abstract: A mounting structure for an electronic component and a method for mounting the electronic component are provided with a sufficient reinforcing effect for the relatively tall electronic component raised from a substrate. The mounting structure and the mounting method can easily respond to a change of the shape of the electronic component. In a mounting structure 1, a substrate 2 and an electronic component 4 raised on the substrate 2 are joined with bonding metal 3 and a reinforcing resin body 5 is bonded to the substrate 2 and the electronic component 4. The reinforcing resin body 5 includes a plurality of reinforcing resin layers 5a. The reinforcing resin layers 5a constituting the reinforcing resin body 5 are stacked in the height direction of the raised electronic component 4 along a side 4a of the electronic component 4 so as to be raised from the substrate 2.

公开(公告)号：US09723755B2

公开(公告)日：2017-08-01

申请号：US14865860

申请日：2015-09-25

Applicant: KONE Corporation

Inventor： Pasi Raassina

IPC: H05K7/20 ,  H05K1/18 ,  H05K1/02 ,  H05K1/14 ,  H05K13/00

CPC classification number: H05K7/20509 ,  H05K1/0203 ,  H05K1/141 ,  H05K1/181 ,  H05K7/209 ,  H05K7/20909 ,  H05K13/00 ,  H05K2201/10007

Abstract: A drive unit for driving a motor has a component assembly including a main circuit board having a component side and a solder side, one or more main circuit conductors formed in at least one layer of the main circuit board, a power component module including one or more power components, the power component module having electrical connection terminals for connecting the power component(s) to the one or more main circuit conductors of the main circuit board and a cooling plate coupled to the power component(s) in a manner enabling transfer of heat from the power component(s) to the cooling plate. The power component module is mounted to the component side of the main circuit board. The component assembly further includes a heat sink mounted on the cooling plate and a fan mounted on the heat sink.

公开(公告)号：US09635764B2

公开(公告)日：2017-04-25

申请号：US14866648

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Shipeng Qiu ,  Shawna Liff ,  Kayleen L Helms ,  Joshua D Heppner ,  Adel Elsherbini ,  Johanna Swan ,  Gary M. Barnes

IPC: H05K1/02 ,  H05K1/18 ,  H05K3/32 ,  H05K1/14 ,  H05K3/36 ,  H05K3/22 ,  H05K3/30 ,  H05K3/00

CPC classification number: H05K1/189 ,  H05K1/0278 ,  H05K1/028 ,  H05K1/036 ,  H05K1/144 ,  H05K3/0014 ,  H05K3/22 ,  H05K3/303 ,  H05K3/326 ,  H05K3/361 ,  H05K2201/0133 ,  H05K2201/0308 ,  H05K2201/041 ,  H05K2201/047 ,  H05K2201/057 ,  H05K2201/10007 ,  H05K2201/10128 ,  H05K2203/10 ,  H05K2203/104 ,  H05K2203/105 ,  H05K2203/1105 ,  H05K2203/1194

Abstract: An integrated circuit that includes a substrate having a shape memory material (SMM), the SMM is in a first deformed state and has a first crystallography structure and a first configuration, the SMM is able to be deformed from a first configuration to a second configuration, the SMM changes to a second crystallography structure and deforms back to the first configuration upon receiving energy, the SMM returns to the first crystallography structure upon receiving a different amount of energy; and an electronic component attached to substrate. In other forms, the SMM is in a first deformed state and has a first polymeric conformation and a first configuration, the SMM changes from a first polymeric conformation to a second polymeric conformation and be deformed from a first configuration to a second configuration, the SMM changes returns to the first polymeric conformation and deforms back to the first configuration upon receiving energy.

公开(公告)号：US20170094799A1

公开(公告)日：2017-03-30

申请号：US14866648

申请日：2015-09-25

Applicant: Shipeng Qiu ,  Shawna Liff ,  Kayleen L. Helms ,  Joshua D. Heppner ,  Adel Elsherbini ,  Johanna Swan ,  Gary M. Barnes

Inventor： Shipeng Qiu ,  Shawna Liff ,  Kayleen L. Helms ,  Joshua D. Heppner ,  Adel Elsherbini ,  Johanna Swan ,  Gary M. Barnes

IPC: H05K1/18 ,  H05K1/14 ,  H05K3/00 ,  H05K3/22 ,  H05K3/30 ,  H05K1/02 ,  H05K3/36

CPC classification number: H05K1/189 ,  H05K1/0278 ,  H05K1/028 ,  H05K1/036 ,  H05K1/144 ,  H05K3/0014 ,  H05K3/22 ,  H05K3/303 ,  H05K3/326 ,  H05K3/361 ,  H05K2201/0133 ,  H05K2201/0308 ,  H05K2201/041 ,  H05K2201/047 ,  H05K2201/057 ,  H05K2201/10007 ,  H05K2201/10128 ,  H05K2203/10 ,  H05K2203/104 ,  H05K2203/105 ,  H05K2203/1105 ,  H05K2203/1194

Abstract: An integrated circuit that includes a substrate having a shape memory material (SMM), the SMM is in a first deformed state and has a first crystallography structure and a first configuration, the SMM is able to be deformed from a first configuration to a second configuration, the SMM changes to a second crystallography structure and deforms back to the first configuration upon receiving energy, the SMM returns to the first crystallography structure upon receiving a different amount of energy; and an electronic component attached to substrate. In other forms, the SMM is in a first deformed state and has a first polymeric conformation and a first configuration, the SMM changes from a first polymeric conformation to a second polymeric conformation and be deformed from a first configuration to a second configuration, the SMM changes returns to the first polymeric conformation and deforms back to the first configuration upon receiving energy.

公开(公告)号：US09451702B2

公开(公告)日：2016-09-20

申请号：US14321030

申请日：2014-07-01

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Takaharu Yamano ,  Hajime Iizuka ,  Hideaki Sakaguchi ,  Toshio Kobayashi ,  Tadashi Arai ,  Tsuyoshi Kobayashi ,  Tetsuya Koyama ,  Kiyoaki Iida ,  Tomoaki Mashima ,  Koichi Tanaka ,  Yuji Kunimoto ,  Takashi Yanagisawa

IPC: H05K1/18 ,  H01L21/683 ,  H01L23/552 ,  H01L23/00 ,  H01L25/10 ,  H01L25/16 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H05K3/20 ,  H05K3/46

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L25/162 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/207 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/185 ,  H05K1/186 ,  H05K3/20 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4644 ,  H05K2201/10007 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  H01L2924/00

Abstract: An electronic part embedded substrate is disclosed. The electronic part embedded substrate includes a first substrate, a second substrate, an electronic part, an electrically connecting member, and a sealing member. A method of producing an electronic part embedded substrate is also disclosed. The method includes mounting an electronic part onto a first substrate, laminating a second substrate on the first substrate through an electrically connecting member; and filling a space between the first substrate and the second substrate with a sealing member to seal the electronic part.

Abstract translation: 公开了一种电子部件嵌入式基板。 电子部件嵌入式基板包括第一基板，第二基板，电子部件，电连接部件和密封部件。 还公开了一种制造电子部件嵌入式基板的方法。 该方法包括将电子部件安装到第一基板上，通过电连接部件将第二基板层压在第一基板上; 以及用密封构件填充第一基板和第二基板之间的空间以密封电子部件。

公开(公告)号：US09420685B2

公开(公告)日：2016-08-16

申请号：US14444583

申请日：2014-07-28

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Jean-Michel Riviere ,  Karine Saxod

IPC: H05K1/02 ,  H05K1/18 ,  H05K3/30 ,  H05K3/28 ,  H01L23/498 ,  H01L23/00

CPC classification number: H05K1/0271 ,  H01L23/49844 ,  H01L23/562 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16111 ,  H01L2224/16237 ,  H05K1/181 ,  H05K3/28 ,  H05K3/30 ,  H05K2201/0275 ,  H05K2201/09909 ,  H05K2201/10007 ,  H05K2201/2009 ,  Y10T29/4913 ,  H01L2924/014

Abstract: A substrate board includes an electrical connection network on a face thereof. An integrated-circuit chip is mounted to the face of the substrate board in electrical contact with the electrical connection network. A local reinforcing or balancing layer made of a non-metallic material is mounted to the face of the substrate board in at least one local zone free of the face which is free of metal portions of the electrical connection network.

Abstract translation: 基板包括在其表面上的电连接网络。 集成电路芯片安装到与电连接网络电接触的基板的表面。 由非金属材料制成的局部增强或平衡层在至少一个不具有电连接网络的金属部分的表面的局部区域中安装到基板的表面上。