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    Method of making multi-layer circuit
    42.
    发明授权
    Method of making multi-layer circuit 失效
    制作多层电路的方法

    公开(公告)号：US5640761A

    公开(公告)日：1997-06-24

    申请号：US478420

    申请日：1995-06-07

    Applicant: Thomas H. DiStefano ,  Igor Y. Khandros ,  Gary W. Grube

    Inventor： Thomas H. DiStefano ,  Igor Y. Khandros ,  Gary W. Grube

    IPC: H01L21/48 ,  H01L23/538 ,  H05K1/00 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  H05K3/36

    CPC classification number: H05K3/462 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5385 ,  H01R12/523 ,  H05K1/0287 ,  H05K1/029 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0298 ,  H05K2201/0195 ,  H05K2201/0305 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2201/10666 ,  H05K2203/175 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4623 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: Multilayer circuit assemblies are made by stacking circuit panels having contacts on their top surfaces, through conductors extending between top and bottom surfaces and terminals connected to the bottom end of each through conductor. The terminals and contacts are arranged so that when the panels are stacked the terminals on the bottom of one panel are in alignment with the contacts on the top surface of the immediately underlying panel. The panels are selectively treated on their top and/or bottom surfaces so as to selectively disconnect or connect each contact to a terminal on the bottom surface of the same panel. For example, the top surface of the panel may be selectively etched to disconnect a contact from one through conductor and hence from the associated terminal. The aligned terminals and contacts are nonselectively connected to one another at each interface so that wherever a terminal and contact on adjacent panels are aligned with one another there are connected to one another. This forms composite vertical conductors extending through a plurality of the panels. The selective treatment of the panel top and bottom surfaces provides selective interruptions in the vertical conductors. A circuit panel precursor having the through conductors and methods of making the same are also provided.

    Abstract translation: 多层电路组件通过在其顶表面上具有接触的电路板堆叠，通过在顶表面和底表面之间延伸的导体以及连接到每个贯通导体的底端的端子而制成。 端子和触点被布置成使得当面板堆叠时，一个面板的底部上的端子与紧邻的底板的顶表面上的触点对准。 在其顶表面和/或底表面上选择性地处理这些面板，以便选择性地将每个接触件断开或连接到同一面板的底表面上的端子。 例如，可以选择性地蚀刻面板的顶表面以将接触从一个导体断开，并因此从相关联的端子断开。 对准的端子和触点在每个接口处彼此非选择性地连接，使得相邻面板上的端子和触点彼此对准的位置彼此连接。 这形成延伸穿过多个面板的复合垂直导体。 面板顶部和底部表面的选择性处理在垂直导体中提供选择性的中断。 还提供了具有贯通导体的电路板前体及其制造方法。

    Multi-layer circuit construction methods and structures with customization features and components for use therein
    43.
    发明授权
    Multi-layer circuit construction methods and structures with customization features and components for use therein 失效
    多层电路构造方法和结构，具有用于其中的定制特征和组件

    公开(公告)号：US5583321A

    公开(公告)日：1996-12-10

    申请号：US443706

    申请日：1995-05-15

    Applicant: Thomas H. DiStefano ,  Igor Y. Khandros ,  Gary W. Grube

    Inventor： Thomas H. DiStefano ,  Igor Y. Khandros ,  Gary W. Grube

    IPC: H01L21/48 ,  H01L23/538 ,  H05K1/00 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  H05K1/02

    CPC classification number: H05K3/462 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5385 ,  H01R12/523 ,  H05K1/0287 ,  H05K1/029 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0298 ,  H05K2201/0195 ,  H05K2201/0305 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2201/10666 ,  H05K2203/175 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4623 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: Multilayer circuit assemblies are made by stacking circuit panels having contacts on their top surfaces, through conductors extending between top and bottom surfaces and terminals connected to the bottomend of each through conductor. The terminals and contacts are arranged so that when the panels are stacked the terminals on the bottom of one panel are in alignment with the contacts on the top surface of the immediately underlying panel. The panels are selectively treated on their top and/or bottom surfaces so as to selectively disconnect or connect each contact to a terminal on the bottom surface of the same panel. For example, the top surface of the panel may be selectively etched to disconnect a contact from one through conductor and hence from the associated terminal. The aligned terminals and contacts are nonselectively connected to one another at each interface so that wherever a terminal and contact on adjacent panels are aligned with one another there are connected to one another. This forms composite vertical conductors extending through a plurality of the panels. The selective treatment of the panel top and bottom surfaces provides selective interruptions in the vertical conductors. A circuit panel precursor having the through conductors and methods of making the same are also provided.

    Abstract translation: 多层电路组件通过在其顶表面上堆叠具有触点的电路板，通过在顶表面和底表面之间延伸的导体以及连接到每个贯通导体的底端的端子而形成。 端子和触点被布置成使得当面板堆叠时，一个面板的底部上的端子与紧邻的底板的顶表面上的触点对准。 在其顶表面和/或底表面上选择性地处理这些面板，以便选择性地将每个接触件断开或连接到同一面板的底表面上的端子。 例如，可以选择性地蚀刻面板的顶表面以将接触从一个导体断开，并因此从相关联的端子断开。 对准的端子和触点在每个接口处彼此非选择性地连接，使得相邻面板上的端子和触点彼此对准的位置彼此连接。 这形成延伸穿过多个面板的复合垂直导体。 面板顶部和底部表面的选择性处理在垂直导体中提供选择性的中断。 还提供了具有贯通导体的电路板前体及其制造方法。

    Multi-Layer circuit construction method and structure
    44.
    发明授权
    Multi-Layer circuit construction method and structure 失效
    多层电路构造方法与结构

    公开(公告)号：US5570504A

    公开(公告)日：1996-11-05

    申请号：US393165

    申请日：1995-02-21

    Applicant: Thomas H. DiStefano ,  Igor Y. Khandros ,  Gary W. Grube

    Inventor： Thomas H. DiStefano ,  Igor Y. Khandros ,  Gary W. Grube

    IPC: H01L21/48 ,  H01L23/538 ,  H05K1/00 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  H05K3/36

    CPC classification number: H05K3/462 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5385 ,  H01R12/523 ,  H05K1/0287 ,  H05K1/029 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0298 ,  H05K2201/0195 ,  H05K2201/0305 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09609 ,  H05K2201/09945 ,  H05K2201/10378 ,  H05K2201/10666 ,  H05K2203/175 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4623 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: Multilayer circuit assemblies are made by stacking circuit panels having contacts on their top surfaces, through conductors extending between top and bottom surfaces and terminals connected to the bottomend of each through conductor. The terminals and contacts are arranged so that when the panels are stacked the terminals on the bottom of one panel are in alignment with the contacts on the top surface of the immediately underlying panel. The panels are selectively treated on their top and/or bottom surfaces so as to selectively disconnect or connect each contact to a terminal on the bottom surface of the same panel. For example, the top surface of the panel may be selectively etched to disconnect a contact from one through conductor and hence from the associated terminal. The aligned terminals and contacts are nonselectively connected to one another at each interface so that wherever a terminal and contact on adjacent panels are aligned with one another there are connected to one another. This forms composite vertical conductors extending through a plurality of the panels. The selective treatment of the panel top and bottom surfaces provides selective interruptions in the vertical conductors. A circuit panel precursor having the through conductors and methods of making the same are also provided.

    Abstract translation: 多层电路组件通过在其顶表面上堆叠具有触点的电路板，通过在顶表面和底表面之间延伸的导体以及连接到每个贯通导体的底端的端子而形成。 端子和触点被布置成使得当面板堆叠时，一个面板的底部上的端子与紧邻的底板的顶表面上的触点对准。 在其顶表面和/或底表面上选择性地处理这些面板，以便选择性地将每个接触件断开或连接到同一面板的底表面上的端子。 例如，可以选择性地蚀刻面板的顶表面以将接触从一个导体断开，并因此从相关联的端子断开。 对准的端子和触点在每个接口处彼此非选择性地连接，使得相邻面板上的端子和触点彼此对准的位置彼此连接。 这形成延伸穿过多个面板的复合垂直导体。 面板顶部和底部表面的选择性处理在垂直导体中提供选择性的中断。 还提供了具有贯通导体的电路板前体及其制造方法。

    Electrical connections with shaped contacts
    45.
    发明授权
    Electrical connections with shaped contacts 失效
    与成型触点的电气连接

    公开(公告)号：US5354205A

    公开(公告)日：1994-10-11

    申请号：US51598

    申请日：1993-04-23

    Applicant: Haim Feigenbaum ,  William R. Crumly ,  Christopher M. Schreiber

    Inventor： Haim Feigenbaum ,  William R. Crumly ,  Christopher M. Schreiber

    IPC: G01R1/073 ,  G01R31/02 ,  H01H1/14 ,  H01L21/66 ,  H01R12/00 ,  H05K1/11 ,  H05K3/20 ,  H05K3/32 ,  H05K3/36 ,  H05K3/40 ,  H01R9/09

    CPC classification number: G01R1/073 ,  H05K3/205 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/10666 ,  H05K2203/0113 ,  H05K2203/0152 ,  H05K2203/0726 ,  H05K2203/167 ,  H05K3/365 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49158

    Abstract: Shaped contacts (40,42) for interconnecting circuits or for use in an integrated circuit test probe are electroplated as integral parts of circuit traces (34) upon a stainless steel mandrel (10). A shaped, hardened steel indentation tool (16,18,26,28) makes indentations (24a,24b) of predetermined shape in the surface of the mandrel (10), which is provided with a pattern of dielectric, such as Teflon (12), or photoresist. Areas of the steel mandrel, including the indentations (24a,24b), are electroplated with a pattern of conductive material (34,36,38), and a dielectric substrate (32) is laminated to the conductive material. The circuit features formed by the indentations define raised contacts of a conical (18) or pyramidal (28) shape, having free ends with a small area that allows higher pressures to be applied to a surface against which the contacts are pressed. This enables the contacts to penetrate foreign materials, such as oxides, that may form on the surface of the pads (56,58), to which the contacts are to be connected to ensure a good contact without any need for wiping action. The projecting contacts can also be pressed into plated holes (82,84) in a substrate, such as a printed wiring board, to which mateable/demateable electrical connection is to be made.

    Abstract translation: 用于互连电路或用于集成电路测试探针的成形触头（40,42）作为电路迹线（34）作为不锈钢芯棒（10）的一部分进行电镀。 成型的硬化钢压痕工具（16,18,26,28）在心轴（10）的表面中形成具有预定形状的凹部（24a，24b），其设置有电介质图案，例如特氟隆（12） ）或光致抗蚀剂。 包括凹陷（24a，24b）的钢心轴的区域用导电材料（34,36,38）的图案电镀，并且电介质基底（32）层压到导电材料上。 由凹口形成的电路特征限定了锥形（18）或金字塔形（28）形状的凸起接触，其具有小的面积的自由端，允许更高的压力施加到触点抵靠的表面。 这使得触点能够渗透可能形成在焊盘（56,58）的表面上的诸如氧化物的异物，触点将被连接到其上，以确保良好的接触而不需要擦拭动作。 突出的触点也可以被压入到将要制造可配对/可分离的电连接的基板（例如印刷电路板）中的电镀孔（82,84）中。

    Semi-additive circuitry with raised features using formed mandrels
    47.
    发明授权
    Semi-additive circuitry with raised features using formed mandrels 失效
    具有凸起特征的半添加电路使用形成的心轴

    公开(公告)号：US5207887A

    公开(公告)日：1993-05-04

    申请号：US753400

    申请日：1991-08-30

    Applicant: William R. Crumly ,  Christopher M. Schreiber ,  David B. Swarbrick

    Inventor： William R. Crumly ,  Christopher M. Schreiber ,  David B. Swarbrick

    IPC: B28B7/28 ,  G01R1/073 ,  H05K3/20 ,  H05K3/36 ,  H05K3/40

    CPC classification number: G01R1/073 ,  H05K3/205 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/10666 ,  H05K2203/0113 ,  H05K2203/0152 ,  H05K2203/0726 ,  H05K2203/167 ,  H05K3/365

    Abstract: A circuit is produced by using a formed mandrel (10,12) and semi-additive techniques for creating circuit traces. A stainless steel mandrel (10) flash plated with copper (14) includes a depression (12) which will form a raised interconnection feature (24). Using a photolithographically formed pattern of photoresistive material (16) on the mandrel the selected pattern of circuit traces (18,20) and raised features (24) are electroplated onto the flash plated mandrel. After stripping the photoresist (16), a dielectric substrate (26) is laminated to the circuit traces, effectively encapsulating the traces on three sides. After removing the laminated circuit traces and dielectric from the mandrel the flash plated copper (14) is removed and the circuit covered with an insulation coverlay.

    Abstract translation: 通过使用形成的心轴（10,12）和用于产生电路迹线的半添加技术来生产电路。 用铜（14）闪镀的不锈钢心轴（10）包括将形成升高的互连特征（24）的凹陷（12）。 使用在心轴上的光致抗蚀剂材料（16）的光刻形成图案，将电路迹线（18,20）和凸起特征（24）的选定图案电镀到闪光电镀心轴上。 在剥离光致抗蚀剂（16）之后，电介质衬底（26）被层压到电路迹线上，有效地将迹线封装在三面上。 在从心轴上去除叠层电路迹线和电介质后，去除闪镀铜（14），并且电路覆盖有绝缘覆盖层。

    Method of making thin film laminate printed circuit
    49.
    发明授权
    Method of making thin film laminate printed circuit 失效
    制造薄膜层压印刷电路的方法

    公开(公告)号：US5074035A

    公开(公告)日：1991-12-24

    申请号：US382718

    申请日：1989-07-19

    Applicant: John C. Tyznik

    Inventor： John C. Tyznik

    IPC: F42B3/12 ,  H05K1/00 ,  H05K3/00 ,  H05K3/40 ,  H05K3/46

    CPC classification number: H05K3/4635 ,  F42B3/124 ,  H05K3/007 ,  H05K3/4617 ,  H05K1/0393 ,  H05K2201/0305 ,  H05K2201/0355 ,  H05K2201/09536 ,  H05K2201/10666 ,  H05K2203/0156 ,  H05K2203/063 ,  H05K2203/066 ,  H05K3/4038 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49158

    Abstract: Method of making a multilayer printed circuit including one or more thin film laminates having a circuit etched thereon without tearing, bending, or wrinkling the laminate during fabrication and which allows the use of standard multilayer etching and registration processes. The method involves the application of a low melting point plastic adhesive to a temporary backing for adhering a thin film laminate to the backing for etching and registration. A high melting point adhesive is then used to laminate an inner layer assembly to the thin film laminate/temporary backing assembly and the temporary backing removed by heating to the melting point of the plastic adhesive. The method can be used to make multilayer printed circuits or a circuit for a blasting cap for initiating the explosion of a secondary explosive.

    Abstract translation: 制造多层印刷电路的方法，该多层印刷电路包括一个或多个薄膜层压板，其中在其上蚀刻了电路，而不会在制造过程中撕裂，弯曲或起皱层压板，并且允许使用标准的多层蚀刻和配准工艺。 该方法涉及将低熔点塑料粘合剂施加到临时背衬上，以将薄膜层压体粘附到背衬上用于蚀刻和配准。 然后使用高熔点粘合剂将内层组件层压到薄膜层压体/临时衬垫组件上，并且通过加热到塑料粘合剂的熔点去除临时衬垫。 该方法可用于制造多层印刷电路或用于爆炸帽的电路，用于引发二次爆炸物的爆炸。

    Method of forming solder terminals for a pinless ceramic module
    50.
    发明授权
    Method of forming solder terminals for a pinless ceramic module 失效
    形成无引脚陶瓷模块焊接端子的方法

    公开(公告)号：US4830264A

    公开(公告)日：1989-05-16

    申请号：US106094

    申请日：1987-10-07

    Applicant: Alexis Bitaillou ,  Michel Grandguillot

    Inventor： Alexis Bitaillou ,  Michel Grandguillot

    IPC: H01L21/48 ,  H01L21/60 ,  H05K1/03 ,  H05K3/34 ,  H05K3/40

    CPC classification number: H05K3/3478 ,  H01L21/4853 ,  H01L21/486 ,  H01L2224/11334 ,  H01L2924/15311 ,  H05K1/0306 ,  H05K2201/09572 ,  H05K2201/10666 ,  H05K2201/10734 ,  H05K2203/041 ,  H05K2203/043 ,  H05K2203/0485 ,  H05K3/3489

    Abstract: Disclosed is a method of forming solder terminals for a pinless module, preferably for a pinless metallized ceramic module. The method is comprised of the following steps: forming a substrate having a pattern of conductors formed onto its top surface and preformed via-holes extending from the top to bottom surface; applying a droplet of flux at at least one of said preformed via-hole openings of the bottom surface of said substrate to fill said via-holes with flux by capillarity and form a glob of flux at the bottom openings; applying a solder preform, i.e. solder balls on each glob of flux to which it will adhere, the volume of the preform being substantially equal to the inner volume of the via hole plus the volume of the bump to be formed; heating to cause solder reflow of the solder preform to fill the via-hole and the inner volume of the eyelet with solder; and, cooling below the melting point of the solder so that the molten solder solidifies to form solder terminals at the via-hole locations while forming solder columns in the via-holes. The resultant pinless metallized ceramic module has connections between the I/O's of the module interfacing with the next level of packaging, (i.e., printed circuit boards), that consist of integral solder terminals. Each integral solder terminal comprises a column in the vias of the metallized ceramic substrate, a mound of solder at the top surface of the substrate and spherical solder bumps on the bottom level for making interconnections with the next level of packaging.

    Abstract translation: 公开了一种形成无针模块的焊接端子的方法，优选地用于无针金属化陶瓷模块。 该方法包括以下步骤：形成具有形成在其顶表面上的导体图案的基底和预先形成的从顶部到底面延伸的通孔; 在所述衬底的底表面的至少一个所述预制通孔开口处施加液滴以通过毛细管作用填充所述通孔，并在底部开口处形成焊剂球; 将焊料预制件（即，将要粘附到其上的焊剂球上的焊球）施加到预成型件的体积上，其大体上等于通孔的内部容积加上待形成的凸块的体积; 加热以使焊料预制件的焊料回流以焊料填充孔眼和孔的内部体积; 并且冷却到低于焊料的熔点，使得熔融焊料在通孔位置处固化以形成焊接端子，同时在通孔中形成焊料柱。 所得到的无引脚金属化陶瓷模块具有与由整体焊接端子组成的下一级封装（即，印刷电路板）的模块的I / O之间的连接。 每个整体焊接端子包括在金属化陶瓷衬底的通孔中的柱，在衬底的顶表面上的焊料堆，以及底层上的球形焊料凸块，用于与下一级封装相互连接。

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