公开(公告)号：US20160078952A1

公开(公告)日：2016-03-17

申请号：US14943035

申请日：2015-11-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Kuo-Yi Cheng

IPC: G11C16/14 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C11/5642 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/26 ,  H01L27/11582 ,  H01L29/7926

Abstract: A NAND flash memory unit, an operating method and a reading method are provided. The NAND flash memory unit includes a plurality of gate layers, a tunnel layer, a charge trapping layer, a conductor layer and a second dielectric layer. A first dielectric layer is included between two adjacent gate layers among the gate layers. The tunnel layer, the charge trapping layer, the conductor layer, and the second dielectric layer penetrate the gate layers. The charge trapping layer is disposed between the tunnel layer and the gate layers, and the second dielectric layer is disposed between the conductor layer and the tunnel layer. Therefore, an erasing speed may be increased; the charge trapping layer may be repaired; the controllability of the gate layers may be increased.

Abstract translation: 提供NAND闪存单元，操作方法和读取方法。 NAND闪存单元包括多个栅极层，隧道层，电荷俘获层，导体层和第二介电层。 在栅极层之间的两个相邻栅极层之间包括第一介电层。 隧道层，电荷俘获层，导体层和第二介电层穿透栅极层。 电荷捕获层设置在隧道层和栅极层之间，第二介电层设置在导体层和隧道层之间。 因此，可以增加擦除速度; 电荷捕获层可以被修复; 可以提高栅极层的可控性。

公开(公告)号：US20150193204A1

公开(公告)日：2015-07-09

申请号：US14203584

申请日：2014-03-11

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Siu-Tung Lam

IPC: G06F7/58

CPC classification number: G06F7/588

Abstract: A method for generating a random number, a memory storage device and a control circuit are provided. The method includes: writing data into a plurality of memory cells; reading at least one of the memory cells repeatedly according to a first read voltage to obtain a plurality of sensing currents; and generating the random number according to the sensing currents.

Abstract translation: 提供了一种产生随机数的方法，存储器存储装置和控制电路。 该方法包括：将数据写入到多个存储单元中; 根据第一读取电压重复读取至少一个存储器单元以获得多个感测电流; 并根据感​​测电流产生随机数。

公开(公告)号：US09007829B2

公开(公告)日：2015-04-14

申请号：US13778055

申请日：2013-02-26

Applicant: Phison Electronics Corp.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Kuo-Yi Cheng ,  Chun-Yen Chang

IPC: G11C29/04 ,  G11C29/00 ,  G11C16/14 ,  G11C16/34

CPC classification number: G11C29/82 ,  G11C16/14 ,  G11C16/349 ,  G11C29/04 ,  G11C2029/0409

Abstract: A memory repairing method for a rewritable non-volatile memory module and a memory controller and a memory storage apparatus are provided. The method includes monitoring a wear degree of the rewritable non-volatile memory module; determining whether the wear degree of the rewritable non-volatile memory module is larger than a threshold; and heating the rewritable non-volatile memory module such that the temperature of the rewritable non-volatile memory module lies in between 100° C.˜600° C. if the wear degree of the rewritable non-volatile memory module is larger than the threshold. Accordingly, deteriorated memory cells in the rewritable non-volatile memory module can be repaired, thereby preventing data loss.

Abstract translation: 提供了一种用于可重写非易失性存储器模块和存储器控制器和存储器存储装置的存储器修复方法。 该方法包括监视可重写非易失性存储器模块的磨损程度; 确定可重写非易失性存储器模块的磨损程度是否大于阈值; 并且加热可重写非易失性存储器模块，使得可重写非易失性存储器模块的温度在100℃至600℃之间，如果可重写非易失性存储器模块的磨损程度大于阈值 。 因此，可以修复可重写非易失性存储器模块中的劣化的存储单元，从而防止数据丢失。

公开(公告)号：US20140160844A1

公开(公告)日：2014-06-12

申请号：US13778055

申请日：2013-02-26

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Kuo-Yi Cheng ,  Chun-Yen Chang

IPC: G11C29/04 ,  G11C16/14

CPC classification number: G11C29/82 ,  G11C16/14 ,  G11C16/349 ,  G11C29/04 ,  G11C2029/0409

Abstract: A memory repairing method for a rewritable non-volatile memory module and a memory controller and a memory storage apparatus are provided. The method includes monitoring a wear degree of the rewritable non-volatile memory module; determining whether the wear degree of the rewritable non-volatile memory module is larger than a threshold; and heating the rewritable non-volatile memory module such that the temperature of the rewritable non-volatile memory module lies in between 100° C.˜600° C. if the wear degree of the rewritable non-volatile memory module is larger than the threshold. Accordingly, deteriorated memory cells in the rewritable non-volatile memory module can be repaired, thereby preventing data loss.

Abstract translation: 提供了一种用于可重写非易失性存储器模块和存储器控制器和存储器存储装置的存储器修复方法。 该方法包括监视可重写非易失性存储器模块的磨损程度; 确定可重写非易失性存储器模块的磨损程度是否大于阈值; 并且加热可重写非易失性存储器模块，使得可重写非易失性存储器模块的温度在100℃至600℃之间，如果可重写非易失性存储器模块的磨损程度大于阈值 。 因此，可以修复可重写非易失性存储器模块中的劣化的存储单元，从而防止数据丢失。

公开(公告)号：US20240304235A1

公开(公告)日：2024-09-12

申请号：US18301275

申请日：2023-04-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Po-Hao Chen ,  Po-Cheng Su ,  Shih-Jia Zeng ,  Yu-Cheng Hsu ,  Wei Lin

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C11/409 ,  G06F3/0679 ,  G11C16/26

Abstract: A voltage calibration method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: reading first data from a first physical unit using a first read voltage level and reading second data from at least one second physical unit using a second read voltage level; obtaining count information reflecting a total number of memory cells meeting a default condition in the first physical unit and the at least one second physical unit according to the first data and the second data; and calibrating the first read voltage level according to the count information.

公开(公告)号：US20240201857A1

公开(公告)日：2024-06-20

申请号：US18168573

申请日：2023-02-14

Applicant: Phison Electronics Corp.

Inventor： Po-Cheng Su ,  Yu-Cheng Hsu ,  Wei Lin

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0679

Abstract: A decoding method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending at least one read command sequence instructing to read a first physical unit in a rewritable non-volatile memory module; receiving response data from the rewritable non-volatile memory module, wherein the response data includes a plurality of identification bits, and the plurality of identification bits reflect a voltage variation of a first bit line where a first memory cell in the first physical unit is located during a discharge process; determining a decoding parameter corresponding to the first memory cell according to the plurality of identification bits; and decoding data read from the first memory cell according to the decoding parameter.

公开(公告)号：US20230071724A1

公开(公告)日：2023-03-09

申请号：US17498771

申请日：2021-10-12

Applicant: PHISON ELECTRONICS CORP.

Inventor： Jia-Fan Chien ,  Wei Lin ,  Yu-Cheng Hsu ,  Yu-Siang Yang

IPC: G06F3/06 ,  G06F11/30

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes: detecting a first temperature status of a rewritable non-volatile memory module; performing a first write operation on a first physical unit under the first temperature status to store first data to the first physical unit; after performing the first write operation, detecting a second temperature status of the rewritable non-volatile memory module; in response to the first temperature status and the second temperature status meeting a first condition, performing a data refresh operation on the first physical unit under the second temperature status to re-store the first data to a second physical unit different from the first physical unit.

公开(公告)号：US20220342547A1

公开(公告)日：2022-10-27

申请号：US17349918

申请日：2021-06-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Siang Yang ,  Yu-Cheng Hsu ,  Tsai-Hao Kuo ,  Wei Lin ,  An-Cheng Liu

IPC: G06F3/06

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes: reading first data from a first physical unit by using a first read voltage level according to first management information among multiple candidate management information; decoding the first data and recording first error bit information of the first data; and adjusting sorting information related to the candidate management information according to the first error bit information. The sorting information reflects a usage order of the candidate management information in a decoding operation.

公开(公告)号：US10679707B2

公开(公告)日：2020-06-09

申请号：US16120313

申请日：2018-09-03

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Tsai-Hao Kuo ,  Szu-Wei Chen ,  Lih Yuarn Ou ,  Hsiao-Yi Lin

IPC: G06F3/01 ,  G11C16/26 ,  G06F11/10 ,  G11C29/52 ,  G06F3/06 ,  G11C16/04 ,  G11C11/56

Abstract: A voltage adjusting method, a memory controlling circuit unit and a memory storage device are provided. The method includes: reading a first physical programming unit in a first physical programming unit group to obtain first data; correcting the first data according to a first error check and correction code corresponding to the first data to obtain first corrected data; reading a second physical programming unit in the first physical programming unit group to obtain second data; and adjusting a first read voltage for reading a first memory cell to a second read voltage according to the first data, the first corrected data, and the second data.

公开(公告)号：US10586596B2

公开(公告)日：2020-03-10

申请号：US15412065

申请日：2017-01-23

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Szu-Wei Chen

IPC: G06F12/00 ,  G11C16/10 ,  G11C16/04 ,  G11C29/00 ,  G11C11/56 ,  G11C16/08 ,  G11C7/10 ,  G06F3/06

Abstract: A data writing method for a rewritable non-volatile memory module having a plurality of physical erasing units and a memory control circuit unit and a memory storage apparatus using the same are provided. Each of the physical erasing units has a plurality of physical programming unit sets, and each of the physical programming unit sets has a plurality of physical programming unit. The method includes receiving data and arranging the data to generate a first data stream and a second data stream. The method also includes encoding the first data stream and the second data stream to generate a third data stream, and issuing a programming command sequence to write the first data stream, the second data stream and the third data stream respectively into a first physical programming unit, a second physical programming unit and a third physical programming unit of a physical programming unit set.