公开(公告)号：US20230342088A1

公开(公告)日：2023-10-26

申请号：US18345759

申请日：2023-06-30

Applicant: Microsoft Technology Licensing, LLC

Inventor： Peng LI

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201

Abstract: Systems, methods, and devices are described for writing to a solid-state drive (SSD) that includes a non-volatile memory device, the volatile memory device includes first and second memory regions, the first memory region storing an address mapping table. A write request that includes a host logic block address (LBA) and data is received. A determination of whether the received LBA corresponds to the non-volatile memory device or the second memory region is made. In response to the received LBA corresponding to the non-volatile memory device, a physical address of the non-volatile memory device corresponding to the received LBA is determined based on the address mapping table and the included data is written to the determined physical address of the non-volatile memory device. In response to the received LBA corresponding to the second memory region, the included data is written to the second memory region based on the received LBA.

公开(公告)号：US11789860B2

公开(公告)日：2023-10-17

申请号：US17694470

申请日：2022-03-14

Applicant: Western Digital Technologies, Inc.

Inventor： Amir Hossein Gholamipour ,  Mark David Myran ,  Chandan Mishra ,  Namhoon Yoo ,  Jun Tao

IPC: G06F11/00 ,  G06F12/00 ,  G06F12/02 ,  G06F11/14 ,  G06F12/0804

CPC classification number: G06F12/0246 ,  G06F11/1441 ,  G06F11/1471 ,  G06F12/0804 ,  G06F2201/81 ,  G06F2201/84 ,  G06F2212/1024 ,  G06F2212/7201 ,  G06F2212/7203

Abstract: Disclosed are systems and methods for providing logical to physical (L2P) table management using low-latency NVM to reduce solid state drive (SSD) random access memory (RAM) footprint. A method includes determining a logical to physical (L2P) mapping of a logical address to a physical address in a flash storage, for an operation directed to the logical address. The method also includes adding a data entry, comprising the L2P mapping, to an open journal structure in RAM. The method also includes adding a log entry, comprising the L2P mapping, to a buffer in the RAM. The method also includes flushing the buffer to a low-latency NVM storage in response to determining that the buffer has satisfied a size threshold. Reads, snapshotting and L2P table recovery are also described.

公开(公告)号：US20230325242A1

公开(公告)日：2023-10-12

申请号：US18333752

申请日：2023-06-13

Applicant: SAP SE

Inventor： Daniel Booss ,  Robert Kettler

IPC: G06F9/50 ,  G06F12/0882 ,  G06F9/4401 ,  G06N20/00

CPC classification number: G06F9/5016 ,  G06F12/0882 ,  G06F9/4418 ,  G06F2212/7201 ,  G06N20/00 ,  G06F9/5022 ,  G06F2209/5018 ,  G06F9/442

Abstract: A system for shutting down a process of a database is provided. In some aspects, the system performs operations including tracking, during startup of a process, code locations of a process in the at least one memory. The operations may further include tracking, during runtime of the process and in response to the tracking the code locations, memory segments of the at least one memory allocated to the process. The operations may further include receiving an indication for a shutdown of a process. The operations may further include waking, in response to the indication, at least one processing thread of a plurality of processing threads allocated to a database system. The operations may further include allocating a list of memory mappings to the plurality of processing threads. The operations may further include freeing, by the first processing thread, the physical memory assigned to the processing thread by the memory mappings.

公开(公告)号：US20230315621A1

公开(公告)日：2023-10-05

申请号：US17707538

申请日：2022-03-29

Applicant: NVIDIA Corporation

Inventor： Shirish Bahirat

IPC: G06F12/02 ,  G06F12/1045 ,  G06F9/455

CPC classification number: G06F12/0238 ,  G06F12/0292 ,  G06F12/1054 ,  G06F12/1063 ,  G06F9/45558 ,  G06F2009/45583 ,  G06F2212/7201

Abstract: Apparatuses, systems, and techniques to allocate portions of a virtual address space to allow virtual machines to share data. In at least one embodiment, at least a portion of a virtual memory address space is made accessible to multiple virtual machines and is mapped to memory addresses of different physical devices using, at least in part, a cache-coherent protocol.

公开(公告)号：US20230315294A1

公开(公告)日：2023-10-05

申请号：US18329446

申请日：2023-06-05

Applicant: Kioxia Corporation

Inventor： Hideki Yoshida ,  Shinichi Kanno

IPC: G06F3/06 ,  G06F12/1009 ,  G06F12/02

CPC classification number: G06F3/061 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0658 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1036 ,  G06F2212/2022 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2212/7207 ,  G06F2212/7208

Abstract: According to one embodiment, when receiving a write request to designate a first block number and a first logical address from a host, a memory system determines a first location in a first block having the first block number, to which data from the host is to be written, and writes the data from the host to the first location of the first block. The memory system updates a first address translation table managing mapping between logical addresses and in-block physical addresses of the first block, and maps a first in-block physical address indicative of the first location to the first logical address.

公开(公告)号：US11775464B2

公开(公告)日：2023-10-03

申请号：US17018808

申请日：2020-09-11

Applicant: Jonathan Glickman

Inventor： Jonathan Glickman

IPC: G06F13/40 ,  G06F12/02 ,  G06F13/16 ,  G06F13/42 ,  G06F13/28

CPC classification number: G06F13/4027 ,  G06F12/0246 ,  G06F13/1694 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4282 ,  G06F2212/7201

Abstract: A computer system is provided. The computer system includes a hub board, a common bus, and a plurality of Sibling boards. The hub board has an I/O controller hub, which includes a main communication chipset. The plurality of Sibling boards is coupled to the hub board by the common bus. Each of the Sibling boards includes a memory and at least one CPU. The memory is operative to host a Sibling operating system. The CPU is coupled to the memory. The Southbridge type chipset which resides in the hub board is shared amongst the plurality of Sibling boards. At least one of the plurality of Sibling boards functions as a master processing unit of the system. Sibling boards offer processing flexibility through the means of how they are configured in the system.

公开(公告)号：US20230289285A1

公开(公告)日：2023-09-14

申请号：US18200975

申请日：2023-05-23

Applicant: Micron Technology, Inc.

Inventor： Byron Harris ,  Daniel Boals ,  Abedon Madril

IPC: G06F12/02 ,  G06F12/0891 ,  G06F1/30 ,  G06F12/0804

CPC classification number: G06F12/0246 ,  G06F12/0891 ,  G06F12/0292 ,  G06F1/30 ,  G06F12/0804 ,  G06F2212/7201

Abstract: A journal count reflecting a number of logical-to-physical (L2P) journals written to a non-volatile memory device is maintained, wherein each L2P journal is associated with one or more updates to an L2P address mapping table. In response to determining that the journal count satisfies a threshold criterion, a first section of a plurality of sections of the L2P address mapping table is identified, wherein the plurality of sections of the L2P address mapping table is cached in a volatile memory device. The first section of the L2P address mapping table is written to the non-volatile memory device.

公开(公告)号：US20230289091A1

公开(公告)日：2023-09-14

申请号：US17693431

申请日：2022-03-14

Applicant: Silicon Motion, Inc.

Inventor： Yi-Kai Pai

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0656 ,  G06F3/0659 ,  G06F3/0631 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0238 ,  G06F2212/7201

Abstract: A method of caching mapping table for use in a flash memory device having a flash memory controller and a flash memory is provided. The method includes: in response to a host read command, determining whether a group of a logical-to-physical (L2P) required by handling the host read command has been loaded to a DRAM of the flash memory controller; if the required group of the L2P mapping table has not been loaded to the DRAM, loading the required group of the L2P mapping table from the flash memory to a SRAM of the flash memory controller; directly accessing the SRAM to obtain an L2P address associated with the host read command from the required group of the L2P mapping table; and performing a read operation on the flash memory in response to the host read command according to the obtained L2P address.

公开(公告)号：US11755495B2

公开(公告)日：2023-09-12

申请号：US17202983

申请日：2021-03-16

Applicant: Micron Technology, Inc.

Inventor： Sanjay Subbarao

IPC: G06F12/10 ,  G06F12/1009 ,  G11C16/04 ,  G06F12/0815 ,  G11C14/00 ,  G11C11/56

CPC classification number: G06F12/1009 ,  G06F12/0815 ,  G11C16/0483 ,  G06F2212/7201 ,  G11C11/56 ,  G11C14/0018

Abstract: A processing device receives a request specifying a logical address associated with a host-initiated operation directed at a first portion of a memory device. The processing device accesses a second L2P table comprising a mapping between logical addresses and physical addresses in a second portion of the memory device. A physical location within the second portion of the memory device is identified based on the second L2P table. The physical location corresponds to a portion of a first L2P table that specifies a physical address within the first portion of the memory device that corresponds to the logical address. The physical address is identified based on the portion of the first L2P table and the host-initiated operation is performed at the physical address.

公开(公告)号：US20230281134A1

公开(公告)日：2023-09-07

申请号：US18187092

申请日：2023-03-21

Applicant: Intel Corporation

Inventor： Zhaojuan Bian ,  Kebing Wang

IPC: G06F12/1045 ,  G06F12/06 ,  G06F12/02 ,  G06F12/0871 ,  G06F12/0882

CPC classification number: G06F12/1045 ,  G06F12/0653 ,  G06F12/0246 ,  G06F12/0871 ,  G06F12/0882 ,  G06F2212/7201

Abstract: Embodiments described herein provide an apparatus comprising a processor to reserve a block of physical memory communicatively coupled to a processor, allocate a first portion of the block of physical memory for use with one or more processes executing on the processor, the first portion configured as a single memory page having a first page size, and in response to a determination that an amount of physical memory required by the one or more processes executing on the processor exceeds a first threshold allocate additional memory to the first portion of the block of physical memory, and increase the single memory page from a first page size to a second page size. Other embodiments may be described and claimed.