公开(公告)号：US11935776B2

公开(公告)日：2024-03-19

申请号：US17175315

申请日：2021-02-12

Applicant: Lam Research Corporation

Inventor： Christopher Kimball ,  Keith Gaff ,  Feng Wang

IPC: H01L21/683 ,  H01J37/00 ,  H01J37/32 ,  H01L21/3065 ,  H01L21/66 ,  H01L21/67 ,  H01L21/687

CPC classification number: H01L21/6833 ,  H01J37/00 ,  H01J37/32082 ,  H01J37/32568 ,  H01J37/32642 ,  H01J37/32697 ,  H01J37/32816 ,  H01L21/3065 ,  H01L21/67069 ,  H01L21/67109 ,  H01L21/67126 ,  H01L21/67248 ,  H01L21/67253 ,  H01L21/6831 ,  H01L21/68735 ,  H01L22/26 ,  H01J2237/334 ,  H01L21/68785

Abstract: A method for electrostatically clamping an edge ring in a plasma processing chamber with an electrostatic ring clamp with at least one ring backside temperature channel for providing a flow of gas to the edge ring is provided. A vacuum is provided to the at least one ring backside temperature channel Pressure in the backside temperature channel is measured. An electrostatic ring clamping voltage is provided when the pressure in the backside temperature channel reaches a threshold maximum pressure. The vacuum to the backside temperature channel is discontinued. Pressure in the backside temperature channel is measured. If pressure in the backside temperature channel rises faster than a threshold rate, then sealing failure is indicated. If pressure in the backside temperature channel does not rise faster than the threshold rate, a plasma process is continued, using the backside temperature channel to regulate a temperature of the edge ring.

公开(公告)号：US20180277406A1

公开(公告)日：2018-09-27

申请号：US15699727

申请日：2017-09-08

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Koji NAKAHARA ,  Tomohisa IINO ,  Ryota FUJITSUKA

IPC: H01L21/67 ,  H01L21/673

CPC classification number: H01L21/67207 ,  C23C16/45546 ,  C23C16/45578 ,  C23C16/4583 ,  H01J37/00 ,  H01L21/67017 ,  H01L21/67253 ,  H01L21/67346

Abstract: According to an embodiment, a substrate treatment apparatus includes a vacuum chamber, a cylindrical member, a gas feed member, a support member and a plurality of plate members. The cylindrical member is disposed in the vacuum chamber and includes a gas outlet. The support member supports a plurality of treated substrates in a stacked state in the cylindrical member. The plurality of plate members are supported on the support member and include a patterned surface or an outer circumferential part outside the treated substrate.

公开(公告)号：US20180261458A1

公开(公告)日：2018-09-13

申请号：US15910463

申请日：2018-03-02

Applicant: TOKYO ELECTRON LIMITED

Inventor： Tatsuya YAMAGUCHI ,  Reiji NIINO ,  Hiroyuki HASHIMOTO ,  Syuji NOZAWA ,  Makoto FUJIKAWA

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/265 ,  H01L21/02 ,  H01L21/67 ,  H01L21/677

CPC classification number: H01L21/0337 ,  H01J37/00 ,  H01L21/02057 ,  H01L21/0271 ,  H01L21/033 ,  H01L21/0332 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/67034 ,  H01L21/67063 ,  H01L21/6715 ,  H01L21/6719 ,  H01L21/67213 ,  H01L21/67703 ,  H01L29/785

Abstract: There is provided a semiconductor device manufacturing method including: forming a first mask film composed of a polymer having a urea bond by supplying a raw material to a surface of the substrate for polymerization; forming a second mask inorganic film to be laminated on the first mask film; forming a pattern on the first mask film and the second mask inorganic film and performing an ion implantation on the surface of the substrate; removing the second mask inorganic film after the ion implantation; and removing the first mask film by heating the substrate after the ion implantation and depolymerizing the polymer.

公开(公告)号：US20180259848A1

公开(公告)日：2018-09-13

申请号：US15909650

申请日：2018-03-01

Applicant: APPLIED MATERIALS, INC.

Inventor： Michael N. GRIMBERGEN ,  Khiem K. NGUYEN

IPC: G03F1/80 ,  H01L21/67 ,  H01L21/66 ,  G03F1/42 ,  G03F1/36 ,  G03F1/22

CPC classification number: G03F1/80 ,  G03F1/22 ,  G03F1/36 ,  G03F1/42 ,  H01J37/00 ,  H01L21/67069 ,  H01L21/67253 ,  H01L22/12 ,  H01L22/26

Abstract: Embodiments include wafer and photomask processing equipment. An etch processing system including an endpoint detection system having a light source and a photodetector is described. In an example, the light source emits light toward an alignment region over a substrate support member of an etch chamber, and the photodetector receives a reflection of the light from the alignment region. The reflection is monitored for endpoint and process control. A second light source emits light toward the alignment region, and a camera receives the light to image the alignment region. The image can be used to align the light emitted by the endpoint detection system to a spot location within the alignment region, e.g., within an alignment opening of a substrate mounted on the substrate support member.

公开(公告)号：US20180240678A1

公开(公告)日：2018-08-23

申请号：US15899422

申请日：2018-02-20

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Akihiro ITOU ,  Atsushi HARIKAI ,  Noriyuki MATSUBARA ,  Shogo OKITA

IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/687 ,  H01L21/78 ,  H01L21/683

CPC classification number: H01L21/30655 ,  H01J37/00 ,  H01J37/32009 ,  H01J37/3244 ,  H01J37/32743 ,  H01L21/31138 ,  H01L21/67109 ,  H01L21/6835 ,  H01L21/68735 ,  H01L21/68742 ,  H01L21/68785 ,  H01L21/78 ,  H01L21/7806 ,  H01L2221/68327

Abstract: Provided is a manufacturing process of an element chip, which comprises a preparation step, a setting step for setting the substrate on a stage, and a plasma-dicing step for dividing the substrate into a plurality of element chips, wherein the plasma-dicing step is achieved by repeatedly implementing etching routines each including an etching step for etching the second layer along the street regions to form a plurality of grooves and a depositing step for depositing a protective film on inner walls of the grooves, wherein the plasma-dicing step includes a first etching step for forming the grooves each having a first scallop on the inner wall thereof at a first pitch, and a second etching step for forming the grooves each having a second scallop on the inner wall thereof at a second pitch, and wherein the second pitch is greater than the first pitch.

公开(公告)号：US20180218890A1

公开(公告)日：2018-08-02

申请号：US15746647

申请日：2016-07-18

Applicant: HONEYWELL INTERNATIONAL INC.

Inventor： John A. DUNLOP ,  Kevin T. HUBERT ,  Jacob C. RUZICKA ,  Andrew N.A. WRAGG ,  Michael D. BLONDELL ,  William P. JARDEE ,  Phillip F. JOHN ,  Edward P. LARA ,  Wayne D. MEYER ,  Adam P. DAUB ,  Scott A. BUCKHART ,  Travis C. JUNTTILA

IPC: H01J37/34 ,  H01F7/06 ,  H01F27/28 ,  C23C14/35

CPC classification number: H01J37/3458 ,  C23C14/34 ,  C23C14/35 ,  H01F7/06 ,  H01F27/28 ,  H01F27/2847 ,  H01J37/00 ,  H01J37/3211 ,  H01J37/32871 ,  H01J37/3438 ,  H01J37/3488

Abstract: A high surface area coil for use with a physical vapor deposition apparatus comprising a first surface. At least a portion of the first surface has a macrotexture with a surface roughness between about 15 μm and about 150 μm. At least a portion of the first surface has a microtexture with a surface roughness between about 2 μm and 15 μm.

公开(公告)号：US20180144903A1

公开(公告)日：2018-05-24

申请号：US15860547

申请日：2018-01-02

Applicant: Lam Research Corporation

Inventor： Fayaz Shaikh

IPC: H01J37/00 ,  C23C16/455 ,  C23C16/505

CPC classification number: H01J37/00 ,  C23C16/45565 ,  C23C16/45587 ,  C23C16/505 ,  H01J37/32091 ,  H01J37/32568 ,  H01J37/32926 ,  H01J37/32935

Abstract: Methods and systems for depositing material layers with gap variation between film deposition operations. One method includes depositing a material layer over a substrate. The depositing is performed in a plasma chamber having a bottom electrode and a top electrode. The method includes providing a substrate over the bottom electrode in the plasma chamber. The method sets a first gap between the bottom and top electrodes and performs plasma deposition to deposit a first film of the material layer over the substrate while the first gap is set between the bottom and top electrodes. The method then sets a second gap between the bottom a top electrodes and performs plasma deposition to deposit a second film of the material layer over the substrate while the second gap is set between the bottom and top electrodes. The material layer is defined by the first and second films and the first gap is varied to the second gap to offset expected non-uniformities when depositing the first film followed by the second film.

公开(公告)号：US09978621B1

公开(公告)日：2018-05-22

申请号：US15351437

申请日：2016-11-14

Applicant: Philip Allan Kraus ,  Timothy Joseph Franklin

Inventor： Philip Allan Kraus ,  Timothy Joseph Franklin

IPC: H01L21/66 ,  H01L21/67 ,  G01H13/00

CPC classification number: H01L21/67253 ,  G01H13/00 ,  H01J37/00 ,  H01L21/67069 ,  H01L21/67155 ,  H01L22/14 ,  H01L22/26

Abstract: Embodiments include a real time etch rate sensor and methods of for using a real time etch rate sensor. In an embodiment, the real time etch rate sensor includes a resonant system and a conductive housing. The resonant system may include a resonating body, a first electrode formed over a first surface of the resonating body, a second electrode formed over a second surface of the resonating body, and a sacrificial layer formed over the first electrode. In an embodiment, at least a portion of the first electrode is not covered by the sacrificial layer. In an embodiment, the conductive housing may secure the resonant system. Additionally, the conductive housing contacts the first electrode, and at least a portion of an interior edge of the conductive housing may be spaced away from the sacrificial layer.

公开(公告)号：US20180050120A1

公开(公告)日：2018-02-22

申请号：US15611098

申请日：2017-06-01

Applicant: Plasmology4, Inc.

Inventor： Emilia M. Kulaga

IPC: A61L2/00 ,  A01N59/16 ,  A01N59/20 ,  A61K41/00 ,  A61K33/24 ,  A61K33/38 ,  A61K33/34 ,  A61N1/44

CPC classification number: A61L2/0011 ,  A01N59/16 ,  A01N59/20 ,  A61K33/00 ,  A61K33/24 ,  A61K33/242 ,  A61K33/243 ,  A61K33/34 ,  A61K33/38 ,  A61K41/00 ,  A61K41/0052 ,  A61L2/0082 ,  A61L2/14 ,  A61L2/18 ,  A61N1/44 ,  B22F1/0044 ,  B22F9/14 ,  B22F2202/13 ,  H01J37/00 ,  H05H1/00 ,  H05H1/46 ,  H05H2001/4682 ,  H05H2001/469 ,  H05H2240/20 ,  H05H2245/124 ,  A61K2300/00

Abstract: A method of forming metal nanoparticles includes applying a substance to an area of interest, applying cold plasma to the area of interest, and synthesizing nanoparticles from the substance using the cold plasma in the area of interest, wherein the substance is a solution that contains metal ions, and the nanoparticles synthesized are metallic in nature.

公开(公告)号：US20180030617A1

公开(公告)日：2018-02-01

申请号：US15641746

申请日：2017-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sam-mook KANG ,  Jun-youn KIM ,  Young-jo TAK ,  Mi-hyun KIM ,  Young-soo PARK

IPC: C30B25/16 ,  C23C16/52 ,  C23C14/54 ,  C23C14/06 ,  C23C16/30 ,  C30B29/40 ,  C30B25/18 ,  C23C14/22

CPC classification number: C30B25/165 ,  C23C14/0617 ,  C23C14/221 ,  C23C14/54 ,  C23C16/01 ,  C23C16/0272 ,  C23C16/303 ,  C23C16/455 ,  C23C16/4585 ,  C23C16/52 ,  C30B25/12 ,  C30B25/14 ,  C30B25/183 ,  C30B29/406 ,  H01J37/00 ,  H01L21/02002 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/68721 ,  H01L21/68735 ,  H01L21/7806

Abstract: An apparatus includes a deposition chamber housing that accommodates a growth substrate, a supply nozzle to supply a deposition gas for forming a target large-size substrate on the growth substrate into the deposition chamber housing, a susceptor to support the growth substrate and expose a rear surface of the growth substrate to an etch gas, and an inner liner connected to the susceptor. The inner liner is to isolate the etch gas from the deposition gas and guide the etch gas toward the rear surface of the growth substrate. The susceptor includes a center hole that exposes the rear surface of the growth substrate and a support protrusion supporting the growth substrate, the support protrusion protruding toward the center of the center hole from an inner sidewall of the susceptor defining the center hole.