公开(公告)号：US07906835B2

公开(公告)日：2011-03-15

申请号：US11837835

申请日：2007-08-13

Applicant: Robert John Romero

Inventor： Robert John Romero

IPC: H01L23/495

CPC classification number: H05K1/111 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H05K3/3436 ,  H05K2201/09227 ,  H05K2201/09381 ,  H05K2201/094 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00014

Abstract: Methods, systems, and apparatuses for ball grid array land patterns are provided. A ball grid array land pattern includes a plurality of land pads and electrically conductive traces. The plurality of land pads is arranged in an array of rows and columns. A perimeter edge of the array includes a pair of adjacent oblong shaped land pads. An electrically conductive trace is routed between the pair of adjacent oblong shaped land pads from a land pad positioned in an interior of the array to a location external to the array. The oblong shaped land pads are narrower than standard round land pads, and thus provide more clearance for the routing of traces. The oblong shaped land pads enable more land pads of the land pattern array to be routed external to the array on each routing layer, and thus can save printed circuit board component and assembly costs.

Abstract translation: 提供了球栅排列图案的方法，系统和装置。 球栅阵列平台图案包括多个焊盘和导电迹线。 多个接地焊盘被布置成行和列的阵列。 阵列的周边边缘包括一对相邻的长方形焊盘。 导电迹线在一对相邻的长方形焊盘之间从位于阵列内部的焊盘传送到阵列外部的位置。 长方形的焊盘比标准的圆形焊盘更窄，从而为迹线的布线提供更多的间隙。 长方形的接地焊盘使得焊盘图案阵列的更多焊盘能够在每个布线层上的阵列外部布线，从而可以节省印刷电路板部件和组装成本。

公开(公告)号：US07906734B2

公开(公告)日：2011-03-15

申请号：US11669070

申请日：2007-01-30

Applicant: Rod Del Rosario ,  John Nguyen ,  Anton Rahardja

Inventor： Rod Del Rosario ,  John Nguyen ,  Anton Rahardja

IPC: H05K1/11

CPC classification number: H05K1/0231 ,  H05K1/023 ,  H05K1/0233 ,  H05K1/114 ,  H05K2201/09381 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10545 ,  H05K2201/10734 ,  Y10T29/4913

Abstract: In one implementation, a PCB having an array of vias and electrical terminals disposed on the side of the PCB opposite the side configured to receive a grid array package are disclosed herein. The array of vias have pads and forms a pattern of repetitive rows and columns. A substantially consistent intervia distance is defined along an intervia axis between each adjacent via in each of the rows and columns. A pair of electrical terminals are positioned adjacent one another along an electrical terminal axis between at least two of the vias and the electrical terminal axis intersects the intervia axis. In another implementation, a group of four adjacent vias form a substantially rectangular shape having one of four vias positioned at each of four corners of the rectangular shape. One electrical terminal is positioned within the four vias without contacting any of the four vias.

Abstract translation: 在一个实施方式中，本文公开了具有布置在PCB侧面上的通孔阵列和电端子的PCB，该PCB配置为接收栅格阵列封装。 通孔阵列具有焊盘并形成重复的行和列的图案。 在每个行和列中的每个相邻通孔之间沿着轴间轴线定义基本一致的距离。 一对电端子沿着电端子轴线彼此相邻地定位在至少两个通孔和电端子轴线之间，与导线轴线相交。 在另一实施方案中，一组四个相邻的通孔形成大致矩形的形状，其具有位于矩形形状的四个角中的每一个的四个通孔中的一个。 一个电气端子位于四个通孔内，而不接触四个通孔中的任何一个。

公开(公告)号：US20110024919A1

公开(公告)日：2011-02-03

申请号：US12841310

申请日：2010-07-22

Applicant: Tae-Gyu Kang ,  Wha-Su Sin ,  Jun-Soo Han

Inventor： Tae-Gyu Kang ,  Wha-Su Sin ,  Jun-Soo Han

IPC: H01L23/488 ,  H05K1/18

CPC classification number: H05K1/111 ,  H01L23/13 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/10253 ,  H05K2201/09381 ,  H05K2201/094 ,  H05K2201/09709 ,  H05K2203/049 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A wiring substrate for a semiconductor chip includes a substrate having a first face and a second face opposite to the first face. The substrate has a window from the first face to the second face that exposes chip pads of a semiconductor chip adherable to the first face. A first bonding pad is arranged on the second face along a side portion of the window. The first bonding pad is connected to a bonding wire drawn from the chip pad through the window at a predetermined angle with respect to the side portion. A second bonding pad is adjacent to the first bonding pad on the second face. The second bonding pad includes an end portion having an inclined side portion at an angle corresponding to the drawn angle of the first bonding wire for avoiding an overlap of the second bonding pad with the first bonding wire.

Abstract translation: 用于半导体芯片的布线基板包括具有与第一面相对的第一面和第二面的基板。 衬底具有从第一面到第二面的窗口，其暴露可粘附到第一面的半导体芯片的芯片焊盘。 第一接合焊盘沿着窗口的侧部布置在第二面上。 第一接合焊盘通过窗口以相对于侧部以预定角度从芯片焊盘拉出的接合线连接。 第二接合焊盘与第二面上的第一接合焊盘相邻。 所述第二接合焊盘包括端部，所述端部具有与所述第一接合线的拉拔角度对应的倾斜侧部，以避免所述第二接合焊盘与所述第一接合线的重叠。

公开(公告)号：US07872874B2

公开(公告)日：2011-01-18

申请号：US11701816

申请日：2007-02-01

Applicant: Jun Karasawa ,  Daigo Suzuki ,  Hidenori Tanaka

Inventor： Jun Karasawa ,  Daigo Suzuki ,  Hidenori Tanaka

IPC: H05K7/10 ,  H05K7/12

CPC classification number: H05K1/111 ,  H05K3/284 ,  H05K3/3421 ,  H05K3/3442 ,  H05K2201/09381 ,  H05K2201/09663 ,  H05K2201/10636 ,  H05K2201/10689 ,  H05K2203/1178 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49147

Abstract: According to one embodiment, there is provided a printed-wiring board with a component in which an electronic component is mounted on a pattern-forming surface of a base material. In the printed-wiring board, a guiding path for guiding, to the outside, a void formed in mounting the electronic component is formed on the pattern-forming surface.

Abstract translation: 根据一个实施例，提供了一种印刷电路板，其具有将电子部件安装在基材的图案形成表面上的部件。 在印刷电路板中，在图案形成表面上形成用于将安装电子部件形成的空隙引导到外部的引导路径。

公开(公告)号：US20100270365A1

公开(公告)日：2010-10-28

申请号：US12831667

申请日：2010-07-07

Applicant: Yoichi KUKIMOTO ,  Kazuki Ikeda ,  Hitoshi Sakurai ,  Nobuhiro Kinoshita ,  Masaki Nakanishi

Inventor： Yoichi KUKIMOTO ,  Kazuki Ikeda ,  Hitoshi Sakurai ,  Nobuhiro Kinoshita ,  Masaki Nakanishi

IPC: B23K1/20

CPC classification number: B23K35/025 ,  B22F1/007 ,  B23K35/36 ,  H01L24/73 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01327 ,  H05K1/111 ,  H05K3/3463 ,  H05K3/3484 ,  H05K2201/0215 ,  H05K2201/09381 ,  H05K2203/043 ,  Y10T428/12035 ,  Y10T428/12493 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: The present invention relates to a solder paste composition used for precoating an electrode surface with solder. A first solder paste composition is contains a solder powder and a flux, and a metallic powder made by metallic species different from metallic species constituting the solder powder and metallic species constituting the electrode surface in a rate of 0.1% by weight or more and 20% by weight or less based on a total amount of the solder powder. When these solder paste compositions are evenly applied onto an electronic circuit substrate for precoating, such a solder that does not generate any swollen portion, solder-lacking portion and variability in a height thereof can be formed irrespective of a shape of a pad.

Abstract translation: 本发明涉及一种用于用焊料预涂电极表面的焊膏组合物。 第一焊膏组合物含有焊料粉末和焊剂，以及由构成焊料粉末的金属物质的金属物质构成的金属粉末和构成电极表面的金属物质的比例为0.1重量％以上且20重量％ 或更少的焊锡粉末。 当将这些焊膏组合物均匀地涂覆到用于预涂层的电子电路基板上时，可以形成不产生任何溶胀部分的焊料，焊料缺乏部分和其高度的变化性，而与焊盘的形状无关。

公开(公告)号：US07723855B2

公开(公告)日：2010-05-25

申请号：US11967098

申请日：2007-12-29

Applicant: Shu-Jen Tsai ,  Long-Fong Chen ,  Wen-Haw Tseng ,  Shih-Fang Wong

Inventor： Shu-Jen Tsai ,  Long-Fong Chen ,  Wen-Haw Tseng ,  Shih-Fang Wong

IPC: H01L23/48

CPC classification number: H05K1/111 ,  H01L2224/16225 ,  H05K3/3436 ,  H05K2201/09381 ,  H05K2201/094 ,  H05K2201/10734 ,  Y02P70/611 ,  Y10T428/12222 ,  Y10T428/24942

Abstract: A pad for soldering a contact of a surface mounted component is provided herein. The pad includes a central portion and a plurality of separate extending portions extending from the central portion. All of the plurality of separate extending portions includes a free end and a connected end connected to the central portion. A width of the free end is larger than a width of the connected end. A circuit board and an electronic device are also provided.

Abstract translation: 本文提供了用于焊接表面安装部件的触点的垫。 垫包括中心部分和从中心部分延伸的多个单独的延伸部分。 所述多个单独的延伸部分包括自由端和连接到中心部分的连接端。 自由端的宽度大于连接端的宽度。 还提供电路板和电子设备。

公开(公告)号：US07677905B2

公开(公告)日：2010-03-16

申请号：US11979968

申请日：2007-11-13

Applicant: Takayoshi Honda

Inventor： Takayoshi Honda

IPC: H01R12/00

CPC classification number: H05K1/116 ,  H01R12/707 ,  H01R43/0256 ,  H05K1/023 ,  H05K3/3405 ,  H05K3/3447 ,  H05K3/3484 ,  H05K2201/09381 ,  H05K2201/094 ,  H05K2201/09709 ,  H05K2201/09727 ,  H05K2201/0979 ,  H05K2201/10189 ,  H05K2201/10446 ,  H05K2201/10757 ,  H05K2201/10787 ,  H05K2201/10803 ,  H05K2201/10871 ,  H05K2201/10901 ,  H05K2203/1178 ,  H05K2203/1394

Abstract: An electronic device includes a printed circuit board with multiple lands and through holes and an electronic element with multiple terminals on the board. Each terminal is coupled with the land through a solder. The lands include a surface land on the board and an insertion land on a sidewall of the through hole. The terminals include a branch terminal having an insertion member and a surface member. The insertion member is coupled with the insertion land through the solder. The surface member is coupled with the surface land through the solder. The surface member is parallel to the printed circuit board. The insertion member is perpendicular to the printed circuit board. The insertion member extends from a part of the surface member, which faces the surface land and disposed above the through hole.

Abstract translation: 电子设备包括具有多个焊盘和通孔的印刷电路板以及具有多个端子的电子元件。 每个端子通过焊料与焊盘连接。 焊盘包括板上的表面焊盘和通孔的侧壁上的插入焊盘。 端子包括具有插入部件和表面部件的分支端子。 插入构件通过焊料与插入平台耦合。 表面构件通过焊料与表面焊盘连接。 表面构件平行于印刷电路板。 插入构件垂直于印刷电路板。 所述插入部件从所述表面部件的面向所述表面焊盘并设置在所述通孔的上方的一部分延伸。

公开(公告)号：US07675176B2

公开(公告)日：2010-03-09

申请号：US11968035

申请日：2007-12-31

Applicant: Chang-Yong Park ,  Kwang-Ho Chun ,  Dong-Chun Lee ,  Yong-Hyun Kim

Inventor： Chang-Yong Park ,  Kwang-Ho Chun ,  Dong-Chun Lee ,  Yong-Hyun Kim

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H05K1/111 ,  H01L2924/0002 ,  H05K3/3452 ,  H05K2201/0367 ,  H05K2201/09381 ,  H05K2201/094 ,  H05K2201/09845 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

Abstract: Provided are a semiconductor package and a module printed circuit board (PCB) for mounting the same. Each of the semiconductor package and the module PCB includes a substrate, a first-type pad structure disposed in a first region of the substrate, and a second-type pad structure disposed in a second region of the package substrate. The first-type pad includes a first conductive pad disposed on the package substrate and a first insulating layer coated on the package substrate. The first insulating layer has a first opening by which a portion of a sidewall of the first conductive pad is exposed, and partially covers the first conductive pad. The second-type pad includes a second insulating layer coated on the package substrate to have a second opening and a second conductive pad disposed on the package substrate in the second opening to have an exposed sidewall. In this structure, the semiconductor package and the module PCB can have an excellent resistance to physical and thermal stresses to enhance structural reliability.

Abstract translation: 提供了用于安装它的半导体封装和模块印刷电路板（PCB）。 半导体封装和模块PCB中的每一个包括衬底，设置在衬底的第一区域中的第一类型衬垫结构以及设置在封装衬底的第二区域中的第二类型衬垫结构。 第一型焊盘包括设置在封装衬底上的第一导电焊盘和涂覆在封装衬底上的第一绝缘层。 第一绝缘层具有第一开口，通过该第一开口，第一导电焊盘的侧壁的一部分被暴露，并且部分覆盖第一导电焊盘。 第二类型衬垫包括涂覆在封装衬底上以具有第二开口的第二绝缘层和设置在第二开口中的封装衬底上的具有暴露侧壁的第二导电焊盘。 在这种结构中，半导体封装和模块PCB可以具有优异的耐物理和热应力，以增强结构可靠性。

公开(公告)号：US20100035446A1

公开(公告)日：2010-02-11

申请号：US12535337

申请日：2009-08-04

Applicant: CHIN-WEN LO ,  YUEH-FANG WANG

Inventor： CHIN-WEN LO ,  YUEH-FANG WANG

IPC: H01R12/00

CPC classification number: H05K1/118 ,  H05K3/0058 ,  H05K2201/09381 ,  H05K2201/09409 ,  H05K2201/09481 ,  H05K2201/09727 ,  H05K2201/0979 ,  H05K2201/2009

Abstract: A pin layout of a golden finger for FPC is disclosed, which comprises: a substrate; a first conductive layer, having a plurality of first routings; a second conductive layer, having a plurality of second routings; and a plurality of conductive members; wherein the first and the second conductive layers are formed respectively on the two opposite sides of the substrate in a manner that each first routing is electrically connected to its corresponding first pin, while disposing a plurality of second pins, without contacting to the first pins and the first routings, on the side of the substrate where the first conductive layer is disposed for corresponding each of the second pins to the extensions of the plural second routings; and the plural conductive members are disposed forming electric connections between the second routings and the second pins in respective.

Abstract translation: 公开了一种用于FPC的金手指的销布局，其包括：基板; 第一导电层，具有多个第一布线; 第二导电层，具有多个第二布线; 和多个导电构件; 其中所述第一导电层和所述第二导电层分别形成在所述基板的两个相对侧上，使得每个第一布线电连接到其对应的第一引脚，同时设置多个第二引脚而不与所述第一引脚接触， 所述第一布线在所述基板的所述第一导电层被设置用于将所述第二引脚中的每一个对应于所述多个第二布线的延伸部的一侧上; 并且多个导电构件被布置成分别在第二布线和第二插脚之间形成电连接。

公开(公告)号：US07633766B2

公开(公告)日：2009-12-15

申请号：US12229367

申请日：2008-08-22

Applicant: Kent E. Regnier ,  David L. Brunker ,  Martin U. Ogbuokiri

Inventor： Kent E. Regnier ,  David L. Brunker ,  Martin U. Ogbuokiri

IPC: H05K7/00

CPC classification number: H05K1/0245 ,  H01R12/523 ,  H05K1/0222 ,  H05K1/0237 ,  H05K1/115 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09381 ,  H05K2201/09718

Abstract: A circuit board design is disclosed that is useful in high-speed differential signal applications uses either a via arrangement or a circuit trace exit structure. A pair of differential signal vias in a circuit board are surrounded by an opening that is formed within a ground plane disposed on another layer of the circuit board. The vias are connected to traces on the circuit board by way of an exit structure that includes two flag portions and associated angled portions that connect the flag portions to circuit board traces. In an alternate embodiment, the circuit board traces that leave the differential signal vias are disposed in one layer of the circuit board above a wide ground strip disposed on another layer of the circuit board.

Abstract translation: 公开了一种在高速差分信号应用中使用电路板设计或电路走线出口结构的电路板设计。 电路板中的一对差分信号通孔被形成在布置在电路板的另一层上的接地平面内的开口包围。 通孔通过出口结构连接到电路板上的迹线，该出口结构包括将标志部分连接到电路板迹线的两个标记部分和相关联的倾斜部分。 在替代实施例中，将差分信号通路的电路板迹线设置在设置在电路板的另一层上的宽接地条上的电路板的一层中。