公开(公告)号：US20110303451A1

公开(公告)日：2011-12-15

申请号：US13216767

申请日：2011-08-24

Applicant: Yasushi INAGAKI ,  Katsuyuki Sano

Inventor： Yasushi INAGAKI ,  Katsuyuki Sano

IPC: H05K1/16 ,  H05K1/11

CPC classification number: H05K1/0237 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/66 ,  H01L24/81 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/3511 ,  H05K1/0224 ,  H05K1/0263 ,  H05K1/0265 ,  H05K1/111 ,  H05K1/115 ,  H05K1/144 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09736 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A multilayer printed wiring board including a core substrate, a first conductor layer on a first surface of the substrate, a second conductor layer on a second surface of the substrate, a third conductor layer inside the substrate between the first and second conductor layers, a conductive post connecting the third conductor layer with the first and second conductor layers, a first conductor circuit on the first surface of the substrate, a second conductor circuit on the second surface of the substrate, and a through hole formed through the substrate and connecting the first and second conductor circuits. The through hole is not connected to the third conductor layer, the third conductor layer has thickness larger than thicknesses of the first and second conductor layers, each of the first, second and third conductor layers forms one of power supply and ground layers, and the through hole forms a signal line.

Abstract translation: 一种多层印刷布线板，包括芯基板，在基板的第一表面上的第一导体层，在基板的第二表面上的第二导体层，在第一和第二导体层之间的基板内的第三导体层， 将第三导体层与第一和第二导体层连接的导电柱，在基板的第一表面上的第一导体电路，在基板的第二表面上的第二导体电路，以及穿过基板形成的通孔， 第一和第二导体电路。 通孔不连接到第三导体层，第三导体层的厚度大于第一和第二导体层的厚度，第一，第二和第三导体层中的每一个形成电源和接地层中的一个，并且 通孔形成信号线。

公开(公告)号：US20110284914A1

公开(公告)日：2011-11-24

申请号：US13131257

申请日：2008-11-25

Applicant: Motohiro Suzuki ,  Naomi Yonemura ,  Yoshihiko Okajima ,  Tetsuro Maeda ,  Eiji Yoshimura

Inventor： Motohiro Suzuki ,  Naomi Yonemura ,  Yoshihiko Okajima ,  Tetsuro Maeda ,  Eiji Yoshimura

IPC: H01L33/64 ,  B32B37/02 ,  H05K1/11

CPC classification number: H05K1/0204 ,  H01L33/486 ,  H01L33/641 ,  H01L33/642 ,  H01L2224/48091 ,  H01L2224/48227 ,  H05K1/0206 ,  H05K1/0373 ,  H05K1/056 ,  H05K3/022 ,  H05K2201/0209 ,  H05K2201/0266 ,  H05K2201/09054 ,  H05K2201/09736 ,  H05K2201/10106 ,  H05K2203/1545 ,  H01L2924/00014

Abstract: A substrate for a light emitting element package provided with a thick metal section formed under a mounting position of a light emitting element, comprising:an insulating layer which is composed of a resin containing heat conductive fillers under the mounting position of said light emitting element and has a heat conductivity of 1.0 W/mK or more; and a metal layer disposed inside said insulating layer and having the thick metal section, wherein a heat conductive mask section is disposed at the top of said thick metal section.

Abstract translation: 一种用于发光元件封装的衬底，其具有形成在发光元件的安装位置的厚金属部分，包括：绝缘层，其由在所述发光元件的安装位置处的包含导热填料的树脂构成;以及 热导率为1.0W / mK以上; 以及金属层，其设置在所述绝缘层的内部并且具有厚的金属部分，其中导热掩模部分设置在所述厚金属部分的顶部。

公开(公告)号：US08049111B2

公开(公告)日：2011-11-01

申请号：US12485091

申请日：2009-06-16

Applicant: Katsutoshi Kamei ,  Voonyee Ho

Inventor： Katsutoshi Kamei ,  Voonyee Ho

IPC: H05K1/00

CPC classification number: H05K1/0237 ,  G11B5/484 ,  H05K1/0263 ,  H05K1/0265 ,  H05K1/056 ,  H05K2201/0191 ,  H05K2201/09236 ,  H05K2201/09736 ,  H05K2201/09845 ,  H05K2201/09972 ,  Y10T29/49155

Abstract: A first insulating layer is formed on a suspension body. Wiring traces are formed in parallel at an interval on the first insulating layer. A second insulating layer is formed in a region on the first insulating layer on both sides of the wiring traces. A wiring trace is formed in a region on the second insulating layer on the side of the wiring trace. A wiring trace is formed in a region on the second insulating layer on the side of the wiring trace. A third insulating layer is formed on the first and second insulating layers to cover the wiring traces.

Abstract translation: 在悬架体上形成第一绝缘层。 在第一绝缘层上以一定间隔平行地形成接线迹线。 第二绝缘层形成在布线迹线两侧的第一绝缘层上的区域中。 在布线迹线侧的第二绝缘层的区域中形成布线。 在布线迹线侧的第二绝缘层的区域中形成布线。 在第一和第二绝缘层上形成第三绝缘层以覆盖布线迹线。

公开(公告)号：US20110253306A1

公开(公告)日：2011-10-20

申请号：US13169736

申请日：2011-06-27

Applicant: Motoo Asai ,  Dongdong Wang ,  Takahiro Mori

Inventor： Motoo Asai ,  Dongdong Wang ,  Takahiro Mori

IPC: H05K3/00 ,  B32B38/04

CPC classification number: H05K3/423 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/036 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/381 ,  H05K3/385 ,  H05K3/387 ,  H05K3/388 ,  H05K3/426 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/0315 ,  H05K2203/0733 ,  H05K2203/0773 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599

Abstract: A method of manufacturing a printed circuit board includes the following steps (A) to (D). (A) Laminating a resin insulating layer on each of two sides of a core member to form a core substrate, (B) forming penetrating openings in the core substrate by applying laser beams, (C) forming a rough surface on the core substrate, and (D) providing a metal film for each penetrating opening to form through holes.

Abstract translation: 制造印刷电路板的方法包括以下步骤（A）至（D）。 （A）在芯部件的两侧各自层叠树脂绝缘层，形成芯基板，（B）通过施加激光而在芯基板上形成贯通孔，（C）在芯基板上形成粗糙面， 和（D）为每个穿透孔提供金属膜以形成通孔。

公开(公告)号：US08039762B2

公开(公告)日：2011-10-18

申请号：US12379056

申请日：2009-02-11

Applicant: Myung Sam Kang

Inventor： Myung Sam Kang

IPC: H05K1/11

CPC classification number: H05K1/111 ,  H01L2924/0002 ,  H05K3/205 ,  H05K3/28 ,  H05K3/3473 ,  H05K2201/0376 ,  H05K2201/09472 ,  H05K2201/09736 ,  Y02P70/611 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149 ,  H01L2924/00

Abstract: Disclosed is a printed circuit board having a buried solder bump, in which a circuit pattern and a solder bump formed on the circuit pattern are buried in an insulating layer, thus improving the degree of matching between the solder bump and the circuit pattern and obviating a need for an additional coining process of the solder bump. A manufacturing method thereof is also provided.

Abstract translation: 公开了一种具有掩埋焊料凸块的印刷电路板，其中形成在电路图案上的电路图案和焊料凸块被掩埋在绝缘层中，从而提高了焊料凸块与电路图案之间的匹配程度，并且消除了 需要额外的冲压焊过程。 还提供了其制造方法。

公开(公告)号：US08037596B2

公开(公告)日：2011-10-18

申请号：US11946360

申请日：2007-11-28

Applicant: Shigetsugu Muramatsu ,  Yasuhiko Kusama

Inventor： Shigetsugu Muramatsu ,  Yasuhiko Kusama

IPC: H05K3/02 ,  H05K1/00

CPC classification number: H05K3/4007 ,  H05K1/111 ,  H05K3/0044 ,  H05K3/243 ,  H05K3/28 ,  H05K3/3452 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09736 ,  H05K2203/025 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A wiring board includes: an uppermost wiring layer formed on a prescribed number of underlying wiring layers, a portion of the uppermost wiring layer being exposed and used as a pad for connection with a component to be mounted; and an insulation resin layer covering the uppermost wiring layer, wherein the thickness of the portion of the uppermost wiring layer is larger than that of other portions thereof.

Abstract translation: 布线基板包括：形成在规定数量的底层布线层上的最上布线层，最上布线层的一部分露出并用作与要安装的部件连接的垫; 以及覆盖最上层布线层的绝缘树脂层，其中最上层布线层的部分的厚度比其它部分的厚度大。

公开(公告)号：US20110121452A1

公开(公告)日：2011-05-26

申请号：US13019562

申请日：2011-02-02

Applicant: KiYoun Jang ,  SungSoo Kim ,  YongHee Kang

Inventor： KiYoun Jang ,  SungSoo Kim ,  YongHee Kang

IPC: H01L23/49 ,  H01L23/48

CPC classification number: H01L23/49811 ,  H01L21/4846 ,  H01L21/6835 ,  H01L23/498 ,  H01L23/49827 ,  H01L24/06 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2224/0401 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K3/108 ,  H05K3/205 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/097 ,  H05K2201/09736 ,  H05K2203/049 ,  H05K2203/1476 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate, a first recessed conductive layer embedded and recessed into a first surface of the substrate, and a first raised conductive layer disposed above the first surface. A first vertical offset exists between an upper surface of the first recessed conductive layer and an upper surface of the first raised conductive layer. The device includes a second recessed conductive layer embedded and recessed into a second surface of the substrate. The second surface of the substrate is opposite the first surface. The device includes a second raised conductive layer disposed beneath the second surface and an interconnect structure disposed on the first recessed and raised conductive layers and the second recessed and raised conductive layers. A second vertical offset exists between a lower surface of the second recessed conductive layer and a lower surface of the second recessed conductive layer.

Abstract translation: 半导体器件包括衬底，嵌入并凹入到衬底的第一表面中的第一凹陷导电层和设置在第一表面上方的第一凸起导电层。 在第一凹陷导电层的上表面和第一凸起导电层的上表面之间存在第一垂直偏移。 该器件包括嵌入并凹入到衬底的第二表面中的第二凹陷导电层。 基板的第二表面与第一表面相对。 该装置包括设置在第二表面下方的第二凸起导电层和设置在第一凹入和凸起导电层上的互连结构和第二凹入和凸起导电层。 在第二凹陷导电层的下表面和第二凹陷导电层的下表面之间存在第二垂直偏移。

公开(公告)号：US20110067909A1

公开(公告)日：2011-03-24

申请号：US12787422

申请日：2010-05-26

Applicant: Wei-Ming Cheng

Inventor： Wei-Ming Cheng

IPC: H05K1/09 ,  H05K1/00

CPC classification number: H05K3/381 ,  H05K1/0265 ,  H05K3/0032 ,  H05K3/38 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2201/2072 ,  H05K2203/0723

Abstract: An embedded circuit board structure and a fabricating process thereof are disclosed. The embedded circuit board structure comprises a dielectric layer and a metal layer. The dielectric layer comprises an indentation; the indentation is formed by a plurality of pits, and the pits are substantially perpendicular to the surface of the dielectric layer. The metal layer is formed within the indentation.

Abstract translation: 公开了一种嵌入式电路板结构及其制造方法。 嵌入式电路板结构包括电介质层和金属层。 介电层包括凹陷; 凹陷由多个凹坑形成，凹坑基本上垂直于介电层的表面。 金属层形成在压痕内。

公开(公告)号：US07897502B2

公开(公告)日：2011-03-01

申请号：US12207986

申请日：2008-09-10

Applicant: KiYoun Jang ,  SungSoo Kim ,  YongHee Kang

Inventor： KiYoun Jang ,  SungSoo Kim ,  YongHee Kang

IPC: H01L21/44

CPC classification number: H01L23/49811 ,  H01L21/4846 ,  H01L21/6835 ,  H01L23/498 ,  H01L23/49827 ,  H01L24/06 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2224/0401 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K3/108 ,  H05K3/205 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/097 ,  H05K2201/09736 ,  H05K2203/049 ,  H05K2203/1476 ,  H01L2924/00

Abstract: A method of making a semiconductor device comprises forming a first conductive layer recessed below a surface of a substrate. The method further comprises forming a second conductive layer raised above the surface of the substrate to create a vertical offset between the first and second conductive layers. The method further comprises forming an interconnect structure on the first and second conductive layers.

Abstract translation: 制造半导体器件的方法包括形成在衬底的表面下方凹入的第一导电层。 该方法还包括形成在衬底的表面上方升高的第二导电层，以在第一和第二导电层之间产生垂直偏移。 该方法还包括在第一和第二导电层上形成互连结构。

公开(公告)号：US20110013366A1

公开(公告)日：2011-01-20

申请号：US12835961

申请日：2010-07-14

Applicant: Luisa COPPOLA ,  Didier Cottet ,  Matteo Fabbri ,  Roland Schmidt

Inventor： Luisa COPPOLA ,  Didier Cottet ,  Matteo Fabbri ,  Roland Schmidt

IPC: H05K7/20

CPC classification number: H05K1/0209 ,  H05K2201/066 ,  H05K2201/09736 ,  H05K2201/09781 ,  H05K2201/10204

Abstract: An electronic circuit board includes at least one conductor path and at least one component which is one of an electronic component, electric component and heat emitting component, and which is connected to the conductor path. At least one thermal capacitor is thermally connected to the conductor in vicinity to the at least one component. The at least one thermal capacitor is suitable for transmitting and/or buffering thermal energy of the at least one component.

Abstract translation: 电子电路板包括至少一个导体路径和至少一个作为电子部件，电气部件和发热部件之一的部件，并且连接到导体路径。 至少一个热电容器与至少一个部件附近的导体热连接。 所述至少一个热电容器适用于传输和/或缓冲所述至少一个部件的热能。