公开(公告)号：US09767241B2

公开(公告)日：2017-09-19

申请号：US12749254

申请日：2010-03-29

Applicant: Norman L. Rogers ,  John W. Hoffman ,  Jun Feng ,  Charles Krauter

Inventor： Norman L. Rogers ,  John W. Hoffman ,  Jun Feng ,  Charles Krauter

IPC: G06F17/50 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00

CPC classification number: G06F17/5068 ,  H05K1/0206 ,  H05K1/029 ,  H05K1/0295 ,  H05K1/111 ,  H05K1/114 ,  H05K3/0005 ,  H05K3/0064 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09418 ,  H05K2201/09454 ,  H05K2201/09663 ,  H05K2201/09954 ,  H05K2201/10022 ,  H05K2201/10166 ,  H05K2201/10636 ,  H05K2203/173 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/49124

Abstract: A method and apparatus for inputting a plurality of different circuit schematics designed with printed circuit board (PCB) mountable components; extracting circuit topologies for said plurality of different circuit schematics; transforming said extracted circuit topologies to a fixed number of connection points; and generating a configurable circuit PCB physical layout pattern having said fixed number of connection points such that said PCB mountable components when positioned on one or more of said fixed number of connection points can implement any circuit represented by said plurality of different circuit schematics.

公开(公告)号：US09748664B2

公开(公告)日：2017-08-29

申请号：US14487711

申请日：2014-09-16

Applicant: Sony Corporation

Inventor： Hirofumi Kawamura

IPC: H01Q21/00 ,  H01L23/66 ,  H01L23/00 ,  H01P1/04 ,  H01P5/08 ,  H05K1/02

CPC classification number: H01Q21/0075 ,  H01L23/66 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2223/6627 ,  H01L2223/6633 ,  H01L2223/6677 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/19032 ,  H01L2924/19039 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01P1/047 ,  H01P5/08 ,  H05K1/0219 ,  H05K1/0243 ,  H05K1/025 ,  H05K2201/09727 ,  H05K2201/10166 ,  H05K2203/049 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Disclosed herein is a semiconductor device including: a semiconductor circuit element configured to process an electrical signal having a predetermined frequency; and a transmission line configured to be connected to the semiconductor circuit element via a wire and transmit the electrical signal. An impedance matching pattern having a symmetric shape with respect to a direction of the transmission line is provided in the transmission line.

公开(公告)号：US09748205B2

公开(公告)日：2017-08-29

申请号：US15081365

申请日：2016-03-25

Applicant: DELTA ELECTRONICS, INC.

Inventor： Kai Lu ,  Zhenqing Zhao ,  Tao Wang ,  Le Liang

IPC: H01L23/495 ,  H01L25/065 ,  H01L23/31 ,  H05K1/02 ,  H05K3/28

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/49517 ,  H01L23/49531 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49589 ,  H01L2224/16225 ,  H01L2224/48137 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06572 ,  H01L2924/181 ,  H01L2924/19105 ,  H05K1/0263 ,  H05K3/284 ,  H05K2201/10166 ,  H05K2203/1316 ,  H01L2924/00012

Abstract: A molding type power module includes: a leadframe including a first step and a second step; a first planar power device including a first surface having electrodes and a second surface opposite to the first surface, the electrodes being correspondingly bond to the first step respectively; and a second planar power device including a first surface having electrodes and a second surface opposite to the first surface, the electrodes being correspondingly bond to the second step respectively, wherein, the first surface of the first planar power device and the first surface of the second planar power device face each other, the projected areas thereof on a vertical direction at least partially overlap, and the first planar power device at least has one electrode electronically connected with the electrodes of the second planar power device.

公开(公告)号：US09743509B2

公开(公告)日：2017-08-22

申请号：US13159743

申请日：2011-06-14

Applicant: Peter Sven Jansson ,  Anders Lars Uddner

Inventor： Peter Sven Jansson ,  Anders Lars Uddner

IPC: H02M7/00 ,  H05K1/02 ,  H05K1/14 ,  H05K3/00

CPC classification number: H05K1/0263 ,  H02M7/003 ,  H05K1/144 ,  H05K3/0061 ,  H05K2201/042 ,  H05K2201/10166 ,  H05K2201/10272

Abstract: It is presented an inverter type motor drive device for feeding three phase AC electric power to an electric motor, the inverter type motor drive device comprising: an insulated metal substrate board on which, for each of the three phases, a plurality of power switches are mounted in straight lines in switch assemblies along a first direction; a printed circuit board on which a plurality of capacitors are mounted; and two DC power input terminals. The inverter type motor drive device further comprises three AC power output terminals, each extending through the printed circuit board while avoiding galvanic contact with the printed circuit board, and each of the three AC power output terminals comprise an elongated AC busbar, wherein a longitudinal direction of the AC busbar extends along the first direction.

公开(公告)号：US09741702B2

公开(公告)日：2017-08-22

申请号：US14950411

申请日：2015-11-24

Applicant: Transphorm Inc.

Inventor： Yifeng Wu

IPC: H01L25/00 ,  H01L25/07 ,  H05K1/02 ,  H03K17/16 ,  H01L23/12 ,  H01L23/367 ,  H01L27/088 ,  H01L29/20 ,  H01L29/78 ,  H01L23/498 ,  H01L25/11 ,  H05K1/16 ,  H01L23/552 ,  H01L23/64 ,  H01L25/16

CPC classification number: H01L25/50 ,  H01L23/12 ,  H01L23/3675 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49844 ,  H01L23/552 ,  H01L23/642 ,  H01L25/074 ,  H01L25/117 ,  H01L25/16 ,  H01L25/165 ,  H01L27/0883 ,  H01L29/2003 ,  H01L29/7827 ,  H01L2224/48091 ,  H01L2924/13055 ,  H01L2924/30107 ,  H03K17/164 ,  H03K2217/0045 ,  H05K1/0218 ,  H05K1/0263 ,  H05K1/162 ,  H05K2201/10015 ,  H05K2201/10166 ,  H05K2201/10545 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive portion of the first package, and a second transistor encased in a second package, the second transistor being mounted over a second conductive portion of the second package. The component further includes a substrate comprising an insulating layer between a first metal layer and a second metal layer. The first package is on one side of the substrate with the first conductive portion being electrically connected to the first metal layer, and the second package is on another side of the substrate with the second conductive portion being electrically connected to the second metal layer. The first package is opposite the second package, with at least 50% of a first area of the first conductive portion being opposite a second area of the second conductive portion.

公开(公告)号：US20170230011A1

公开(公告)日：2017-08-10

申请号：US15312717

申请日：2015-04-29

Applicant: CommScope Technologies LLC

Inventor： Sammit A. Patel ,  Yongjie Xu ,  Qiyun Gu ,  Richard W. Brown

IPC: H03F1/30 ,  H03F3/213 ,  H03F3/193 ,  H01L23/427 ,  H01L23/66 ,  H03F3/21 ,  H01L25/10 ,  H05K1/02 ,  H05K1/18 ,  H01L23/40 ,  H01L25/00 ,  H05K3/34 ,  H03F3/195 ,  H01L25/11

CPC classification number: H03F1/301 ,  H01L23/4006 ,  H01L23/427 ,  H01L23/66 ,  H01L29/7816 ,  H01L2023/4031 ,  H01L2023/4062 ,  H01L2023/4087 ,  H01L2223/6644 ,  H01L2924/0002 ,  H03F3/213 ,  H03F2200/411 ,  H03F2200/447 ,  H03F2200/451 ,  H05K1/0203 ,  H05K1/183 ,  H05K3/3421 ,  H05K3/3463 ,  H05K7/2029 ,  H05K7/20336 ,  H05K7/20936 ,  H05K2201/064 ,  H05K2201/09036 ,  H05K2201/09063 ,  H05K2201/10166 ,  H01L2924/00

Abstract: In one embodiment, an electronic system includes a printed circuit board, one or more packaged semiconductor devices, and a vapor chamber having a top and a bottom and enclosing a sealed cavity that is partially filled with a coolant. The vapor chamber comprises a thermo-conductive and electro-conductive material. The top of the vapor chamber has one or more depressions formed therein, each depression receiving and thermo-conductively connected to at least part of a bottom of a corresponding packaged semiconductor device, which is mounted through a corresponding aperture in the PCB. A heat sink may be thermo-conductively attached to the bottom of the vapor chamber.

公开(公告)号：US20170223834A1

公开(公告)日：2017-08-03

申请号：US15297190

申请日：2016-10-19

Applicant: CYNTEC CO., LTD.

Inventor： CHI-FENG HUANG ,  BAU-RU LU ,  DA-JUNG CHEN

IPC: H05K1/18

CPC classification number: H05K1/181 ,  H01F27/06 ,  H01F27/292 ,  H01F2027/065 ,  H01F2027/297 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10166 ,  H05K2201/10174

Abstract: A stacked electronic structure is provided. The stacked electronic structure includes: a magnetic device, electronic devices, and a substrate. The substrate is disposed under the magnetic device. First and second electronic devices are disposed between a bottom surface of the magnetic device and a top surface of the substrate. The first and second electronic devices comprise first and third terminals, disposed on first and second surfaces thereof, respectively, electrically connected to the magnetic device without using the substrate. The first and second electronic devices also comprise second and fourth terminals, disposed on second and fourth surfaces thereof, respectively, electrically connected to the substrate.

公开(公告)号：US20170196089A1

公开(公告)日：2017-07-06

申请号：US15466442

申请日：2017-03-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael A. Gaynes ,  Jeffrey D. Gelorme ,  Robert P. Kuder, II ,  Daniel J. Littrell ,  Thomas E. Lombardi ,  Marie-Claude Paquet ,  Frank L. Pompeo ,  David L. Questad ,  James Speidell ,  Sri M. Sri-Jayantha ,  Son K. Tran

IPC: H05K1/18 ,  H05K3/30 ,  H01R4/02

CPC classification number: H05K1/18 ,  H01L23/12 ,  H01R4/02 ,  H01R12/51 ,  H01R12/7041 ,  H01R43/205 ,  H05K1/0271 ,  H05K1/181 ,  H05K3/30 ,  H05K3/305 ,  H05K3/366 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10106 ,  H05K2201/10159 ,  H05K2201/10166 ,  H05K2201/10977

Abstract: An interconnect structure that includes a component circuit board containing a plurality of electrical components, and a wafer connector assembly. The wafer connector assembly includes a plurality of interconnect circuit boards that are in electrical connection with the components circuit board through a plurality of rows of solder joints, the plurality of interconnect circuit boards having a connection end including at least one contact. An adhesive is present structurally reinforcing at least a row of the solder joints that is proximate to the connection end of the plurality of interconnect circuit boards of the wafer assembly.

公开(公告)号：US20170164465A1

公开(公告)日：2017-06-08

申请号：US15325550

申请日：2015-06-17

Applicant: Siemens Aktiengesellschaft

Inventor： Ruediger Knofe ,  Bernd Mueller ,  Andrey Prihodovsky

IPC: H05K1/02 ,  H05K3/30 ,  H05K1/11

CPC classification number: H05K1/0212 ,  H05K1/095 ,  H05K1/11 ,  H05K1/167 ,  H05K3/30 ,  H05K3/321 ,  H05K3/325 ,  H05K3/34 ,  H05K3/3494 ,  H05K2201/06 ,  H05K2201/0999 ,  H05K2201/10053 ,  H05K2201/10151 ,  H05K2201/10166 ,  H05K2201/10689 ,  H05K2203/1115 ,  H05K2203/165

Abstract: A method for producing or disassembling an electronic assembly are provided. The assembly may have a heating device integrated into a substrate. The heating device can be heated via an external power supply during the assembly process so that, for example, solder connections of an electric component can be melted. The heating device can also be used when operating the electronic assembly, and the heating device can then be directly actuated by the component. For this purpose, an electric connection is then established between the component and the heating device, the connection not yet being provided during the thermal assembly process in order to protect the electronic components of the circuit from being damaged.

公开(公告)号：US09661752B2

公开(公告)日：2017-05-23

申请号：US13163200

申请日：2011-06-17

Applicant: Tao Hong ,  Markus Thoben

Inventor： Tao Hong ,  Markus Thoben

IPC: H05K7/00 ,  H05K1/18 ,  G01R1/20 ,  H01L23/64 ,  H01L25/07 ,  H01L25/16 ,  H01L25/18 ,  H01L23/00 ,  H01L27/02 ,  H01L49/02 ,  H05K3/22

CPC classification number: H05K1/181 ,  G01R1/203 ,  H01L23/647 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L25/072 ,  H01L25/16 ,  H01L25/18 ,  H01L27/0207 ,  H01L28/20 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/8382 ,  H01L2224/8384 ,  H01L2224/85205 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30107 ,  H05K3/222 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/10022 ,  H05K2201/10166 ,  H05K2203/173 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/83205

Abstract: A circuit arrangement has a populated circuit carrier and includes a flat insulation carrier having a top side and a patterned metallization layer on the top side and a first power semiconductor chip arranged on a first section of the metallization layer. The first power semiconductor chip has a first lower chip load terminal electrically conductively connected to the first section. A shunt resistor is arranged on a second section of the metallization layer. The shunt resistor has a lower main terminal electrically conductively connected to the second section. An electrically conductive connection is provided between the first section and the second section. The electrically conductive connection includes a constriction between the first section and the second section so that a current which flows between the first lower chip load terminal and the lower main terminal during operation of the circuit arrangement must pass through the constriction.