公开(公告)号：US20100090351A1

公开(公告)日：2010-04-15

申请号：US12357643

申请日：2009-01-22

Applicant: Heung-Kyu Kim ,  Young-Hwan Shin ,  Jong-Jin Lee

Inventor： Heung-Kyu Kim ,  Young-Hwan Shin ,  Jong-Jin Lee

IPC: H01L23/538

CPC classification number: H01L23/5385 ,  H01L24/13 ,  H01L24/14 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2225/1005 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/141 ,  H05K3/222 ,  H05K2201/1053 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2224/0401

Abstract: An electro component package is disclosed. The electro component package in accordance with an embodiment of the present invention includes a first package substrate having a first chip mounted on an upper surface thereof, the first chip having a through-via formed therein; a second package substrate being separated from the first package substrate and having a second chip mounted on an upper surface thereof; and a connection substrate having one end connected with an upper surface of the first chip and the other end connected with an upper surface of the second chip, the connection substrate electrically connecting the first chip with the second chip.

Abstract translation: 公开了电子部件封装。 根据本发明的实施例的电子部件封装包括：第一封装基板，其具有安装在其上表面上的第一芯片，所述第一芯片具有形成在其中的通孔; 第二封装衬底与第一封装衬底分离并且具有安装在其上表面上的第二芯片; 以及连接基板，其一端与所述第一芯片的上表面连接，所述另一端与所述第二芯片的上表面连接，所述连接基板将所述第一芯片与所述第二芯片电连接。

公开(公告)号：US07592202B2

公开(公告)日：2009-09-22

申请号：US11395021

申请日：2006-03-31

Applicant: Munehiro Toyama ,  Charan Gurumurthy ,  Toshimi Kohmura

Inventor： Munehiro Toyama ,  Charan Gurumurthy ,  Toshimi Kohmura

IPC: H01L21/00

CPC classification number: H05K1/183 ,  H01L23/5389 ,  H01L23/66 ,  H01L25/18 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10674 ,  H01L2224/05599

Abstract: An embodiment of the present invention is a technique to reduce interconnect length between devices. A cavity is formed in a substrate having a substrate surface. The cavity has a depth. A first device having a device surface and a thickness is placed into the cavity. The thickness matches the depth such that the device surface is approximately planar with the substrate surface. The first device is attached to a second device via bumps on the second device.

Abstract translation: 本发明的实施例是减少设备之间的互连长度的技术。 在具有基板表面的基板中形成空腔。 空腔有一个深度。 具有器件表面和厚度的第一器件被放置在腔中。 厚度与深度匹配，使得器件表面与衬底表面近似平面。 第一设备通过第二设备上的凸块附接到第二设备。

公开(公告)号：US07505284B2

公开(公告)日：2009-03-17

申请号：US11416757

申请日：2006-05-03

Applicant: Bert J. Offrein ,  Stefano S. Oggioni ,  Mauro Spreafico

Inventor： Bert J. Offrein ,  Stefano S. Oggioni ,  Mauro Spreafico

IPC: H05K1/11

CPC classification number: H01L23/66 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/522 ,  H01L23/552 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/86 ,  H01L25/0655 ,  H01L25/167 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/81143 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81224 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/222 ,  H05K3/3436 ,  H05K2201/045 ,  H05K2201/10121 ,  H05K2201/1053 ,  H05K2201/10674 ,  Y10T29/49144 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic system comprising: an electronic system support substrate for the attachment of components of the electronic system, the electronic system support substrate including electric signal propagation paths for the propagation of electric signals between the system components; at least a first and a second electronic components wherein at least the first electronic component is part of a module in mechanical and electrical connection with the electronic system support substrate, the module comprising a module substrate to which the first electronic component is at least mechanically connected, and an electric coupling between the first and the second electronic components, for the electric coupling allowing the first and the second electronic components exchange of electric signals. The electric coupling comprises a direct electric connection particularly formed by a flexible electrical interconnection member, between the first and the second electronic components, the electric connection being independent of the electronic system support substrate.

Abstract translation: 一种电子系统，包括：用于附接所述电子系统的部件的电子系统支撑基板，所述电子系统支撑基板包括用于在所述系统部件之间传播电信号的电信号传播路径; 至少第一和第二电子部件，其中至少所述第一电子部件是与所述电子系统支撑基板机械和电连接的模块的一部分，所述模块包括模块基板，所述第一电子部件至少机械连接到所述模块基板 以及第一和第二电子部件之间的电耦合，用于电耦合，允许第一和第二电子部件交换电信号。 电耦合包括在第一和第二电子部件之间特别由柔性电互连部件形成的直接电连接，电连接独立于电子系统支撑基板。

公开(公告)号：US20090051004A1

公开(公告)日：2009-02-26

申请号：US11844672

申请日：2007-08-24

Applicant: Weston C. Roth ,  James D. Jackson ,  Damion Searls ,  Kevin Byrd

Inventor： Weston C. Roth ,  James D. Jackson ,  Damion Searls ,  Kevin Byrd

IPC: H01L29/00 ,  H01L21/00 ,  H01L23/48

CPC classification number: H01L23/49816 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/0231 ,  H05K1/145 ,  H05K3/3436 ,  H05K2201/094 ,  H05K2201/10242 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10734 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00

Abstract: A microelectronic package and a method of forming the package. The package includes a first level package mounted to a carrier. The first level package includes a package substrate having a die side and a carrier side; and a microelectronic die mounted on the package substrate at the die side thereof. The carrier has a substrate side, and the first level package is mounted on the carrier at the substrate side thereof. A rigid body is attached to the carrier side of the substrate at an attachment location of the substrate and to the substrate side of the carrier at an attachment location of the carrier, the attachment location of the carrier being electrically unconnected, the rigid body being configured and disposed to provide structural support between the substrate and the carrier.

Abstract translation: 微电子封装和形成封装的方法。 该包装包括安装在载体上的第一级封装。 第一级封装包括具有裸片侧和载体侧的封装基板; 以及在其芯片侧安装在封装基板上的微电子管芯。 载体具有基板侧，并且第一级封装在其基板侧安装在载体上。 刚性体在基板的安装位置和载体的安装位置处附着到基板的载体侧，载体的附接位置电连接，刚体被构造成 并设置成在基板和载体之间提供结构支撑。

公开(公告)号：US20090032922A1

公开(公告)日：2009-02-05

申请号：US12182034

申请日：2008-07-29

Applicant: Yuichi Koga

Inventor： Yuichi Koga

IPC: H01L23/495

CPC classification number: H01L23/642 ,  H01L23/50 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/19105 ,  H05K1/0239 ,  H05K1/0245 ,  H05K2201/09236 ,  H05K2201/10015 ,  H05K2201/1053 ,  H05K2201/10734 ,  H01L2924/00

Abstract: According to one embodiment, a semiconductor package comprises a substrate having one surface mounted with a semiconductor chip, and the other surface mounted with a plurality of arrayed external connection electrodes, a differential line pair provided on the surface of the substrate mounted with the semiconductor chip, and making a connection between the semiconductor chip and a predetermined pair of electrodes included in the external connection electrodes, and a coupling capacitor pair inserted between the differential lines.

Abstract translation: 根据一个实施例，半导体封装包括具有安装有半导体芯片的一个表面的基板，并且另一表面安装有多个排列的外部连接电极，设置在安装有半导体芯片的基板的表面上的差分线对 并且在半导体芯片与包括在外部连接电极中的预定对电极之间形成连接，以及插入差分线之间的耦合电容器对。

公开(公告)号：US20090016033A1

公开(公告)日：2009-01-15

申请号：US12136007

申请日：2008-06-09

Applicant: Seng Guan Chow ,  Il Kwon Shim ,  Byung Joon Han ,  Kambhampati Ramakrishna

Inventor： Seng Guan Chow ,  Il Kwon Shim ,  Byung Joon Han ,  Kambhampati Ramakrishna

IPC: H05K1/18

CPC classification number: H05K1/189 ,  H01L23/49816 ,  H01L23/5387 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19105 ,  H05K1/141 ,  H05K1/147 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/042 ,  H05K2201/056 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2203/1316 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099

Abstract: An integrated circuit package system includes: providing a flexible circuit substrate; mounting an integrated circuit or an integrated circuit package over the flexible circuit substrate and connected to the flexible circuit substrate with interconnects; and encapsulating the integrated circuit or integrated circuit package with a mounded encapsulation having a first level and a second level, the second level having the flexible circuit substrate folded thereover.

Abstract translation: 集成电路封装系统包括：提供柔性电路基板; 在柔性电路基板上安装集成电路或集成电路封装，并用互连连接到柔性电路基板; 以及用具有第一电平和第二电平的堆叠封装封装所述集成电路或集成电路封装，所述第二电平具有在其上折叠的所述柔性电路基板。

公开(公告)号：US20090001541A1

公开(公告)日：2009-01-01

申请号：US11824351

申请日：2007-06-29

Applicant: James B. Covert ,  David S. Trollope

Inventor： James B. Covert ,  David S. Trollope

IPC: H01L23/02 ,  H01L21/44

CPC classification number: H05K1/18 ,  H01L25/105 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/0002 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10704 ,  H01L2924/00

Abstract: Systems and methods for vertically stacking integrated circuit (IC) modules on a motherboard to conserve motherboard space and reduce power consumption are disclosed. IC modules can comprise processor circuitry, memory elements, communication circuitry, etc. Pins on each IC module can be directly inserted into lower IC module or into a socket layer that couples the IC modules. Heat generated by the IC modules can be dissipated by inserting heat dissipation layers into the vertical stack, between IC modules, or by placing a heat-dissipating sleeve around the stack. The IC modules themselves and/or heat-generating regions therein may be misaligned on their respective socket layers to further facilitate dissipating heat. Module stacks are scalable in that a user may add memory and/or processor modules as desired to increase device capability.

Abstract translation: 公开了用于在母板上垂直堆叠集成电路（IC）模块以节省主板空间并降低功耗的系统和方法。 IC模块可以包括处理器电路，存储器元件，通信电路等。每个IC模块上的引脚可以直接插入到下IC模块或耦合IC模块的插座层中。 通过将散热层插入垂直堆叠，IC模块之间，或者通过在堆叠周围放置散热套筒，可以消散由IC模块产生的热量。 IC模块本身和/或其中的发热区域可能在其相应的插座层上不对准，以进一步促进散热。 模块堆栈是可扩展的，因为用户可以根据需要添加内存和/或处理器模块以增加设备能力。

公开(公告)号：US20080284043A1

公开(公告)日：2008-11-20

申请号：US10598483

申请日：2005-02-23

Applicant: Robert-Christian Hagen ,  Jens Pohl

Inventor： Robert-Christian Hagen ,  Jens Pohl

IPC: H01L23/48 ,  H01L21/00

CPC classification number: H01L23/4985 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3511 ,  H05K1/141 ,  H05K1/147 ,  H05K2201/049 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A base semiconductor component for a semiconductor component stack is disclosed. In one embodiment, the base semiconductor component has a semiconductor chip arranged centrally on a stiff wiring substrate. The wiring substrate has, in its edge regions, contact pads which are electrically connected to external contacts and at the same time to contact areas of the semiconductor chip and also to stack contact areas. The stack contact areas simultaneously form the upper side of the base semiconductor component and have an arrangement pattern corresponding to an arrangement pattern of external contacts of a semiconductor component to be stacked.

Abstract translation: 公开了一种用于半导体部件堆叠的基底半导体部件。 在一个实施例中，基底半导体部件具有中央布置在刚性布线基板上的半导体芯片。 布线基板在其边缘区域中具有电连接到外部触点并且同时接触半导体芯片的区域并且还与堆叠接触区域的接触焊盘。 堆叠接触区域同时形成基底半导体部件的上侧，并且具有对应于待堆叠的半导体部件的外部触头的布置图案的布置图案。

公开(公告)号：US20080266827A1

公开(公告)日：2008-10-30

申请号：US12216153

申请日：2008-06-30

Applicant: Hiroshi Yokozawa

Inventor： Hiroshi Yokozawa

IPC: H05K7/02

CPC classification number: H05K1/181 ,  H01L25/0753 ,  H01L2924/0002 ,  H05K3/321 ,  H05K3/3442 ,  H05K2201/09418 ,  H05K2201/10106 ,  H05K2201/1053 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00

Abstract: A chip component mounting structure is provided that has a chip component surface mounted on a pair of electrodes formed on a substrate. The electrodes have differing areas, and the chip component and t.

Abstract translation: 提供一种芯片部件安装结构，其具有安装在形成在基板上的一对电极上的芯片部件表面。 电极具有不同的面积，以及芯片组件和t。

公开(公告)号：US20080157320A1

公开(公告)日：2008-07-03

申请号：US11617906

申请日：2006-12-29

Applicant: Ray D. Harrison ,  Jianbai Zhu ,  Jeffrey J. Wolfe ,  Frank Stepniak

Inventor： Ray D. Harrison ,  Jianbai Zhu ,  Jeffrey J. Wolfe ,  Frank Stepniak

IPC: H01L23/48 ,  H01L21/58

CPC classification number: H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/112 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/09627 ,  H05K2201/1053 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Semiconductor devices and methods for their assembly are described in which IC packages may be combined in novel configurations. A multi-package semiconductor device system and associated methods for its construction include a plurality of packaged semiconductor devices, each provided with at least one lateral electrical contact. The plurality of packaged semiconductor devices so provided are fixed in a coplanar configuration and have the adjacent lateral contacts coupled for operation in concert.

Abstract translation: 描述了用于组装的半导体器件和方法，其中IC封装可以以新颖的结构组合。 多封装半导体器件系统及其结构的相关方法包括多个封装的半导体器件，每个封装的半导体器件均设置有至少一个横向电接触。 如此设置的多个封装半导体器件被固定为共面构造，并且具有相互连接的相邻的侧向触点以一起操作。