-
61.发明申请METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS (ADCS) 有权非线性随机逼近寄存器（SAR）模数转换器（ADCS）的方法与系统公开(公告)号：US20150162928A1
公开(公告)日：2015-06-11
申请号：US14585656
申请日：2014-12-30
Applicant: MaxLinear, Inc.
Inventor： Eric Fogleman , Sheng Ye , Xuefeng Chen , Kok Lim Chan
Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.
Abstract translation: 在每个数模转换器（DAC）码字中利用一个或多个重叠冗余位的异步逐次逼近寄存器模数转换器（SAR ADC）可操作以产生指示每个数 - 模转换器 比较步骤，表示每个比较步骤的输出决定是有效的。 可以基于产生的指示信号来启动定时器。 可以产生超时信号，该超时信号抢占指示信号并强制先占决定，其中先占决定将一个或多个剩余的比特设置为相应的数模转换器中的一个或多个重叠的冗余比特，但不包括其中的一个或多个重叠的冗余比特 用于当前比较步骤的代码字到特定值。 例如，可以将一个或多个剩余比特设置为从在紧接的前一决定中确定的比特的值导出的值。
-
62.发明申请METHOD AND SYSTEM FOR TIME INTERLEAVED ANALOG-TO-DIGITAL CONVERTER TIMING MISMATCH ESTIMATION AND COMPENSATION 有权时间间隔模拟数字转换器时序误差估计与补偿的方法与系统公开(公告)号：US20150124915A1
公开(公告)日：2015-05-07
申请号：US14590250
申请日：2015-01-06
Applicant: Maxlinear, Inc.
Inventor： Pawandeep Taluja , Mingrui Zhu , Xuefeng Chen , Anand Anandakumer , Sheng Ye , Timothy Leo Gallagher
CPC classification number: H03M1/0612 , H03M1/1009 , H03M1/1038 , H03M1/1215 , H03M1/50 , H04L7/0087 , H04L25/08 , H04W56/00
Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may comprise receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.
Abstract translation: 用于时间交织的模数转换器定时失配校准和补偿的方法和系统可以包括在芯片上接收模拟信号，利用时间交织的模数转换器（ADC）将模拟信号转换成数字信号， 并且通过估计期望的数字输出信号和阻塞信号之间的复耦合系数来减少由时间交错ADC中的定时偏移产生的阻塞信号。 解相关算法可以包括对称自适应去相关算法。 所接收的模拟信号可以由芯片上的校准音发生器产生。 混叠信号可以与来自乘法器的输出信号相加。 复数耦合系数可以利用求和信号上的去相关算法来确定。 乘法器可以被配置为利用所确定的复耦合系数来消除阻塞信号。
-
63.发明申请METHOD AND SYSTEM FOR ASYNCHRONOUS SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTOR (ADC) ARCHITECTURE 有权用于异步连续逼近的模拟数字转换器（ADC）架构的方法和系统公开(公告)号：US20140022105A1
公开(公告)日：2014-01-23
申请号：US13945579
申请日：2013-07-18
Applicant: MaxLinear, Inc.
Inventor： Xuefeng Chen , Kok Lim Chan , Eric Fogleman , Sheng Ye
IPC: H03M1/38
CPC classification number: H03M1/38 , H03M1/06 , H03M1/0682 , H03M1/125 , H03M1/466
Abstract: A system for processing signals may be configured to detect occurrence of particular errors, comprising meta-stability events, during digital conversion to analog signals, and to handle any detected meta-stability event, such as by adjusting at least a portion of a corresponding digital output based on detection of the meta-stability event. The adjusting of the digital output may comprise setting at least the portion of the digital output, such as to one of a plurality of predefined digital values or patterns. The system may comprise a code generator for generating and/or outputting the predefined digital values or patterns. The system may comprise a selector for adaptively selecting, for portions of the digital output, between output of normal processing path and between predefined values or patterns.
Abstract translation: 用于处理信号的系统可以被配置为在数字转换到模拟信号期间检测包括元稳定性事件的特定错误的发生，并且处理任何检测到的元稳定性事件，例如通过调整相应数字的至少一部分 基于元稳定事件检测的输出。 数字输出的调整可以包括至少设置数字输出的一部分，诸如多个预定数字值或模式之一。 系统可以包括用于生成和/或输出预定数字值或码型的码发生器。 系统可以包括选择器，用于针对数字输出的部分，在正常处理路径的输出之间和预定义的值或模式之间自适应地选择。
-
公开(公告)号：US10187096B2
公开(公告)日：2019-01-22
申请号：US15609946
申请日：2017-05-31
Applicant: Maxlinear, Inc.
Inventor： Subramanian Anantharaman Chandrasekarapuram , Anand Anandakumar , Stephane Laurent-Michel , Sheng Ye , Raja Pullela , Glenn Chang , Vamsi Paidi
Abstract: A system comprises a microwave backhaul outdoor unit having a first resonant circuit, phase error determination circuitry, and phase error compensation circuitry. The first resonant circuit is operable to generate a first signal characterized by a first amount of phase noise and a first amount of temperature stability. The phase error determination circuitry is operable to generate a phase error signal indicative of phase error between the first signal and a second signal, wherein the second signal is characterized by a second amount of phase noise that is greater than the first amount of phase noise, and the second signal is characterized by a second amount of temperature instability that is less than the first amount of temperature instability. The phase error compensation circuitry is operable to adjust the phase of a data signal based on the phase error signal, the adjustment resulting in a phase compensated signal.
-
公开(公告)号：US20180262990A1
公开(公告)日：2018-09-13
申请号：US15976477
申请日：2018-05-10
Applicant: Maxlinear, Inc.
Inventor： James Qiu , Sridhar Ramesh , Sheng Ye , Curtis Ling
CPC classification number: H04W52/0245 , H03G3/20 , H04B1/109 , H04B17/00 , H04L1/20 , H04L27/06 , H04W88/02 , Y02D70/00 , Y02D70/10 , Y02D70/14 , Y02D70/40
Abstract: Methods and systems for providing reduced bandwidth acquisition latency may comprise communicating a reservation request for bandwidth allocation for devices operating under a wired network protocol, where the reservation request may be sent by wired network devices via a wireless network protocol over a wireless network. Bandwidth may be allocated in the wired network for the requesting devices by a network controller. Data may be communicated with the requesting devices via the wired network. The wired network communication protocol may comprise a multimedia over cable alliance (MoCA) standard. The wireless protocol may comprise an IEEE 802.11x standard, a Bluetooth standard, and/or any non-public network protocol. The communication of the reservation request via the wireless protocol may decrease a latency of the wired network. A medium access plan (MAP) may be generated by the network controller based on the reservation request and may comprise a bandwidth allocation for the requesting devices.
-
Patent Agency Ranking
公开(公告)号：US20180191357A1
公开(公告)日：2018-07-05
申请号：US15906578
申请日：2018-02-27
Applicant: Maxlinear, Inc.
Inventor： Sangeetha Gopalakrishnan , Sheng Ye , Vamsi Paidi , Raghava Manas Bachu
CPC classification number: H03L7/085 , H03L7/093 , H03L7/099 , H03L7/1974 , H03L7/1976
Abstract: Methods and systems for a sampled loop filter in a phase locked loop (PLL) may comprise a phase locked loop (PLL) comprising a phase frequency detector, a sampled loop filter comprising a plurality of capacitors and at least one switch, a plurality of voltage controlled oscillators (VCOs) coupled to said sampled loop filter, and a frequency divider. The PLL generates at least one clock signal, and the sampled loop filter samples an output signal from the phase frequency detector when an average of charge provided to a first of the plurality of capacitors in the sampled loop filter is zero. The frequency divider may be a fractional-N divider. A second switch in said sampled loop filter may have switching times that are non-overlapping with switching times of the at least one switch. Capacitors may be coupled to ground from each terminal of the second switch.
-
公开(公告)号：US10003347B2
公开(公告)日：2018-06-19
申请号：US15711177
申请日：2017-09-21
Applicant: Maxlinear, Inc.
Inventor： Eric Fogleman , Sheng Ye , Xuefeng Chen , Kok Lim Chan
Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.
-
公开(公告)号：US20180102780A1
公开(公告)日：2018-04-12
申请号：US15837312
申请日：2017-12-11
Applicant: Maxlinear, Inc.
Inventor： Sheng Ye
CPC classification number: H03L7/093 , H03L7/08 , H03L7/085 , H03L7/0891 , H03L7/18 , H03L2207/10
Abstract: A phase locked loop may be operable to generate, utilizing a frequency multiplier, a reference clock signal whose frequency is an integer M times a frequency of a crystal clock signal and is keyed on both rising and falling edges of the crystal clock signal. The phase locked loop may enable usage of both rising and falling edges of the crystal clock signal, based on the reference clock signal. The phase locked loop may perform an operation of the phase locked loop based on the enabling. The phase locked loop may perform a phase comparison function, based on both rising and falling edges of the crystal clock signal. By utilizing a sampled loop filter in the phase locked loop, the phase locked loop may eliminate, at an output of a charge pump in the phase locked loop, disturbance which is associated with duty cycle errors of the crystal clock signal.
-
69.发明申请公开(公告)号：US20180069562A1
公开(公告)日：2018-03-08
申请号：US15812365
申请日：2017-11-14
Applicant: Maxlinear, Inc.
Inventor： Pawandeep Taluja , Mingrui Zhu , Xuefeng Chen , Anand Anandakumar , Sheng Ye , Timothy Gallagher
CPC classification number: H03M1/0612 , H03M1/1009 , H03M1/1038 , H03M1/1215 , H03M1/50 , H04L7/0087 , H04L25/08 , H04W56/00
Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.
-
公开(公告)号：US09843333B2
公开(公告)日：2017-12-12
申请号：US15363762
申请日：2016-11-29
Applicant: MaxLinear, Inc.
Inventor： Sheng Ye
CPC classification number: H03L7/093 , H03L7/08 , H03L7/085 , H03L7/0891 , H03L7/18 , H03L2207/10
Abstract: A phase locked loop may be operable to generate, utilizing a frequency doubler, a reference clock signal whose frequency is twice a frequency of a crystal clock signal and is keyed on both rising and falling edges of the crystal clock signal. A sampled loop filter (SLPF) in the phase locked loop may capture charge from a charge pump (CHP) in the phase locked loop and the charge is captured at a frequency corresponding to the frequency of the reference clock signal. Opening a switch of the SLPF may hold the captured charge during a phase comparison and closing the switch may release the captured charge. The switch is controlled utilizing a control signal. By utilizing the SLPF in the phase locked loop, the phase locked loop may eliminate, at an output of the CHP, disturbance which is associated with duty cycle errors of the crystal clock signal.
-
-
-
-
-
-
-
-
-
Search Results
84
records
(took 0.02 seconds)
