公开(公告)号：US09872383B1

公开(公告)日：2018-01-16

申请号：US14266636

申请日：2014-04-30

Applicant: Flextronics AP, LLC

Inventor： Weifeng Liu ,  Anwar Mohammed ,  Zhen Feng

IPC: H05K1/00 ,  H05K1/03 ,  H01R4/00 ,  D05B17/00 ,  H01R4/02 ,  H01R43/02 ,  H05K1/18 ,  H05K9/00

CPC classification number: H01M6/40 ,  A41D1/002 ,  A41D1/005 ,  D05B17/00 ,  H01M2/08 ,  H01M6/12 ,  H01M10/0436 ,  H01R4/00 ,  H01R4/02 ,  H01R4/029 ,  H01R43/005 ,  H01R43/02 ,  H01R43/0235 ,  H05K1/0271 ,  H05K1/0296 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/0366 ,  H05K1/0373 ,  H05K1/038 ,  H05K1/0393 ,  H05K1/09 ,  H05K1/11 ,  H05K1/111 ,  H05K1/112 ,  H05K1/115 ,  H05K1/18 ,  H05K1/181 ,  H05K1/189 ,  H05K3/284 ,  H05K3/30 ,  H05K3/305 ,  H05K3/32 ,  H05K3/4015 ,  H05K3/42 ,  H05K3/4644 ,  H05K7/02 ,  H05K9/009 ,  H05K13/04 ,  H05K2201/0154 ,  H05K2201/0158 ,  H05K2201/0162 ,  H05K2201/0287 ,  H05K2201/05 ,  H05K2201/09418 ,  H05K2201/09818

Abstract: An electronics assembly includes one or more electronic components coupled to a fabric. Each electronic component includes one or more electrical connection points, such as a bond pad or solder bump. The electronics assembly also includes one or more electrically conductive wire cloths, one electrically conductive wire cloth coupled to one electrical connection point on an electronic component. The electrically conductive wire cloth is stitched to the fabric by an electrically conductive wire, thereby providing an electrical connection between the electronic component and the electrically conductive wire via the electrically conductive wire cloth.

公开(公告)号：US09812387B2

公开(公告)日：2017-11-07

申请号：US15364143

申请日：2016-11-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li-Chuan Tsai ,  Chih-Cheng Lee

IPC: H05K1/11 ,  H05K1/03 ,  H05K1/16 ,  H05K7/00 ,  H05K1/18 ,  H01L23/498 ,  H05K1/02 ,  H05K3/36 ,  H05K3/00 ,  H05K3/22 ,  H05K3/40 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/19105 ,  H05K1/0266 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K1/183 ,  H05K3/0017 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/22 ,  H05K3/36 ,  H05K3/40 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0158 ,  H05K2201/09472 ,  H05K2201/09527 ,  H05K2201/10204 ,  H05K2203/166 ,  Y02P70/611

Abstract: A semiconductor substrate includes: 1) a first dielectric structure having a first surface and a second surface opposite the first surface; 2) a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure; 3) a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and 4) a second patterned conductive layer, disposed on the second surface of the first dielectric structure and including at least one conductive trace. The first dielectric structure defines at least one opening to expose a portion of the second patterned conductive layer.

公开(公告)号：US20170264804A1

公开(公告)日：2017-09-14

申请号：US15473609

申请日：2017-03-30

Applicant: NINGBO SUNNY OPOTECH CO., LTD.

Inventor： Mingzhu WANG ,  Bojie ZHAO ,  Takehiko TANAKA ,  Nan GUO ,  Zhenyu CHEN ,  Heng JIANG ,  Zhongyu LUAN ,  Fengsheng XI ,  Feifan CHEN ,  Liang DING

IPC: H04N5/225

CPC classification number: H04N5/2257 ,  G02B3/0075 ,  G02B5/201 ,  G02B7/006 ,  G02B7/021 ,  H01L27/14625 ,  H04M1/0264 ,  H04N5/2252 ,  H04N5/2253 ,  H04N5/2254 ,  H04N5/2258 ,  H05K1/0203 ,  H05K1/0274 ,  H05K1/183 ,  H05K1/185 ,  H05K1/189 ,  H05K2201/0141 ,  H05K2201/0158 ,  H05K2201/0175 ,  H05K2201/09036 ,  H05K2201/10121

Abstract: An array imaging module includes a molded photosensitive assembly which includes a supporting member, at least a circuit board, at least two photosensitive units, at least two lead wires, and a mold sealer. The photosensitive units are coupled at the chip coupling area of the circuit board. The lead wires are electrically connected the photosensitive units at the chip coupling area of the circuit board. The mold sealer includes a main mold body and has two optical windows. When the main mold body is formed, the lead wires, the circuit board and the photosensitive units are sealed and molded by the main mold body of the mold sealer, such that after the main mold body is formed, the main mold body and at least a portion of the circuit board are integrally formed together at a position that the photosensitive units are aligned with the optical windows respectively.

公开(公告)号：US20170264803A1

公开(公告)日：2017-09-14

申请号：US15473607

申请日：2017-03-30

Applicant: NINGBO SUNNY OPOTECH CO., LTD.

Inventor： Mingzhu WANG ,  Bojie ZHAO ,  Takehiko TANAKA ,  Nan GUO ,  Zhenyu CHEN ,  Heng JIANG ,  Zhongyu LUAN ,  Fengsheng XI ,  Feifan CHEN ,  Liang DING

IPC: H04N5/225 ,  B29C45/14 ,  G02B5/20 ,  G02B3/00 ,  G02B7/00

CPC classification number: H04N5/2257 ,  G02B3/0075 ,  G02B5/201 ,  G02B7/006 ,  G02B7/021 ,  H01L27/14625 ,  H04M1/0264 ,  H04N5/2252 ,  H04N5/2253 ,  H04N5/2254 ,  H04N5/2258 ,  H05K1/0203 ,  H05K1/0274 ,  H05K1/183 ,  H05K1/185 ,  H05K1/189 ,  H05K2201/0141 ,  H05K2201/0158 ,  H05K2201/0175 ,  H05K2201/09036 ,  H05K2201/10121

Abstract: An array imaging module includes a molded photosensitive assembly which includes a supporting member, at least a circuit board, at least two photosensitive units, at least two lead wires, and a mold sealer. The photosensitive units are coupled at the chip coupling area of the circuit board. The lead wires are electrically connected the photosensitive units at the chip coupling area of the circuit board. The mold sealer includes a main mold body and has two optical windows. When the main mold body is formed, the lead wires, the circuit board and the photosensitive units are sealed and molded by the main mold body of the mold sealer, such that after the main mold body is formed, the main mold body and at least a portion of the circuit board are integrally formed together at a position that the photosensitive units are aligned with the optical windows respectively.

公开(公告)号：US09596753B2

公开(公告)日：2017-03-14

申请号：US15240958

申请日：2016-08-18

Applicant: NOVOSET, LLC

Inventor： Sajal Das ,  Patrick Shipman

IPC: H05K1/03 ,  C08F279/02 ,  C08J5/24 ,  C08F283/12 ,  B32B15/06 ,  B32B25/02 ,  B32B15/20

CPC classification number: H05K1/0326 ,  B32B15/06 ,  B32B15/20 ,  B32B25/02 ,  B32B2307/204 ,  B32B2457/08 ,  C08F279/02 ,  C08F283/12 ,  C08J5/24 ,  C08J2351/00 ,  C08J2351/08 ,  H05K1/0346 ,  H05K1/0366 ,  H05K2201/015 ,  H05K2201/0158 ,  H05K2201/0162

Abstract: An ultra low loss dielectric thermosetting resin composition has at least one cyanate ester component (A) and at least one reactive intermediate component (B) that is capable of copolymerization with said component (A). The invention is a cyanate ester resin of the form: Tn-[W-(Z)f/(H)1−f-W]n−1-[W-(Z)f/(H)1−f-(OCN)f/(R)1−f]n+2, wherein T is a 1,3,5-substituted-triazine moiety (C3N3); W is a linking atom between triazine and either component A or component B; Z is component (A); H is component (B); OCN is a cyanate ester end group; R is a reactive end group of component B; n is an integer greater than or equal to 1; and f is a weight or mole fraction of component A. The composition exhibits excellent dielectric properties and yields a high performance laminate for use in high layer count, multilayer printed circuit board (PCB), prepregs, resin coated copper (RCC), film adhesives, high frequency radomes, radio frequency (RF) laminates and various composites.

Abstract translation: 超低损耗介电热固性树脂组合物具有至少一种能够与所述组分（A）共聚的氰酸酯组分（A）和至少一种反应性中间组分（B）。 本发明是以下形式的氰酸酯树脂：Tn- [W-（Z）f /（H）1-fW] n-1- [W-（Z）f /（H）1-f-（OCN） f /（R）1-f] n + 2，其中T是1,3,5-取代三嗪部分（C 3 N 3）; W是三嗪与组分A或组分B之间的连接原子; Z是组分（A）; H是组分（B）; OCN是氰酸酯端基; R是组分B的反应性端基; n是大于或等于1的整数; 并且f是组分A的重量或摩尔分数。组合物显示出优异的介电性能并产生用于高层计数，多层印刷电路板（PCB），预浸料，树脂涂层铜（RCC），膜粘合剂 ，高频雷达，射频（RF）层压板和各种复合材料。

公开(公告)号：US20170019993A1

公开(公告)日：2017-01-19

申请号：US14798384

申请日：2015-07-13

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Li-Chuan TSAI ,  Chih-Cheng LEE

IPC: H05K1/11 ,  H05K1/18 ,  H05K3/40 ,  H05K3/00 ,  H05K3/22 ,  H05K1/02 ,  H05K3/36

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/19105 ,  H05K1/0266 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K1/183 ,  H05K3/0017 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/22 ,  H05K3/36 ,  H05K3/40 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0158 ,  H05K2201/09472 ,  H05K2201/09527 ,  H05K2201/10204 ,  H05K2203/166 ,  Y02P70/611

Abstract: The present disclosure relates to a semiconductor substrate, a semiconductor module and a method for manufacturing the same. The semiconductor substrate includes a first dielectric structure, a second dielectric structure, a first patterned conductive layer and a second patterned conductive layer. The first dielectric structure has a first surface and a second surface opposite the first surface. The second dielectric structure has a third surface and a fourth surface opposite the third surface, where the fourth surface is adjacent to the first surface. The second dielectric structure defines a through hole extending from the third surface to the fourth surface. A cavity is defined by the through hole and the first dielectric structure. The first patterned conductive layer is disposed on the first surface of the first dielectric structure. The second patterned conductive layer is disposed on the second surface of the first dielectric structure.

Abstract translation: 本公开涉及半导体衬底，半导体模块及其制造方法。 半导体衬底包括第一电介质结构，第二电介质结构，第一图案化导电层和第二图案化导电层。 第一电介质结构具有与第一表面相对的第一表面和第二表面。 第二电介质结构具有与第三表面相对的第三表面和第四表面，其中第四表面与第一表面相邻。 第二电介质结构限定了从第三表面延伸到第四表面的通孔。 空腔由通孔和第一电介质结构限定。 第一图案化导电层设置在第一电介质结构的第一表面上。 第二图案化导电层设置在第一介电结构的第二表面上。

公开(公告)号：US20160316556A1

公开(公告)日：2016-10-27

申请号：US14692559

申请日：2015-04-21

Applicant: NORTHROP GRUMMAN SYSTEMS CORPORATION

Inventor： Daniel J. Braley ,  Eric G. Barnes ,  Pedro Gonzalez

IPC: H05K1/09 ,  B29C67/00 ,  H05K1/03 ,  H05K3/10

CPC classification number: H05K1/09 ,  B29C64/106 ,  B29K2023/0666 ,  B29K2305/00 ,  B29L2031/3425 ,  B33Y70/00 ,  B33Y80/00 ,  H05K1/032 ,  H05K1/0393 ,  H05K3/10 ,  H05K3/1241 ,  H05K3/4664 ,  H05K2201/0129 ,  H05K2201/0158 ,  H05K2203/0126

Abstract: An electronic component, such as a circuit board, fabricated by coextruding an Ultra High Molecular Weight Polyethylene (UHMWPE) filament, such as a Dyneema® filament, and a conductive material, such as an Indalloy wire, using only a three-dimensional printer, such as an FDM machine.

Abstract translation: 通过使用仅使用三维打印机共挤出超高分子量聚乙烯（UHMWPE）丝，例如Dyneema灯丝和导电材料（例如Indalloy线）制造的诸如电路板的电子部件， 例如FDM机器。

公开(公告)号：US09265160B2

公开(公告)日：2016-02-16

申请号：US14099207

申请日：2013-12-06

Applicant: Rogers Corporation

Inventor： Sankar Paul ,  Scott D. Kennedy ,  Dirk M. Baars

IPC: H05K3/46 ,  B32B7/12 ,  B32B15/14 ,  C08G65/48 ,  C08L71/12 ,  C09J107/00 ,  C09J113/00 ,  C09J171/12 ,  H05K3/00 ,  C08K3/00 ,  C08L9/00 ,  C08L13/00 ,  C08L15/00 ,  C08L19/00 ,  C08L51/04 ,  H05K1/03

CPC classification number: H05K3/4626 ,  B32B3/04 ,  B32B3/08 ,  B32B3/18 ,  B32B3/30 ,  B32B5/08 ,  B32B5/16 ,  B32B5/30 ,  B32B7/12 ,  B32B15/06 ,  B32B15/08 ,  B32B15/14 ,  B32B15/16 ,  B32B15/20 ,  B32B25/08 ,  B32B25/14 ,  B32B27/08 ,  B32B27/12 ,  B32B27/14 ,  B32B27/20 ,  B32B27/26 ,  B32B27/285 ,  B32B27/302 ,  B32B27/32 ,  B32B27/38 ,  B32B2255/10 ,  B32B2255/205 ,  B32B2260/025 ,  B32B2260/046 ,  B32B2262/0269 ,  B32B2262/101 ,  B32B2262/14 ,  B32B2264/10 ,  B32B2264/102 ,  B32B2264/104 ,  B32B2264/12 ,  B32B2270/00 ,  B32B2307/202 ,  B32B2307/204 ,  B32B2307/30 ,  B32B2307/302 ,  B32B2307/3065 ,  B32B2307/308 ,  B32B2307/7265 ,  B32B2457/00 ,  B32B2457/08 ,  C08G65/485 ,  C08K3/013 ,  C08L9/00 ,  C08L13/00 ,  C08L15/00 ,  C08L19/006 ,  C08L51/04 ,  C08L71/12 ,  C08L71/126 ,  C08L2666/08 ,  C08L2666/14 ,  C09J107/00 ,  C09J113/00 ,  C09J171/12 ,  H05K1/0393 ,  H05K3/00 ,  H05K3/462 ,  H05K3/4641 ,  H05K3/4676 ,  H05K2201/0133 ,  H05K2201/0158 ,  H05K2201/0355 ,  H05K2201/10378 ,  Y10T156/10 ,  Y10T428/24802 ,  Y10T428/263 ,  Y10T428/31544 ,  Y10T428/31931 ,  C08L2666/04

Abstract: A circuit subassembly, comprising a dielectric layer formed from a dielectric composition comprising, based on the total volume of the composition: about 15 to about 65 volume percent of a dielectric filler; and about 35 to about 85 volume percent of a thermosetting composition comprising: a poly(arylene ether), and a carboxy-functionalized polybutadiene or polyisoprene polymer.

Abstract translation: 一种电路子组件，包括由电介质组合物形成的电介质层，所述电介质层包含基于所述组合物的总体积：约15至约65体积％的介电填料; 和约35至约85体积％的热固性组合物，其包含：聚（亚芳基醚）和羧基官能化聚丁二烯或聚异戊二烯聚合物。

公开(公告)号：US20150220010A1

公开(公告)日：2015-08-06

申请号：US14416453

申请日：2012-07-23

Applicant: Yaron Grinwald ,  Gideon Amir ,  Rita Reznikov ,  Reut Avigdor ,  Haim Gefen ,  Gil Bar-Haim ,  Mark Sandler ,  Dror Kella

Inventor： Yaron Grinwald ,  Gideon Amir ,  Rita Reznikov ,  Reut Avigdor ,  Haim Gefen ,  Gil Bar-Haim ,  Mark Sandler ,  Dror Kella

IPC: G03G9/087 ,  H05K1/09 ,  H05K1/03

CPC classification number: H01B1/24 ,  B05D5/12 ,  C08L23/0869 ,  C08L33/02 ,  C09D7/70 ,  C09D11/037 ,  C09D11/106 ,  C09D11/52 ,  G03G9/0827 ,  G03G9/08704 ,  G03G9/08733 ,  H05K1/09 ,  H05K2201/0158 ,  H05K2201/0323

Abstract: The present disclosure is drawn to an electrostatic ink composition comprising a resin and an elongate conductive species. Also disclosed herein is a substrate on which is electrostatically printed a conductive trace, wherein the trace comprises a resin and an elongate conductive species. Further disclosed herein is a method of electrophotographic printing an electrostatic ink composition comprising a resin and an elongate conductive species.

Abstract translation: 本公开涉及包含树脂和细长导电种类的静电墨水组合物。 本文还公开了在其上静电印刷导电迹线的基底，其中痕迹包括树脂和细长的导电物质。 本文进一步公开的是电子照相印刷包含树脂和细长导电种类的静电墨水组合物的方法。

公开(公告)号：US20150098196A1

公开(公告)日：2015-04-09

申请号：US14400261

申请日：2012-05-18

Applicant: Logan Peter Palmer

Inventor： Logan Peter Palmer

IPC: H05K1/18 ,  H05K3/00

CPC classification number: H05K1/189 ,  H05K3/0091 ,  H05K3/284 ,  H05K3/4691 ,  H05K9/0022 ,  H05K2201/0158 ,  H05K2201/0162 ,  H05K2201/042 ,  H05K2201/055 ,  H05K2201/056 ,  Y10T29/49124

Abstract: Printed circuit board apparatus with electromagnetic interference shields and methods of making the same.

Abstract translation: 具有电磁干扰屏蔽的印刷电路板装置及其制造方法。