公开(公告)号：US20120097429A1

公开(公告)日：2012-04-26

申请号：US13191807

申请日：2011-07-27

Applicant: Pao-Hung Chou ,  Hsien-Min Chang

Inventor： Pao-Hung Chou ,  Hsien-Min Chang

IPC: H05K1/11 ,  H05K3/10 ,  C25D1/00

CPC classification number: H01L23/49811 ,  C25D5/02 ,  C25D7/12 ,  H01L21/4853 ,  H01L23/3128 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/181 ,  H05K1/111 ,  H05K3/0097 ,  H05K3/107 ,  H05K3/282 ,  H05K2201/0376 ,  H05K2203/1536 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A package substrate includes: a dielectric layer having two opposite surfaces; a wiring layer embedded in the dielectric layer and exposed from the two opposite surfaces of the dielectric layer, wherein the wiring layer has solder pads, conductive pads and circuit wires electrically connecting the solder pads and the conductive pads; and a first insulating protection layer disposed on one of the two opposite surfaces of the dielectric layer to cover the dielectric layer and the wiring layer and having a plurality of openings for exposing the conductive pads, respectively. The package substrate, by directly using the dielectric layer as a base, provides a package substrate having reduced thickness and lower fabrication costs compared to the prior art.

Abstract translation: 封装基板包括：具有两个相对表面的电介质层; 介于所述电介质层中并且从所述电介质层的两个相对表面露出的布线层，其中所述布线层具有焊接焊盘，导电焊盘和电连接所述焊盘和所述导电焊盘的电路线; 以及第一绝缘保护层，其设置在电介质层的两个相对表面之一上以覆盖电介质层和布线层，并且具有多个用于暴露导电焊盘的开口。 通过直接使用电介质层作为基底，封装衬底提供了与现有技术相比具有减小的厚度和较低制造成本的封装衬底。

公开(公告)号：US20120092816A1

公开(公告)日：2012-04-19

申请号：US13202176

申请日：2010-10-13

Applicant: Jonas Moran ,  Mats Kleverman

Inventor： Jonas Moran ,  Mats Kleverman

IPC: H05K5/00 ,  H05K13/00

CPC classification number: G06F3/0202 ,  H03K17/9645 ,  H05K1/0275 ,  H05K1/053 ,  H05K1/115 ,  H05K1/116 ,  H05K1/162 ,  H05K1/167 ,  H05K3/0026 ,  H05K3/4015 ,  H05K3/4046 ,  H05K3/445 ,  H05K2201/0108 ,  H05K2201/0376 ,  H05K2201/09545 ,  H05K2201/09609 ,  H05K2201/09836 ,  H05K2201/0999 ,  H05K2201/10121 ,  H05K2201/10151 ,  H05K2203/107

Abstract: An electronic device comprises a housing having an outer face and an inner face. A key is provided on the housing, which comprises a micro hole formed in the housing and a conductive material extending within the micro hole to the outer face of the housing. A sensor is coupled to the conductive material to detect whether an object is brought into contact or out of contact with the micro hole at the outer face.

Abstract translation: 电子设备包括具有外表面和内表面的壳体。 在壳体上设有钥匙，该钥匙包括形成在壳体中的微孔和在微孔内延伸到壳体外表面的导电材料。 传感器耦合到导电材料，以检测物体是否与外表面的微孔接触或脱离接触。

公开(公告)号：US08158891B2

公开(公告)日：2012-04-17

申请号：US11898103

申请日：2007-09-10

Applicant: Chao-Wen Shih

Inventor： Chao-Wen Shih

IPC: H05K1/11

CPC classification number: H05K3/465 ,  H05K3/0023 ,  H05K3/0035 ,  H05K3/045 ,  H05K2201/0376 ,  Y10T29/49155

Abstract: A circuit board disclosed in the present invention includes a core board on which a first circuit layer is placed, wherein the first circuit layer has a plurality of conductive pads; and at least one built-up structure covering the surface of the circuit board, which comprises a dielectric layer, a second circuit layer, and a plurality of conductive vias without being surrounded by annular metal rings. The conductive vias are conducted with the conductive pads of the first circuit layer and the second circuit layer. Besides, the surface of the second circuit layer is in the same height as the surface of the dielectric layer. Also, the present invention provides a method for manufacturing the above-mentioned circuit board structure. Therefore, a circuit board having fine circuits can be formed, and the shape of the circuit can be ensured efficiently. Moreover, electric performances of the circuit board can be improved.

Abstract translation: 本发明公开的电路板包括其上放置有第一电路层的芯板，其中第一电路层具有多个导电焊盘; 以及覆盖电路板的表面的至少一个堆积结构，其包括介电层，第二电路层和多个导电通孔，而不被环形金属环包围。 导电通孔与第一电路层和第二电路层的导电焊盘一起导电。 此外，第二电路层的表面与介电层的表面的高度相同。 此外，本发明提供一种制造上述电路板结构的方法。 因此，可以形成具有精细电路的电路板，并且可以有效地确保电路的形状。 此外，可以提高电路板的电气性能。

公开(公告)号：US08110918B2

公开(公告)日：2012-02-07

申请号：US10864870

申请日：2004-06-10

Applicant: Kyoung-sei Choi

Inventor： Kyoung-sei Choi

IPC: H01L23/12

CPC classification number: H01L21/4846 ,  H01L21/3122 ,  H01L23/3107 ,  H01L23/4985 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H05K1/0393 ,  H05K3/045 ,  H05K3/06 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/243 ,  H05K3/28 ,  H05K3/388 ,  H05K2201/0108 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K2203/0108 ,  Y10T29/49227 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A flexible substrate used in a semiconductor package, a method of manufacturing the same, and a semiconductor package including the flexible substrate. A circuit pattern forming region is formed in an insulating substrate with a dented shape and a circuit pattern formed of a metallic material is formed in the circuit pattern forming region.

Abstract translation: 用于半导体封装的柔性衬底，其制造方法以及包括柔性衬底的半导体封装。 电路图案形成区域形成在具有凹陷形状的绝缘基板中，并且在电路图案形成区域中形成由金属材料形成的电路图案。

公开(公告)号：US20110120756A1

公开(公告)日：2011-05-26

申请号：US13006122

申请日：2011-01-13

Applicant: Tsugio AMBO ,  Satoru Fujiwara ,  Yoshikatsu Hasegawa ,  Chihiro Nakagawa ,  Takeshi Ono ,  Atsushi Urushidani ,  Tooru Kashioka ,  Katsuji Shimazawa

Inventor： Tsugio AMBO ,  Satoru Fujiwara ,  Yoshikatsu Hasegawa ,  Chihiro Nakagawa ,  Takeshi Ono ,  Atsushi Urushidani ,  Tooru Kashioka ,  Katsuji Shimazawa

IPC: H05K1/02 ,  H05K3/10

CPC classification number: H05K3/202 ,  H01R9/2466 ,  H01R12/523 ,  H05K3/041 ,  H05K3/222 ,  H05K3/308 ,  H05K3/326 ,  H05K3/328 ,  H05K3/4046 ,  H05K3/4611 ,  H05K13/0061 ,  H05K2201/0376 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/091 ,  H05K2201/096 ,  H05K2201/10287 ,  H05K2201/10401 ,  H05K2201/1059 ,  H05K2201/10598 ,  H05K2203/081 ,  H05K2203/082 ,  H05K2203/167 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T428/24917

Abstract: A circuit board includes a foil circuit provided on a synthetic resin plate formed by injection molding, made of a copper foil, and having a pattern different for the circuit board. Anchor pins projecting upward are provided on the resin plate and passed through pinholes made in the foil circuit. The foil circuit is positioned and secured to the resin plate. In a required portion of the resin plate, a terminal insertion hole is provided, and a receiving terminal is secured to the required portion of the terminal insertion hole and connected to the foil circuit.

公开(公告)号：US20110108313A1

公开(公告)日：2011-05-12

申请号：US12646384

申请日：2009-12-23

Applicant: Chen-Yueh Kung

Inventor： Chen-Yueh Kung

IPC: H05K1/11 ,  B44C1/22

CPC classification number: H05K3/4007 ,  H01L2924/0002 ,  H05K3/0035 ,  H05K3/062 ,  H05K3/108 ,  H05K3/243 ,  H05K3/28 ,  H05K3/421 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09436 ,  H05K2201/09545 ,  H05K2203/0361 ,  H05K2203/0554 ,  H05K2203/0574 ,  H05K2203/1152 ,  H05K2203/308 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A circuit substrate includes a base layer, a patterned conductive layer, a dielectric layer, an outer pad and a conductive block. The patterned conductive layer is disposed on the base layer and has an inner pad. The dielectric layer is disposed on the base layer and covers the patterned conductive layer. The outer pad is disposed on the dielectric layer. The conductive layer is passed through the dielectric layer and connected between the outer pad and the inner pad, wherein the outer pad and the conductive block are formed as an integrative unit, and an outer diameter of the outer pad is substantially equal to an outer diameter of the conductive block. In addition, a fabricating process for the circuit substrate is also provided.

Abstract translation: 电路基板包括基底层，图案化导电层，电介质层，外部焊盘和导电块。 图案化导电层设置在基底层上并具有内部衬垫。 电介质层设置在基底层上并覆盖图案化的导电层。 外垫设置在电介质层上。 导电层通过电介质层并连接在外焊盘和内焊盘之间，其中外焊盘和导电块形成为整体单元，外焊盘的外径基本上等于外焊盘 的导电块。 此外，还提供了用于电路基板的制造工艺。

公开(公告)号：US20110061231A1

公开(公告)日：2011-03-17

申请号：US12631594

申请日：2009-12-04

Applicant: Mi Sun HWANG ,  Myung Sam KANG ,  Ok Tae KIM ,  Seon Ha KANG ,  Gil Yong SHIN ,  Kil Yong YUN ,  Min Jung CHO

Inventor： Mi Sun HWANG ,  Myung Sam KANG ,  Ok Tae KIM ,  Seon Ha KANG ,  Gil Yong SHIN ,  Kil Yong YUN ,  Min Jung CHO

IPC: H05K3/36 ,  H05K3/10

CPC classification number: H05K3/4685 ,  H05K3/0097 ,  H05K3/205 ,  H05K3/421 ,  H05K2201/0376 ,  H05K2203/0152 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Disclosed herein is a method of manufacturing a printed circuit board, comprising: preparing a first carrier including a first pattern formed on one side thereof; preparing a second carrier including a first solder resist layer and a second pattern sequentially formed on one side thereof; pressing the first carrier and the second carrier such that the first pattern is embedded in one side of an insulation layer and the second pattern is embedded in the other side of the insulation layer and then removing the first carrier and the second carrier to fabricate two substrates; attaching the two substrates to each other using an adhesion layer such that the first solder resist layers face each other; and forming a via for connecting the first pattern with the second pattern in the insulation layer, forming a second solder resist on the insulation layer provided with the first pattern, and then removing the adhesion layer.

Abstract translation: 本文公开了一种制造印刷电路板的方法，包括：制备第一载体，其包括在其一侧上形成的第一图案; 制备包括在其一侧上顺序形成的第一阻焊层和第二图案的第二载体; 按压第一载体和第二载体，使得第一图案嵌入绝缘层的一侧，并且将第二图案嵌入绝缘层的另一侧，然后移除第一载体和第二载体以制造两个基板 ; 使用粘合层将两个基板彼此连接，使得第一阻焊层彼此面对; 以及形成用于在绝缘层中连接第一图案与第二图案的通孔，在设置有第一图案的绝缘层上形成第二阻焊剂，然后除去粘合层。

公开(公告)号：US07902463B2

公开(公告)日：2011-03-08

申请号：US11844788

申请日：2007-08-24

Applicant: Michimasa Takahashi ,  Yukinobu Mikado ,  Hiroyuki Yanagisawa

Inventor： Michimasa Takahashi ,  Yukinobu Mikado ,  Hiroyuki Yanagisawa

IPC: H05K1/00

CPC classification number: H05K1/167 ,  H05K3/205 ,  H05K3/4644 ,  H05K2201/0376 ,  H05K2201/09736 ,  H05K2203/1453

Abstract: A printed wiring board includes an insulation layer having a surface, electrodes embedded in the insulation layer, a resistor formed on the surface of the insulation layer and electrically connected to the electrodes, and an external connection conductive pattern formed over the surface of the insulation layer and electrically connected to one or more electrodes. The insulation layer and the electrodes form a component-mounting surface on the surface of the insulation layer, the component-mounting surface is substantially leveled with the surface of the insulation layer and includes a resistor forming region on which the resistor is formed, and the external connection conductive pattern is separated by a space from the resistor.

Abstract translation: 印刷电路板包括具有表面的绝缘层，嵌入在绝缘层中的电极，形成在绝缘层的表面上并电连接到电极的电阻器，以及形成在绝缘层表面上的外部连接导电图案 并电连接到一个或多个电极。 绝缘层和电极在绝缘层的表面上形成部件安装表面，部件安装表面与绝缘层的表面基本平齐，并且包括形成电阻器的电阻器形成区域，并且 外部连接导体图案与电阻器隔开一个空间。

公开(公告)号：US20110003086A1

公开(公告)日：2011-01-06

申请号：US12747331

申请日：2008-12-10

Applicant: Kwang Choon Chung ,  Ji Hoon Yoo ,  Byung Hun Kim ,  Su Han Kim

Inventor： Kwang Choon Chung ,  Ji Hoon Yoo ,  Byung Hun Kim ,  Su Han Kim

IPC: B05D3/06

CPC classification number: H05K3/1258 ,  C23C18/165 ,  C23C18/1868 ,  C23C18/204 ,  H05K1/092 ,  H05K1/097 ,  H05K3/0026 ,  H05K3/107 ,  H05K3/245 ,  H05K2201/0112 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K2203/0568 ,  H05K2203/072 ,  H05K2203/0723 ,  H05K2203/1126

Abstract: The present invention relates to a method for fabricating blackened conductive patterns, which includes (i) forming a resist layer on a non-conductive substrate; (ii) forming fine pattern grooves in the resist layer using a laser beam; (iii) forming a mixture layer containing a conductive material and a blackening material in the fine pattern grooves; and (iv) removing the resist layer remained on the non-conductive substrate.

Abstract translation: 本发明涉及一种制造黑化导电图案的方法，其包括（i）在非导电基底上形成抗蚀剂层; （ii）使用激光束在抗蚀剂层中形成精细图案凹槽; （iii）在精细图案槽中形成含有导电材料和变黑材料的混合层; 和（iv）去除残留在非导电基底上的抗蚀剂层。

公开(公告)号：US20100139960A1

公开(公告)日：2010-06-10

申请号：US12379307

申请日：2009-02-18

Applicant: Seok Hwan Ahn ,  Young Gwan Ko

Inventor： Seok Hwan Ahn ,  Young Gwan Ko

IPC: H05K1/00 ,  H05K1/11

CPC classification number: H05K3/107 ,  H05K3/0032 ,  H05K3/045 ,  H05K3/426 ,  H05K2201/0376 ,  H05K2201/0959 ,  H05K2203/025 ,  H05K2203/1461

Abstract: Disclosed is a printed circuit board having a plating pattern buried in a via and a method of manufacturing the same. The method of manufacturing the printed circuit board includes forming a negative pattern for forming a plating pattern, thus remarkably reducing the generation of plating thickness deviation in a plating process for forming a circuit pattern, and the printed circuit board has improved electrical signal transmission properties.

Abstract translation: 公开了一种印刷电路板及其制造方法。 制造印刷电路板的方法包括形成用于形成电镀图案的负图案，从而显着减少了用于形成电路图案的电镀工艺中电镀厚度偏差的产生，并且印刷电路板具有改善的电信号传输性能。