公开(公告)号：US07145779B2

公开(公告)日：2006-12-05

申请号：US11009250

申请日：2004-12-10

Applicant: Shih-Hsiung Lien

Inventor： Shih-Hsiung Lien

IPC: H05K7/10 ,  H05K7/02

CPC classification number: H05K1/142 ,  H05K2201/09172 ,  H05K2201/09181 ,  H05K2201/09963 ,  H05K2201/10159 ,  H05K2201/209

Abstract: A memory module includes a plurality of memory units and an assembling holder. Each of the memory units includes a memory substrate, at least a memory chipset having a predetermined memory capacity mounted on the memory substrate, and an electric terminal provided at a lower edge portion of the memory substrate. The assembling holder includes an elongated unit housing having an elongated receiving slot extended therealong and a signal terminal provided along the unit housing, wherein the electric terminals of the memory substrates are detachably inserted into the receiving slot of the unit housing to electrically connect the electric terminals with the signal terminal, such that the memory units are alignedly and detachably mounted along the receiving slot in an edge to edge manner.

Abstract translation: 存储器模块包括多个存储器单元和组装保持器。 每个存储器单元包括存储器基板，至少存储器芯片组具有安装在存储器基板上的预定存储器容量，以及设置在存储器基板的下边缘部分处的电端子。 组装保持器包括细长单元壳体，其具有沿其延伸的细长接收槽和沿单元壳体设置的信号端子，其中存储器基板的电端子可拆卸地插入到单元壳体的接收槽中，以电连接电端子 信号端子，使得存储器单元沿着接收槽以边缘到边缘的方式对齐地和可拆卸地安装。

公开(公告)号：US20060170090A1

公开(公告)日：2006-08-03

申请号：US11339352

申请日：2006-01-25

Applicant: Yasuhiro Shinma ,  Masanori Onodera ,  Kouichi Meguro ,  Koji Taya ,  Junji Tanaka ,  Junichi Kasai

Inventor： Yasuhiro Shinma ,  Masanori Onodera ,  Kouichi Meguro ,  Koji Taya ,  Junji Tanaka ,  Junichi Kasai

IPC: H01L23/02

CPC classification number: H05K1/144 ,  H01L23/49827 ,  H01L23/5387 ,  H01L24/73 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/01004 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/023 ,  H05K1/147 ,  H05K1/189 ,  H05K3/361 ,  H05K3/403 ,  H05K2201/09181 ,  H05K2201/10515 ,  H05K2201/10734 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A stacked type semiconductor device includes semiconductor devices, interposers by which the semiconductor devices are stacked, the interposers having electrodes provided on sides thereof, and a connection substrate connecting the electrodes together. The electrodes provided on the sides of the interposers may be connected to the connection substrate by one of an electrically conductive adhesive or an anisotropically conductive film.

Abstract translation: 堆叠型半导体器件包括半导体器件，半导体器件堆叠的插入器，具有设置在其侧面上的电极的插入器以及将电极连接在一起的连接基板。 设置在插入件侧面的电极可以通过导电粘合剂或各向异性导电膜中的一种连接到连接基板。

公开(公告)号：US20060126316A1

公开(公告)日：2006-06-15

申请号：US11344251

申请日：2006-02-01

Applicant: Kouichi Takagi ,  Fumiaki Mizuno

Inventor： Kouichi Takagi ,  Fumiaki Mizuno

IPC: H05K3/30 ,  H05K3/34

CPC classification number: H05K7/20854 ,  H05K3/202 ,  H05K3/3405 ,  H05K3/403 ,  H05K3/42 ,  H05K2201/0352 ,  H05K2201/0391 ,  H05K2201/09181 ,  Y10T29/49133 ,  Y10T29/49144

Abstract: A control circuit board has an end portion formed with a cut that is opened sideways. The cut is coated with a conductor layer. Upon connecting the control circuit board to a conductor such as a bus bar, solder is supplied so as to bridge the conductor layer and the bus bar in a state that the conductor layer is laid on the bus bar.

Abstract translation: 控制电路板具有形成有横向打开的切口的端部。 切口涂有导体层。 在将控制电路板连接到诸如母线的导体时，提供焊料以使导体层和母线在导体层铺设在母线上的状态下桥接。

公开(公告)号：US20060118330A1

公开(公告)日：2006-06-08

申请号：US11295520

申请日：2005-12-07

Applicant: Yasunari Ooyabu ,  Yasuhito Ohwaki

Inventor： Yasunari Ooyabu ,  Yasuhito Ohwaki

IPC: H05K1/14

CPC classification number: H05K3/363 ,  H05K1/056 ,  H05K3/3442 ,  H05K3/366 ,  H05K2201/0394 ,  H05K2201/09181 ,  H05K2203/167

Abstract: A wired circuit board that can allow precise connection between wired circuit boards with respect to a direction orthogonal to each other with a simple structure, while allowing reduction in size of the wired circuit boards, and a connecting structure of the wired circuit board comprising two wired circuit boards connected to each other with respect to a direction orthogonal to each other. Relay terminals 9 of the circuit suspension board 1 are arranged along one widthwise edge of the circuit suspension board 1, and terminal cutouts 10 cut in a generally semicircular arc shape from one edge thereof toward an widthwise inside thereof are formed in the relay terminals 9. In addition, insulating base layer cutouts 12 are formed in the first insulating base layer 3 to correspond to the terminal cutouts 10. The circuit suspension board 1 and a flexible wired circuit board for relay 21 are electrically connected to each other by fitting bumps 29 formed on suspension terminals 26 of the flexible wired circuit board for relay 21 in the terminal cutouts 10.

公开(公告)号：US20060084291A1

公开(公告)日：2006-04-20

申请号：US11246167

申请日：2005-10-11

Applicant: Masuoka Hironobu ,  Yoshida Ryuji ,  Hanabusa Kazuyoshi

Inventor： Masuoka Hironobu ,  Yoshida Ryuji ,  Hanabusa Kazuyoshi

IPC: H01R12/00

CPC classification number: H05K3/3405 ,  H01R4/02 ,  H01R4/04 ,  H01R12/57 ,  H01R12/58 ,  H01R12/721 ,  H05K3/0052 ,  H05K3/3447 ,  H05K3/403 ,  H05K2201/09181 ,  H05K2201/09854 ,  H05K2201/1034

Abstract: A mounting structure for mounting a terminal at a circuit board, which allows the terminal to be mounted at the circuit board easily by using an automatic mounter and facilitates inspection of the bonding state at the mounting area where the terminal is mounted at another board, is provided. The mounting structure for a circuit board terminal also assures a sufficient level of strength at the terminal mounting area, reduces the electrical resistance and improves the usable area ratio at the circuit board. According to the present invention, one or a plurality of recessed electrodes (1a) are formed at an end of a circuit board (1) in correspondence to each terminal. One or a plurality of hollow through electrodes (1b) are disposed near the recessed electrodes (1a) at the circuit board (1) in correspondence to each terminal. A mounting portion (4b) of each terminal (4) which is mounted at the circuit board (1), includes a first vertical portion (4c), a horizontal portion (4d) and a second vertical portion (4e) formed by bending the front end of the horizontal portion (4d). The first vertical portion (4c) is fitted at the recessed electrodes (1a) at the circuit board (1) and is then bonded to the circuit board (1) via a conductive bonding material. The second vertical portion (4e) is inserted at the through electrodes (1b) and is then bonded via a conductive bonding material.

Abstract translation: 一种用于将端子安装在电路板上的安装结构，其允许通过使用自动安装器容易地将端子安装在电路板上，并且便于检查端子安装在另一个板上的安装区域的接合状态。 提供。 电路板端子的安装结构也确保端子安装区域的强度足够的水平，降低电阻并提高电路板的可用面积比。 根据本发明，对应于每个端子，在电路板（1）的一端形成一个或多个凹陷电极（1a）。 一对或多个中空贯通电极（1b）设置在电路板（1）的与每个端子对应的凹陷电极（1a）附近。 安装在电路板（1）上的每个端子（4）的安装部分（4b）包括第一垂直部分（4c），水平部分（4d）和第二垂直部分（4e） 通过弯曲水平部分（4d）的前端而形成。 第一垂直部分（4c）装配在电路板（1）的凹陷电极（1a）处，然后通过导电接合材料结合到电路板（1）上。 第二垂直部分（4e）插入通孔（1b），然后通过导电接合材料接合。

公开(公告)号：US20050253681A1

公开(公告)日：2005-11-17

申请号：US10506947

申请日：2002-03-25

Applicant: Eiji Kobayashi

Inventor： Eiji Kobayashi

IPC: H01C1/01 ,  H01G2/06 ,  H05K3/34

CPC classification number: H01G2/065 ,  H01C1/01 ,  H05K3/3442 ,  H05K2201/09181 ,  H05K2201/09781 ,  H05K2201/10045 ,  Y02P70/613

Abstract: A surface mounting chip network component in which a network having three or more odd number of terminals are formed on the surface of an insulating substrate and Tomb Stone Phenomenon is suppressed. Even number of network circuits are formed on the surface of the insulating substrate (2) and the same number of terminals (1) are arranged, respectively, on the opposite sides of the insulating substrate (2). Alternatively, even number of network circuits are formed on the surface of the insulating substrate (2) and the terminals (1) are arranged on the side edges of the insulating substrate (2) point-symmetrically with respect to the center of the surface of the insulating substrate (2).

Abstract translation: 在绝缘基板的表面上形成具有三个以上奇数个端子的网络的表面安装芯片网络部件被抑制。 在绝缘基板（2）的表面上形成有多个网络电路，并且在绝缘基板（2）的相对侧分别配置有相同数量的端子（1）。 或者，在绝缘基板（2）的表面上形成有多个网络电路，并且端子（1）相对于表面的中心点对称地配置在绝缘基板（2）的侧缘 绝缘基板（2）。

公开(公告)号：US20050168917A1

公开(公告)日：2005-08-04

申请号：US11095588

申请日：2005-04-01

Applicant: Seok Jun ,  Myoung Moon ,  Duk Lee

Inventor： Seok Jun ,  Myoung Moon ,  Duk Lee

IPC: H05K1/11 ,  H01L23/498 ,  H05K1/03 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  H01G4/06

CPC classification number: H05K3/403 ,  H01L23/49805 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/16195 ,  H05K1/0306 ,  H05K3/0052 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/09181 ,  H05K2201/0919 ,  H05K2201/09454 ,  H05K2203/1476 ,  H01L2924/00

Abstract: The A ceramic multilayer substrate includes a plurality of ceramic substrates being stacked vertically, each substrate having a designated thickness; pattern layers formed on surfaces of the ceramic substrates so as to form circuit elements; external terminals vertically formed on side surfaces of the stacked ceramic substrates; and internal connection parts, each of which is formed on a part of one of the pattern layers, is connected to one of the external terminal terminals so as to exchange signals with the outside, and be is broad enough to surround at least partially the connected external terminal.

Abstract translation: A陶瓷多层基板包括垂直堆叠的多个陶瓷基板，每个基板具有指定的厚度; 形成在陶瓷基板的表面上的图案层，以形成电路元件; 垂直形成在堆叠的陶瓷基板的侧表面上的外部端子; 并且每个形成在一个图案层的一部分上的内部连接部分连接到外部端子之一，以便与外部交换信号，并且足够宽以至少部分地包围连接的 外部终端。

公开(公告)号：US06906415B2

公开(公告)日：2005-06-14

申请号：US10184340

申请日：2002-06-27

Applicant: Tongbi Jiang ,  Setho Sing Fee ,  Tay Wuu Yean ,  Lim Thiam Chye

Inventor： Tongbi Jiang ,  Setho Sing Fee ,  Tay Wuu Yean ,  Lim Thiam Chye

IPC: H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10 ,  H05K1/14 ,  H05K3/34 ,  H05K3/40 ,  H01L23/34

CPC classification number: H01L23/13 ,  H01L23/3128 ,  H01L23/49805 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/19041 ,  H05K1/141 ,  H05K3/3436 ,  H05K3/3442 ,  H05K3/403 ,  H05K2201/045 ,  H05K2201/049 ,  H05K2201/09181 ,  H05K2201/10727

Abstract: A multidie semiconductor device (MDSCD) package includes a generally planar interposer comprising a substrate with a central receptacle, upper surface conductors, and outer connectors on the lower surface of the interposer. Conductive vias connect upper surface conductors with outer connectors. One or more semiconductor devices may be mounted in the receptacle and one or more other semiconductor devices mounted above and/or below the interposer and attached thereto. The package may be configured to have a footprint not significantly larger than the footprint of the largest device and/or a thickness not significantly greater than the combined thickness of included devices. Methods for assembling and encapsulating packages from multidie wafers and multi-interposer sheets or strips are disclosed. Methods for combining a plurality of packages into a single stacked package are disclosed. The methods may include use of somewhat laterally extending intermediate conductive elements, flip-chip style electrical connection, or both within the same package.

Abstract translation: 多芯片半导体器件（MDSCD）封装包括大体上平面的中介层，其包括具有中心插座的基板，上表面导体以及插入件下表面上的外部连接器。 导电通孔将上表面导体与外部连接器相连。 一个或多个半导体器件可以安装在插座中，以及安装在插入件上方和/或下方并附着于其上的一个或多个其它半导体器件。 封装可以被配置为具有不显着大于最大器件的占地面积和/或不显着大于所包括的器件的组合厚度的厚度。 公开了用于组装和封装来自多芯片晶片和多中介片片或条的封装的方法。 公开了将多个封装组合成单个堆叠封装的方法。 这些方法可以包括在相同封装内使用稍微侧向延伸的中间导电元件，倒装片式电连接或两者。

公开(公告)号：US06848912B2

公开(公告)日：2005-02-01

申请号：US10317143

申请日：2002-12-12

Applicant: Tonglong Zhang

Inventor： Tonglong Zhang

IPC: H05K3/00 ,  H05K3/40 ,  H05K3/42 ,  H01R12/00

CPC classification number: H05K1/115 ,  H01R12/523 ,  H05K3/0047 ,  H05K3/403 ,  H05K3/42 ,  H05K3/429 ,  H05K2201/09181 ,  H05K2201/09645 ,  H05K2201/09854 ,  H05K2203/1476

Abstract: A via provides a plurality of electrical connections between conductors on different layers of a circuit board. The via includes an opening through the circuit board formed by a plurality of substantially partially overlapping bores. An electrically conductive plating is formed on an inner surface of the opening. The plating forms a plurality of distinct electrically conductive paths.

Abstract translation: 通孔在电路板的不同层上的导体之间提供多个电连接。 通孔包括通过由多个基本上部分重叠的孔形成的电路板的开口。 在开口的内表面上形成导电电镀。 电镀形成多个不同的导电路径。

公开(公告)号：US06815249B2

公开(公告)日：2004-11-09

申请号：US10173432

申请日：2002-06-18

Applicant: Tsuyoshi Miura

Inventor： Tsuyoshi Miura

IPC: H01L2144

CPC classification number: H01L33/62 ,  H01L33/486 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01078 ,  H01L2924/12041 ,  H05K3/0052 ,  H05K3/0094 ,  H05K3/284 ,  H05K3/3442 ,  H05K3/403 ,  H05K3/42 ,  H05K2201/09181 ,  H05K2203/1394 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A surface-mount device has a substrate, a pair of electrodes, each of which comprises an upper electrode and a lower electrode. A pair of grooves are formed in opposite sides of the substrate. The upper electrode and the lower electrode are connected by a connecting layer formed on an inside wall of each of the grooves. An LED is mounted on one of the electrodes, and a lid is provided in an upper portion of each of the grooves. A protector layer is formed on the substrate to seal the upper electrode, LED and lids.