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    Low profile equipment housing with angular fan
    61.
    发明授权
    Low profile equipment housing with angular fan 有权
    薄型设备外壳带角式风扇

    公开(公告)号：US06512673B1

    公开(公告)日：2003-01-28

    申请号：US09899762

    申请日：2001-07-05

    Applicant: Robert Wiley

    Inventor： Robert Wiley

    IPC: H05V720

    CPC classification number: H05K7/20727 ,  G06F1/183 ,  G06F1/189 ,  G06F1/20 ,  G11B33/022 ,  G11B33/123 ,  G11B33/127 ,  G11B33/142 ,  H01L23/467 ,  H01L2924/0002 ,  H01R12/523 ,  H01R12/7082 ,  H01R12/721 ,  H05K1/0263 ,  H05K1/116 ,  H05K3/325 ,  H05K2201/09254 ,  H05K2201/10189 ,  H05K2201/10409 ,  H01L2924/00

    Abstract: The present invention is directed to ventilating or cooling element for airflow cooling in a digital data processing apparatus, and it is particularly suited to such apparatus having a high circuit density, or mounted within a restricted chassis or housing, such as the housing of a web server, or of a storage array device for a network server or web server. The cooling element includes a fan that is disposed at an angle to integrate its cooling air with general circulation or air flow through the chassis. The element may mount on a plate, such as the thermally conductive plate of a heat sink, that is adapted for coupling to the chassis and/or contacting a microprocessor chip, and a fan is disposed on the mounting plate at an angle to cool the plate or chip without creating obstructive cross wind. The mounting plate can be disposed within the middle portion of the chassis. The fan or cooling element can be angled so as to direct airflow towards at least a selected portion of the chassis, e.g. along a flow path to a chassis vent or opening, which may be in the rear portion. The mounting plate can also include one or more a thermally conductive heat dissipation members, such as fins or posts, and the fan may have a side-to-side tilt as well as an inclination with respect to the plane of the plate.

    Abstract translation: 本发明涉及用于数字数据处理装置中的气流冷却的通风或冷却元件，并且其特别适合于具有高电路密度的这种装置，或者安装在限制的底盘或壳体内，例如网的外壳 服务器或用于网络服务器或Web服务器的存储阵列设备。 冷却元件包括风扇，其以一定角度设置，以将其冷却空气与通过底盘的一般循环或空气流相结合。 元件可以安装在诸如散热器的导热板的板上，其适于联接到底盘和/或接触微处理器芯片，并且风扇以一定角度设置在安装板上以冷却 板或芯片，而不产生阻塞性交叉风。 安装板可以设置在底盘的中间部分内。 风扇或冷却元件可以是成角度的，以便将气流引导至底盘的至少一部分选定区域。 沿着可以位于后部的机箱通风口或开口的流动路径。 安装板还可以包括一个或多个导热散热构件，例如翅片或柱，并且风扇可以具有相对于板的平面的侧向倾斜以及倾斜。

    Apparatus and method for high speed board-to board ribbon cable data transfer
    64.
    发明授权
    Apparatus and method for high speed board-to board ribbon cable data transfer 失效
    高速板对板带状电缆数据传输的装置和方法

    公开(公告)号：US06237056B1

    公开(公告)日：2001-05-22

    申请号：US09615966

    申请日：2000-07-14

    Applicant: Chris Lam ,  James Burnham

    Inventor： Chris Lam ,  James Burnham

    IPC: G06F1300

    CPC classification number: H05K1/0246 ,  G06F13/4072 ,  H05K1/0237 ,  H05K1/148 ,  H05K3/361 ,  H05K2201/09254 ,  H05K2201/10022 ,  H05K2201/10689

    Abstract: A high speed board-to-board data transfer system capable of data transfer over single ended ribbon cable between a slave device and a master device. A slave device comprises a plurality of drivers generating clock signals at above 40 MHz connected to cable connector pins by a trace line through a series termination resistor. A master device comprises a plurality of receivers corresponding to the drivers connected to cable connector pins through a trace line. The ribbon cable is a single-ended ribbon cable using a ground-signal-ground configuration. The drivers, trace lines, resistors, cables, and receivers are chosen to provide reliable data transfer above 40 MHz, preferably between 40 MHz and 80 MHz. Preferred master and slave devices comprise VESA VIP 2.0 masters and slaves transmitting high quality video.

    Abstract translation: 一种高速板对板数据传输系统，能够通过单端带状电缆在从设备和主设备之间进行数据传输。 从设备包括多个驱动器，其通过串行终端电阻器的轨迹线在40MHz以上产生时钟信号，连接到电缆连接器引脚。 主设备包括对应于通过轨迹线连接到电缆连接器引脚的驱动器的多个接收器。 带状电缆是使用接地信号接地配置的单端带状电缆。 选择驱动器，跟踪线，电阻，电缆和接收器，以提供高于40 MHz，优选在40 MHz和80 MHz之间的可靠数据传输。 主设备和从设备包括VESA VIP 2.0主机和从机发送高质量视频。

    Backplane having reduced LC product
    66.
    发明授权
    Backplane having reduced LC product 失效
    背板具有降低的LC产品

    公开(公告)号：US5930119A

    公开(公告)日：1999-07-27

    申请号：US31179

    申请日：1998-02-26

    Applicant: Andrew R. Berding

    Inventor： Andrew R. Berding

    IPC: H05K1/02 ,  H05K1/14 ,  H05K3/46 ,  H05K7/14

    CPC classification number: H05K1/0248 ,  H05K1/0216 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09254 ,  H05K2201/09727

    Abstract: A data processing system includes a backplane and a plurality of logic boards connected to the backplane by a plurality of connectors. A set of common points is electrically coupled to the connectors by individual conductive traces between each common point and the corresponding pins of the connectors. The inductance of longer traces is reduced by merging traces near a central portion of the backplane to form a conductive region that extends to at least one connector on either side of the common points, thereby electrically shortening the longer traces. The inductance is further reduced by widening the longer traces. Longer traces are wider than shorter traces to reduce the differences in the LC products associated with each trace and, therefore, the differences in delay among the traces.

    Abstract translation: 数据处理系统包括通过多个连接器连接到背板的背板和多个逻辑板。 一组公共点通过每个公共点和连接器的相应引脚之间的各个导电迹线电耦合到连接器。 通过在背板的中心部分附近合并迹线来形成较长迹线的电感，以形成延伸到公共点两侧的至少一个连接器的导电区域，从而电气缩短较长的迹线。 通过加宽更长的走线来进一步减小电感。 较长的迹线比较短的迹线更宽，以减少与每个迹线相关联的LC产物的差异，并因此减少迹线之间的延迟差异。

    Clock skew reduction using spider clock trace routing
    67.
    发明授权
    Clock skew reduction using spider clock trace routing 失效
    使用蜘蛛时钟跟踪路由减少时钟偏差

    公开(公告)号：US5861764A

    公开(公告)日：1999-01-19

    申请号：US775771

    申请日：1996-12-31

    Applicant: James H. Singer ,  Joseph Peter Miller

    Inventor： James H. Singer ,  Joseph Peter Miller

    IPC: G06F1/10 ,  H03K5/15 ,  H05K1/02 ,  H03K19/00

    CPC classification number: H05K1/0248 ,  G06F1/10 ,  H03K5/15013 ,  H05K1/0246 ,  H05K2201/09254

    Abstract: A technique for reducing skew between clock signals in a digital system requiring multiple clock signals. The system preferably is implemented on a printed circuit board. An oscillator circuit provides a periodic signal to a clock buffer which generates multiple periodic clock signals. The clock signals are provided to various destination points on the printed circuit board. The rising and falling edges of each clock signal generated by the clock buffer do not occur precisely at the same time as the rising and falling edges of the other clock signals. This misalignment of clock edges, or skew, is detrimental to system performance, but is reduced substantially by connecting all of the clock buffer's output clock signals together at a single physical point or node. Accordingly, the printed circuit board traces carrying each of the clock signals are routed to a single point node. A single point node is used to reduce skew caused by the clock buffer. Single point nodes also may be used at various locations on the printed circuit board to reduce skew caused by differences in the lengths of the traces carrying the clock signals.

    Abstract translation: 一种减少需要多个时钟信号的数字系统中时钟信号之间的偏差的技术。 该系统优选地在印刷电路板上实现。 振荡器电路向产生多个周期时钟信号的时钟缓冲器提供周期性信号。 时钟信号被提供给印刷电路板上的各个目的地点。 由时钟缓冲器产生的每个时钟信号的上升沿和下降沿都不会与其他时钟信号的上升沿和下降沿同时精确地出现。 时钟边缘或偏斜的这种不对准对于系统性能是不利的，但是通过将单个物理点或节点上的所有时钟缓冲器的输出时钟信号连接在一起而大大减少。 因此，承载每个时钟信号的印刷电路板迹线被路由到单点节点。 单点节点用于减少时钟缓冲区引起的偏移。 也可以在印刷电路板上的各个位置使用单点节点以减少由携带时钟信号的迹线的长度差引起的偏斜。

    Backplane for high speed data processing system
    68.
    发明授权
    Backplane for high speed data processing system 失效
    背板用于高速数据处理系统

    公开(公告)号：US5696667A

    公开(公告)日：1997-12-09

    申请号：US632648

    申请日：1996-04-15

    Applicant: Andrew R. Berding

    Inventor： Andrew R. Berding

    IPC: H05K1/02 ,  H05K1/14 ,  H05K7/14

    CPC classification number: H05K1/0248 ,  H05K1/0216 ,  H05K7/1459 ,  H05K1/14 ,  H05K2201/044 ,  H05K2201/09254 ,  H05K2201/09263

    Abstract: A data processing system includes a backplane and a plurality of logic boards connected to the backplane by a plurality of connectors. In one embodiment of the invention, a set of common points is electrically coupled to the connectors by individual conductive traces between each common point and the corresponding pins of the connectors. The common points are preferably centrally located among the plurality of connectors to reduce propagation delay. A connector can be attached at the common points. The traces are separated from each other by lateral displacement in a single plane. If the backplane is a multi-layered printed circuit board, the traces are separated from each other by vertical displacement between the layers of the printed circuit board or by both vertical and horizontal displacement. The traces to the connectors nearest the common points have a minimum length greater than the distance between the nearest connectors and the common points.

    Abstract translation: 数据处理系统包括通过多个连接器连接到背板的背板和多个逻辑板。 在本发明的一个实施例中，一组公共点通过在每个公共点和连接器的相应引脚之间的各个导电迹线电耦合到连接器。 公共点优选地位于多个连接器之间，以减少传播延迟。 连接器可以连接在公共点。 通过在单个平面中的横向位移，迹线彼此分离。 如果背板是多层印刷电路板，则通过印刷电路板的层之间的垂直位移或垂直和水平位移两者彼此分开。 到最接近公共点的连接器的迹线的最小长度大于最近连接器和公共点之间的距离。

    Circuit for crossing strip lines
    69.
    发明授权
    Circuit for crossing strip lines 失效
    穿线条线路

    公开(公告)号：US5432485A

    公开(公告)日：1995-07-11

    申请号：US278162

    申请日：1994-07-21

    Applicant: Katsuya Nagashima

    Inventor： Katsuya Nagashima

    IPC: H01P1/00 ,  H01P3/08 ,  H01P5/16 ,  H05K1/02 ,  H05K3/46 ,  H01P5/12

    CPC classification number: H05K1/0237 ,  H01P5/16 ,  H01L2223/6627 ,  H01L2924/15192 ,  H01L2924/1903 ,  H05K2201/09245 ,  H05K2201/09254

    Abstract: A cross circuit comprises a lattice structure formed on a single layer of a multilayer printed circuit, the lattice structure having an arrangement of nodes consisting of two input nodes, two output nodes, a center node and four other nodes which are connected by quarter-wavelength lines. An input node is connected to both a first node and a second node by a quarter-wavelength line, and the other input node is connected to both the first node and a third node by a quarter-wavelength line. Similarly, an output node is connected to both the third node and a fourth node, the other output node to both the fourth node and the second node, the center node to the four nodes, by quarter-wavelength lines, respectively. A first input signal of a predetermined frequency applied to the first input node appears on only the first output node, and the second input signal of the same frequency applied to the second input node appears on only the second output node.

    Abstract translation: 交叉电路包括形成在多层印刷电路的单层上的晶格结构，所述晶格结构具有由两个输入节点，两个输出节点，中心节点和四个其他节点组成的节点的布置，所述节点由四分之一波长 线条。 输入节点通过四分之一波长的线连接到第一节点和第二节点，另一个输入节点通过四分之一波长的线连接到第一节点和第三节点。 类似地，输出节点分别连接到第三节点和第四节点，另一个输出节点连接到第四节点和第二节点，中心节点连接到四个节点，四分之一波长线。 施加到第一输入节点的预定频率的第一输入信号仅出现在第一输出节点上，并且施加到第二输入节点的相同频率的第二输入信号仅出现在第二输出节点上。

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