公开(公告)号：US07874065B2

公开(公告)日：2011-01-25

申请号：US12263416

申请日：2008-10-31

Applicant: Vinh T. Nguyen ,  Claude A. S. Hamrick

Inventor： Vinh T. Nguyen ,  Claude A. S. Hamrick

IPC: H05K3/36

CPC classification number: H05K3/1258 ,  H05K3/108 ,  H05K3/125 ,  H05K3/243 ,  H05K3/4611 ,  H05K3/4623 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09536 ,  H05K2201/098 ,  H05K2203/013 ,  H05K2203/0568 ,  Y10T29/49002 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A process for making a multi-layered circuit board having electrical current traces includes providing a substrate having a 1st layer of conductive material to form a ground plane, plurality of metallic 1st traces on a 2nd side of the substrate having widths of approximately 25 microns or less, developing 1st ribs of photoresist forming 1st walls rising above upper surface of an adjacent seed layer trace, depositing 1st conductive signal traces having a thickness exceeding 25 microns into channels and over seed layer traces and stripping the ribs to leave 1st conductive traces having a height-to-transverse ratio exceeding 1.

Abstract translation: 用于制造具有电流迹线的多层电路板的方法包括提供具有第一层导电材料以形成接地平面的衬底，在衬底的第二面上的多个金属第一迹线具有约25微米的宽度或 在相邻的种子层迹线的上表面上方形成第一壁的第一肋形成第一肋，将厚度超过25微米的第一导电信号迹线沉积到通道中并且超过种子层迹线并剥离肋，以留下第一导电迹线， 高度与横向之比超过1。

公开(公告)号：US07838776B2

公开(公告)日：2010-11-23

申请号：US12148271

申请日：2008-04-17

Applicant: John M. Lauffer ,  Voya R. Markovich ,  Michael Wozniak

Inventor： John M. Lauffer ,  Voya R. Markovich ,  Michael Wozniak

IPC: H05K1/03

CPC classification number: H01L21/4857 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H05K3/383 ,  H05K3/4641 ,  H05K2201/0355 ,  H05K2201/09318 ,  H05K2203/0353 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T428/12556 ,  Y10T428/12993 ,  H01L2224/0401

Abstract: A circuitized substrate in which two conductive layers (e.g., electroplated copper foil) are bonded (e.g., laminated) to an interim dielectric layer. Each of the two foil surfaces which physically bond to the dielectric are smooth (e.g., preferably by chemical processing) and include a thin, organic layer thereon, while the outer surfaces of both foils are also smooth (e.g., preferably also using a chemical processing step). One of these resulting conductive layers may function as a ground or voltage plane while the other may function as a signal plane with a plurality of individual signal lines as part thereof. An electrical assembly and an information handling system utilizing such a circuitized substrate are also provided.

Abstract translation: 其中两个导电层（例如，电镀铜箔）被结合（例如层压）到电介质层的电路化衬底。 物理地结合到电介质的两个箔表面中的每一个是光滑的（例如，优选通过化学处理），并且在其上包括薄的有机层，而两个箔的外表面也是光滑的（例如，优选也使用化学处理 步）。 这些导电层中的一个可以用作接地或电压平面，而另一个可以用作具有多个单独信号线作为其一部分的信号平面。 还提供了使用这种电路化基板的电气组件和信息处理系统。

公开(公告)号：US20100277835A1

公开(公告)日：2010-11-04

申请号：US12771500

申请日：2010-04-30

Applicant: Mitsuru Honjo ,  Daisuke Yamauchi ,  Kei Nakamura

Inventor： Mitsuru Honjo ,  Daisuke Yamauchi ,  Kei Nakamura

IPC: G11B5/55 ,  H05K1/18 ,  H05K1/02

CPC classification number: G11B5/4846 ,  G11B5/484 ,  H05K1/0245 ,  H05K1/189 ,  H05K3/0061 ,  H05K2201/09236 ,  H05K2201/09318 ,  H05K2201/10674 ,  H05K2201/2009

Abstract: A plurality of wiring traces are formed on a base insulating layer, and a metal layer is formed on the opposite surface of the base insulating layer. Two adjacent wiring traces constitute a transmission line pair. The width of the wiring trace is set to not more than 250 μm, and the distance between the adjacent wiring traces is set to not less than 8 μm. The thickness of the base insulating layer is selected to cause differential impedance of the transmission line pair to be not less than 10Ω and not more than 50Ω.

Abstract translation: 在基底绝缘层上形成多个布线迹线，并且在基底绝缘层的相对表面上形成金属层。 两个相邻的布线迹线构成传输线对。 布线迹线的宽度设定为不大于250μm，并且相邻布线迹线之间的距离设定为不小于8μm。 选择基极绝缘层的厚度使传输线对的差分阻抗不小于10Ω; 不超过50个

公开(公告)号：US20100149769A1

公开(公告)日：2010-06-17

申请号：US12421953

申请日：2009-04-10

Applicant: Byoung Hwa LEE ,  Sung Kwon WI ,  Hong Yeon CHO ,  Dong Seok PARK ,  Sang Soo PARK ,  Min Cheol PARK

Inventor： Byoung Hwa LEE ,  Sung Kwon WI ,  Hong Yeon CHO ,  Dong Seok PARK ,  Sang Soo PARK ,  Min Cheol PARK

IPC: H05K1/18

CPC classification number: H05K1/0231 ,  H01G2/065 ,  H01G4/35 ,  H05K2201/09318 ,  H05K2201/09481 ,  H05K2201/10636 ,  H05K2201/10969 ,  Y02P70/611

Abstract: A circuit board device includes a circuit board comprising a mounting area, and first and second power lines and a ground pad formed on the mounting area, and a vertical multilayer chip capacitor (MLCC) comprising a capacitor body, a plurality of first and second polarity inner electrodes, first and second outer electrodes, and a third outer electrode, wherein the first and second power lines are separately disposed on the mounting area, connected to the first and second outer electrodes, and electrically connected to each other only by the vertical MLCC, and the ground pad is disposed between the first and second power lines and connected to the third outer electrode.

Abstract translation: 一种电路板装置，包括：电路板，包括安装区域;以及第一和第二电力线以及形成在所述安装区域上的接地焊盘;以及垂直多层片状电容器（MLCC），其包括电容器本体，多个第一和第二极性 内电极，第一外电极和第二外电极以及第三外电极，其中第一和第二电源线分别设置在安装区域上，连接到第一外电极和第二外电极，并且仅通过垂直MLCC 并且接地焊盘设置在第一和第二电源线之间并且连接到第三外部电极。

公开(公告)号：US20100047535A1

公开(公告)日：2010-02-25

申请号：US12541963

申请日：2009-08-16

Applicant: Lex Kosowsky ,  Robert Fleming

Inventor： Lex Kosowsky ,  Robert Fleming

IPC: B32B3/10 ,  B32B9/04 ,  B05D5/12 ,  C23C28/00

CPC classification number: H05K1/0257 ,  H05K1/0259 ,  H05K1/0373 ,  H05K1/167 ,  H05K3/4688 ,  H05K2201/0738 ,  H05K2201/09318 ,  Y10T428/24802 ,  Y10T428/31504

Abstract: A core layer structure is provided for substrate and packed devices. The core layer structure includes a first layer, a second layer combined with the first layer. A layer of voltage switchable dielectric (VSD) material provided in between the first layer and second layer

Abstract translation: 为基板和打包装置提供芯层结构。 芯层结构包括第一层，与第一层结合的第二层。 设置在第一层和第二层之间的可变压电介质层（VSD）层

公开(公告)号：US07667980B2

公开(公告)日：2010-02-23

申请号：US11539990

申请日：2006-10-10

Applicant: Brian A. Baker ,  James E. Hughes ,  Thomas D. Pahel, Jr. ,  Pravin Patel ,  Challis L. Purrington ,  Christopher C. West

Inventor： Brian A. Baker ,  James E. Hughes ,  Thomas D. Pahel, Jr. ,  Pravin Patel ,  Challis L. Purrington ,  Christopher C. West

IPC: H05K7/00

CPC classification number: H05K1/0216 ,  H05K1/0231 ,  H05K1/0233 ,  H05K3/429 ,  H05K2201/0792 ,  H05K2201/09318 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2201/1003

Abstract: Printed circuit boards for countering signal distortion are disclosed that include: a conductive pathway on a printed circuit board between a transmitter and a receiver, the conductive pathway comprised of traces and vias connected together for conductive transfer of a signal from the transmitter to the receiver; a parasitic element on the printed circuit board, the parasitic element having a parasitic effect that distorts the signal; and one or more passive elements mounted adjacent to the conductive pathway without connecting to the conductive pathway, the passive elements having a corrective effect to reduce the distortion from the parasitic effect on the signal.

Abstract translation: 公开了用于对抗信号失真的印刷电路板，其包括：在发射器和接收器之间的印刷电路板上的导电路径，由连接在一起的迹线和通孔组成的导电通路，用于将信号从发射器传导到接收器; 在印刷电路板上的寄生元件，寄生元件具有扭曲信号的寄生效应; 以及一个或多个无源元件安装在导电路径附近而不连接到导电路径，无源元件具有校正效果，以减少由信号引起的寄生效应的失真。

公开(公告)号：US20090218116A1

公开(公告)日：2009-09-03

申请号：US12167242

申请日：2008-07-02

Applicant: Chia-Hui Wu

Inventor： Chia-Hui Wu

IPC: H05K1/00 ,  B05D5/12

CPC classification number: H01L23/4985 ,  H01L24/16 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/01078 ,  H01L2924/14 ,  H05K1/0209 ,  H05K1/095 ,  H05K1/189 ,  H05K2201/09318 ,  H05K2201/10674 ,  H05K2203/104 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49169

Abstract: A chip on film (COF) structure includes a flexible circuit board and a chip. The flexible circuit board includes a flexible base film and a conductive layer. The flexible base film has a polyimide layer and an anisotropic conductive layer (ACL). The conductive layer is disposed on the flexible base film. The conductive layer and the ACL are separated by the polyimide layer. The chip is mounted with the conductive layer via interconnectors.

Abstract translation: 膜芯片（COF）结构包括柔性电路板和芯片。 柔性电路板包括柔性基膜和导电层。 柔性基膜具有聚酰亚胺层和各向异性导电层（ACL）。 导电层设置在柔性基膜上。 导电层和ACL被聚酰亚胺层分离。 芯片通过互连器件安装有导电层。

公开(公告)号：US20090195998A1

公开(公告)日：2009-08-06

申请号：US12357714

申请日：2009-01-22

Applicant: Yasuto ISHIMARU ,  Hirofumi EBE

Inventor： Yasuto ISHIMARU ,  Hirofumi EBE

IPC: H05K1/18 ,  H05K3/10

CPC classification number: H05K3/303 ,  H01L23/3735 ,  H01L2224/16225 ,  H05K1/0203 ,  H05K1/0269 ,  H05K1/189 ,  H05K2201/0108 ,  H05K2201/09318 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2203/166 ,  Y02P70/613 ,  Y10T29/49162

Abstract: A mounting region having a rectangular shape is provided at an approximately center of one surface of an insulating layer. A plurality of conductive traces are formed so as to outwardly extend from the inside of the mounting region. A cover insulating layer is formed so as to cover the plurality of conductive traces in a periphery of the mounting region. An electronic component is mounted on the insulating layer so as to overlap with the mounting region. A metal layer is provided on the other surface of the insulating layer. Openings having a rectangular shape are formed in the metal layer along a pair of longer sides and a pair of shorter sides of the mounting region. The openings are opposite to part of terminals of the plurality of conductive traces, respectively, with the insulating layer sandwiched therebetween.

Abstract translation: 在绝缘层的一个表面的大致中心处设置具有矩形形状的安装区域。 多个导电迹线被形成为从安装区域的内部向外延伸。 形成覆盖绝缘层，以覆盖安装区域周边的多个导电迹线。 电子部件安装在绝缘层上以与安装区域重叠。 在绝缘层的另一个表面上设置金属层。 具有矩形形状的开口沿着一对长边和安装区域的一对较短边形成在金属层中。 开口分别与多个导电迹线的端子的一部分相对，绝缘层夹在其间。

公开(公告)号：US20090179712A1

公开(公告)日：2009-07-16

申请号：US12285230

申请日：2008-09-30

Applicant: Tae Sun Jang ,  Hark Byeong Park ,  Jong Sung Lee ,  Hyung Geun Kim

Inventor： Tae Sun Jang ,  Hark Byeong Park ,  Jong Sung Lee ,  Hyung Geun Kim

IPC: H03H7/38

CPC classification number: H05K1/0224 ,  H01P3/026 ,  H01P3/082 ,  H05K1/0253 ,  H05K2201/0191 ,  H05K2201/09318 ,  H05K2201/0969

Abstract: An electric apparatus capable of stably transmitting signals in a high frequency band (high speed signals) by preventing distortion of a signal waveform through impedance control is disclosed. The electric apparatus includes a case having a signal line which transmits signals between electronic parts, a dielectric deposited on the case and the signal line, and a ground portion disposed on the dielectric.

Abstract translation: 公开了一种能够通过阻抗控制来防止信号波形的失真而能够稳定地在高频带（高速信号）中发送信号的电气设备。 电气设备包括具有在电子部件之间传输信号的信号线，沉积在壳体上的电介质和信号线以及设置在电介质上的接地部分的壳体。

公开(公告)号：US20090032295A1

公开(公告)日：2009-02-05

申请号：US11911914

申请日：2006-04-19

Applicant: Yoshihiko Okajima ,  Katsunori Yashima ,  Keiji Takano ,  Takuya Okada

Inventor： Yoshihiko Okajima ,  Katsunori Yashima ,  Keiji Takano ,  Takuya Okada

IPC: H05K1/00 ,  H05K1/16

CPC classification number: H05K1/0203 ,  F21K9/00 ,  F21Y2115/10 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2924/13091 ,  H05K1/0233 ,  H05K1/028 ,  H05K1/056 ,  H05K1/189 ,  H05K3/0058 ,  H05K3/0061 ,  H05K3/281 ,  H05K3/386 ,  H05K2201/0209 ,  H05K2201/0266 ,  H05K2201/055 ,  H05K2201/056 ,  H05K2201/086 ,  H05K2201/09318 ,  H05K2201/0989 ,  H05K2201/10106 ,  H05K2203/0191 ,  H05K2203/063 ,  H05K2203/302 ,  H01L2924/00014 ,  H01L2924/00

Abstract: To provide a thin metal base circuit board which can be not only installed on a flat portion but also closely attached to a side or bottom surface of a case or to a stepped or curved portion and which is excellent in heat dissipation performance, electrical insulating performance and flexibility; a process for its production; and a hybrid integrated circuit, an LED module and a bright, ultra-long-life LED light source employing it.A metal base circuit board having insulating layers and conductive circuits or metal foils alternately laminated, characterized in that the thickness of each conductive circuit or metal foil is from 5 μm to 450 μm, each insulating layer is made of a cured product of a resin composition comprising an inorganic filler and a thermosetting resin, and the thickness of each insulating layer is from 9 μm to 300 μm; and a hybrid circuit board employing it. The metal base circuit board wherein a coverlay is provided, and a layer having a magnetic loss or a layer having a dielectric loss is laminated on the surface of the coverlay. A LED light source unit having at least one light-emitting diode (LED) mounted on the conductive circuit.

Abstract translation: 为了提供一种薄的金属基底电路板，其不仅可以安装在平坦部分上，而且可以紧密地附接到壳体的侧面或底部表面，或者可以是阶梯状或弯曲部分，并且散热性能优异，电绝缘性能 灵活性; 一个生产过程; 和混合集成电路，LED模块和采用它的明亮，超长寿命的LED光源。 具有交替层叠绝缘层和导电电路或金属箔的金属基电路板，其特征在于，每个导电电路或金属箔的厚度为5μm至450μm，每个绝缘层由树脂组合物的固化产物 包括无机填料和热固性树脂，并且每个绝缘层的厚度为9μm至300μm; 和采用它的混合电路板。 提供覆盖层的金属基底电路板，具有磁损耗的层或具有介电损耗的层层叠在覆盖层的表面上。 一种LED光源单元，其具有安装在导电电路上的至少一个发光二极管（LED）。