公开(公告)号：US07994433B2

公开(公告)日：2011-08-09

申请号：US12409670

申请日：2009-03-24

Applicant: Honchin En ,  Masayuki Hayashi ,  Dongdong Wang ,  Kenichi Shimada ,  Motoo Asai ,  Koji Sekine ,  Tohru Nakai ,  Shinichiro Ichikawa ,  Yukihiko Toyoda

Inventor： Honchin En ,  Masayuki Hayashi ,  Dongdong Wang ,  Kenichi Shimada ,  Motoo Asai ,  Koji Sekine ,  Tohru Nakai ,  Shinichiro Ichikawa ,  Yukihiko Toyoda

IPC: H01R12/04 ,  H05K1/11

CPC classification number: C23G1/10 ,  H01L2924/0002 ,  H05K3/0094 ,  H05K3/062 ,  H05K3/067 ,  H05K3/108 ,  H05K3/384 ,  H05K3/385 ,  H05K3/388 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4661 ,  H05K2201/0129 ,  H05K2201/0158 ,  H05K2201/0338 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0307 ,  H05K2203/0315 ,  H05K2203/072 ,  H05K2203/1105 ,  Y10T29/49124 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49163 ,  Y10T29/49165 ,  Y10T428/24917 ,  H01L2924/00

Abstract: A multilayer printed circuit board including a substrate board and a built-up structure formed over the substrate board. The built-up structure includes conductor circuits and resin insulating layers. The built-up structure has via holes interconnecting the conductor circuits through one or more resin insulating layers. The via holes are filled up with plating, and the resin insulating layers is formed of a cycloolefin resin.

Abstract translation: 一种多层印刷电路板，包括形成在基板上的基板和叠层结构。 组合结构包括导体电路和树脂绝缘层。 积层结构具有通过一个或多个树脂绝缘层将导体电路互连的通孔。 通孔填充有电镀，树脂绝缘层由环烯烃树脂形成。

公开(公告)号：US20110094780A1

公开(公告)日：2011-04-28

申请号：US12923773

申请日：2010-10-07

Applicant: Shinya Uchibori ,  Nobumasa Handa ,  Yuuki Sanada

Inventor： Shinya Uchibori ,  Nobumasa Handa ,  Yuuki Sanada

IPC: H05K1/00 ,  H05K3/42

CPC classification number: H05K3/4644 ,  H05K1/0265 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/0347 ,  H05K2201/0959 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/025 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: In a printed wiring board, a first inner layer wiring line is formed on one surface of a wiring line formation layer, a resin film made of electric insulation resin is formed on an area other than the first inner layer wiring line formed on the wiring line formation layer. The resin film and the first inner layer wiring line have the same plane surface. A second wiring line is formed on the resin film, and the second wiring line is thinner in thickness than the first inner layer wiring line. A limit of error in thickness of the resin film and the first inner layer wiring line is within 10% of the thickness of each of the resin film and the first inner layer wiring line.

Abstract translation: 在印刷布线板中，在布线线形成层的一个表面上形成第一内层布线，在布线上形成的除了第一内层布线以外的区域形成由电绝缘树脂构成的树脂膜 形成层。 树脂膜和第一内层布线具有相同的平面。 在树脂膜上形成第二布线，第二布线比第一内层布线更薄。 树脂膜和第一内层布线的厚度误差在树脂膜和第一内层布线的厚度的10％以内。

公开(公告)号：US07926172B2

公开(公告)日：2011-04-19

申请号：US11774728

申请日：2007-07-09

Applicant: Tsung-Yuan Chen ,  Shu-Sheng Chiang

Inventor： Tsung-Yuan Chen ,  Shu-Sheng Chiang

IPC: H05K3/36 ,  H05K3/02

CPC classification number: H05K1/0366 ,  H05K3/205 ,  H05K3/426 ,  H05K2201/0959 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: An embedded circuit board including a glass fiber layer, two dielectric layers, and two circuit layers is provided. The glass fiber layer has a first surface and a second surface corresponding to the first surface. The dielectric layers are disposed on the first surface and the second surface, respectively. The circuit layers are embedded in the dielectric layers above the first surface and the second surface, respectively. The outer surface of each circuit layer is coplanar with the outer surface of each dielectric layer, and a distance between the circuit layer and the glass fiber layer is greater than or equal to 3 μm. In addition, a process of the embedded circuit board is provided.

Abstract translation: 提供了包括玻璃纤维层，两个电介质层和两个电路层的嵌入式电路板。 玻璃纤维层具有对应于第一表面的第一表面和第二表面。 电介质层分别设置在第一表面和第二表面上。 电路层分别嵌入在第一表面和第二表面上方的电介质层中。 每个电路层的外表面与每个电介质层的外表面共面，并且电路层和玻璃纤维层之间的距离大于或等于3μm。 此外，提供了嵌入式电路板的处理。

公开(公告)号：US20110048783A1

公开(公告)日：2011-03-03

申请号：US12613072

申请日：2009-11-05

Applicant: Cheng-Po YU

Inventor： Cheng-Po YU

IPC: H05K1/11 ,  H05K3/10

CPC classification number: H05K3/0035 ,  H05K3/107 ,  H05K3/465 ,  H05K2201/0236 ,  H05K2201/0959 ,  H05K2201/09845 ,  H05K2203/1476 ,  Y10T29/49155

Abstract: An embedded wiring board includes an upper wiring layer, a lower wiring layer, an insulation layer, a first conductive pillar and a second conductive pillar. The upper wiring layer contains an upper pad, the lower wiring layer contains a lower pad, and the insulation layer contains an upper surface and a lower surface opposite to the upper surface. The upper pad is embedded in the upper surface and the lower pad is embedded in the lower surface. The first conductive pillar is located in the insulation layer and includes an end surface which is exposed by the upper surface. A height of the first conductive pillar relative to the upper surface is larger than a depth of the upper pad relative to the upper surface. In addition, the second conductive pillar is located in the insulation layer and is connected between the first conductive pillar and the lower pad.

Abstract translation: 嵌入布线板包括上布线层，下布线层，绝缘层，第一导电柱和第二导电柱。 上布线层包含上焊盘，下布线层包含下焊盘，绝缘层包含与上表面相对的上表面和下表面。 上垫片嵌入在上表面中，下垫片嵌入下表面。 第一导电柱位于绝缘层中，并且包括由上表面暴露的端面。 第一导电柱相对于上表面的高度大于上垫相对于上表面的深度。 此外，第二导电柱位于绝缘层中并连接在第一导电柱和下垫之间。

公开(公告)号：US07893792B2

公开(公告)日：2011-02-22

申请号：US10923086

申请日：2004-08-23

Applicant: Jun-sik Hwang ,  Yun-kwon Park ,  Il-jong Song ,  Byeoung-ju Ha

Inventor： Jun-sik Hwang ,  Yun-kwon Park ,  Il-jong Song ,  Byeoung-ju Ha

IPC: H03H9/54 ,  H01P1/213

CPC classification number: H03H9/706 ,  H01L2224/16235 ,  H01L2224/81192 ,  H01L2924/15313 ,  H01L2924/16251 ,  H01P1/213 ,  H03H9/0571 ,  H05K1/0243 ,  H05K1/162 ,  H05K1/165 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/0959 ,  H05K2201/1006 ,  Y10T29/42 ,  Y10T29/49005 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49165

Abstract: A high-integrated duplexer and a fabrication method thereof. The duplexer has a first filter to pass a signal of a transmitted frequency band, a second filter to pass a signal of a received frequency band, an embedded PCB having the first and second filters bonded on a certain area of a surface of an upper side in a predetermined distance from each other, and an isolation part to prevent a signal interference between the first and second filters, and a packaging substrate to package the entire upper side of the embedded PCB so that the packaging substrate is located above and separated from the first and second filters by a predetermined distance. The fabricated high-integrated duplexer has a small size and high performance.

Abstract translation: 高集成双工器及其制造方法。 双工器具有通过发送频带的信号的第一滤波器，传递接收频带的信号的第二滤波器，具有第一和第二滤波器的嵌入式PCB，该第一和第二滤波器接合在上侧表面的某一区域上 隔离部分，以防止第一和第二滤光器之间的信号干扰，以及封装基板，以封装嵌入式PCB的整个上侧，使得封装基板位于上方并与之分离 第一和第二滤光器预定距离。 制造的高集成双工器具有小尺寸和高性能。

公开(公告)号：US20110024164A1

公开(公告)日：2011-02-03

申请号：US12887197

申请日：2010-09-21

Applicant: Motoo ASAI ,  Dongdong WANG ,  Takahiro MORI

Inventor： Motoo ASAI ,  Dongdong WANG ,  Takahiro MORI

IPC: H05K1/03

CPC classification number: H05K3/423 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/036 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/381 ,  H05K3/385 ,  H05K3/387 ,  H05K3/388 ,  H05K3/426 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/0315 ,  H05K2203/0733 ,  H05K2203/0773 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599

Abstract: A multi-layer printed circuit board including a core structure comprising resin layers and conductor circuits sandwiched by the resin layers, the core structure having a first surface and a second surface on an opposite side of the first surface, a first conductor layer including conductor circuits formed on the first surface of the core structure, and a second conductor layer including conductor circuits formed on the second surface of the core structure. The core structure includes a first via hole and a second via hole, and the first via hole and the second via hole include a metal filling up to the respective top of openings formed in the resin layers, respectively, sandwich one or more conductor circuits in the core structure and are positioned vertically to form a through hole electrically connecting respective ones of the conductor circuits of the first and the second conductor layers.

Abstract translation: 一种多层印刷电路板，包括由树脂层和由树脂层夹持的导体电路的芯结构，芯结构具有在第一表面的相对侧上的第一表面和第二表面，第一导体层包括导体电路 形成在芯结构的第一表面上，以及第二导体层，包括形成在芯结构的第二表面上的导体电路。 芯结构包括第一通孔和第二通孔，并且第一通孔和第二通孔分别包括填充到树脂层中形成的开口的相应顶部的金属，将一个或多个导体电路夹在 芯结构并且垂直定位以形成电连接第一和第二导体层的各个导体电路的通孔。

公开(公告)号：US07830018B2

公开(公告)日：2010-11-09

申请号：US11863579

申请日：2007-09-28

Applicant: Teck Kheng Lee

Inventor： Teck Kheng Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H05K13/00 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/115 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09645 ,  H05K2201/09854 ,  H01L2924/00

Abstract: Partitioned vias, interconnects, and substrates that include such vias and interconnects are disclosed herein. In one embodiment, a substrate has a non-conductive layer and a partitioned via formed in a portion of the non-conductive layer. The non-conductive layer includes a top side, a bottom side, and a via hole extending between the top and bottom sides and including a sidewall having a first section a second section. The partitioned via includes a first metal interconnect within the via on the first section of the sidewall and a second metal interconnect within the via hole on the second section of the sidewall and electrically isolated from the first metal interconnect. In another embodiment, the first metal interconnect is separated from the second metal interconnect by a gap within the via hole.

Abstract translation: 包括这种通孔和互连的分隔的过孔，互连和衬底在本文中公开。 在一个实施例中，衬底具有形成在非导电层的一部分中的非导电层和分隔通孔。 非导电层包括在顶侧和底侧之间延伸的顶侧，底侧和通孔，并且包括具有第一部分和第二部分的侧壁。 分隔通孔包括在侧壁的第一部分上的通孔内的第一金属互连和在侧壁的第二部分上的通孔内的第二金属互连，并与第一金属互连电隔离。 在另一个实施例中，第一金属互连通过通孔内的间隙与第二金属互连分开。

公开(公告)号：US07827680B2

公开(公告)日：2010-11-09

申请号：US10751428

申请日：2004-01-06

Applicant: Honchin En ,  Tohru Nakai ,  Takeo Oki ,  Naohiro Hirose ,  Kouta Noda

Inventor： Honchin En ,  Tohru Nakai ,  Takeo Oki ,  Naohiro Hirose ,  Kouta Noda

IPC: H05K3/20

CPC classification number: H05K3/4644 ,  C23C18/1607 ,  C23C18/1653 ,  C23C18/22 ,  C23C18/30 ,  C23C18/34 ,  C23C18/405 ,  C23C28/00 ,  C23C28/023 ,  C23C28/42 ,  C25D3/38 ,  C25D5/022 ,  C25D5/18 ,  C25D5/34 ,  C25D7/123 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/241 ,  H05K3/381 ,  H05K3/382 ,  H05K3/384 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4661 ,  H05K2201/0215 ,  H05K2201/0344 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0353 ,  H05K2203/0723 ,  H05K2203/1476 ,  H05K2203/1492 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: An electroplating process of electroplating an electrically conductive substrate is described. The process includes electroplating intermittently to a predetermined plating thickness using the substrate surface as a cathode and a plating metal as an anode at a constant voltage between the anode and the cathode by repeating application of a voltage between a cathode and an anode and interruption of the application alternately. It is described that a voltage time/interruption time ratio is 0.1 to 1.0, a voltage time is not longer than 10 seconds, and an interruption time is not less than 1 x 10-12 seconds.

Abstract translation: 描述了对导电基板进行电镀的电镀工艺。 该工艺包括通过在阴极和阳极之间重复施加电压并使阴极和阳极之间的电压中断，在阳极和阴极之间以恒定电压将衬底表面作为阴极和电镀金属作为阳极间歇地电镀到预定的镀层厚度 交替应用。 描述了电压时间/中断时间比为0.1至1.0，电压时间不长于10秒，并且中断时间不小于1×10-12秒。

公开(公告)号：US07794820B2

公开(公告)日：2010-09-14

申请号：US11878165

申请日：2007-07-20

Applicant: Dong Sun Kim ,  Taehoon Kim ,  Jong Seok Song ,  Sam Jin Her ,  Jun Heyoung Park

Inventor： Dong Sun Kim ,  Taehoon Kim ,  Jong Seok Song ,  Sam Jin Her ,  Jun Heyoung Park

IPC: B32B15/00

CPC classification number: H05K3/381 ,  H05K1/0346 ,  H05K3/108 ,  H05K3/146 ,  H05K3/426 ,  H05K3/4644 ,  H05K2201/0154 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/092 ,  Y10S428/901 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/24917

Abstract: Disclosed herein are a printed circuit board and a fabrication method thereof, which can improve electrical properties, shorten processing time, and reduce the thickness of a chip package by achieving an ultra-thin fine circuit pattern. The printed circuit board includes an insulating material; a via-hole formed in a given location of the insulating material; a copper seed layer formed through ion beam surface treatment and vacuum deposition on the surface of the insulating material having the via-hole formed therein; and a copper pattern plating layer formed on a given region of the insulating material, which has the copper seed layer formed thereon, and in the via-hole.

Abstract translation: 这里公开了一种印刷电路板及其制造方法，其可以通过实现超薄精细电路图案来改善电性能，缩短处理时间并减小芯片封装的厚度。 印刷电路板包括绝缘材料; 形成在绝缘材料的给定位置的通孔; 通过离子束表面处理形成的铜籽晶层，并且在其中形成有通孔的绝缘材料的表面上真空沉积; 以及形成在其上形成有铜种子层的绝缘材料的给定区域上的铜图案镀层和通孔。

公开(公告)号：US20100218891A1

公开(公告)日：2010-09-02

申请号：US12776771

申请日：2010-05-10

Applicant: Frank D. Egitto ,  Donald S. Farquhar ,  Voya R. Markovich ,  Mark D. Poliks ,  Douglas O. Powell

Inventor： Frank D. Egitto ,  Donald S. Farquhar ,  Voya R. Markovich ,  Mark D. Poliks ,  Douglas O. Powell

IPC: C09J5/06

CPC classification number: H01L21/4853 ,  H01L23/3735 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/114 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4632 ,  H05K3/4641 ,  H05K3/4688 ,  H05K2201/0141 ,  H05K2201/0191 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10378 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/1092

Abstract: A multi-layered interconnect structure and method of formation. In a first embodiment, first and second liquid crystal polymer (LCP) dielectric layers are directly bonded, respectively, to first and second opposing surface of a thermally conductive layer, with no extrinsic adhesive material bonding the thermally conductive layer with either the first or second LCP dielectric layer. In a second embodiment, first and second 2S1P substructures are directly bonded, respectively, to first and second opposing surfaces of a LCP dielectric joining layer, with no extrinsic adhesive material bonding the LCP dielectric joining layer with either the first or second 2S1P substructures.

Abstract translation: 多层互连结构和形成方法。 在第一实施例中，第一和第二液晶聚合物（LCP）电介质层分别直接接合到导热层的第一和第二相对表面，没有外在粘合材料将导热层与第一或第二液晶聚合物 LCP电介质层。 在第二实施例中，第一和第二2S1P子结构分别直接接合到LCP电介质接合层的第一和第二相对表面，没有外部粘合材料将LCP电介质接合层与第一或第二2S1P子结构结合。