公开(公告)号：US07142000B2

公开(公告)日：2006-11-28

申请号：US10673686

申请日：2003-09-29

Applicant: Benjamin N. Eldridge ,  Gary W. Grube ,  Igor Y. Khandros ,  Gaetan L. Mathieu

Inventor： Benjamin N. Eldridge ,  Gary W. Grube ,  Igor Y. Khandros ,  Gaetan L. Mathieu

IPC: G01R31/28 ,  G01R1/073

CPC classification number: H05K7/1069 ,  B23K1/0008 ,  B23K20/004 ,  B23K2101/40 ,  C23C18/1605 ,  C23C18/165 ,  C25D5/08 ,  C25D5/22 ,  C25D7/12 ,  C25D21/02 ,  G01R1/07342 ,  G01R31/2856 ,  G01R31/2863 ,  G01R31/2884 ,  G01R31/2886 ,  H01L21/4853 ,  H01L21/4889 ,  H01L21/563 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/49811 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/27 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/72 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L24/94 ,  H01L25/0652 ,  H01L25/16 ,  H01L2223/54453 ,  H01L2224/02311 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0558 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/11003 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1147 ,  H01L2224/1184 ,  H01L2224/13022 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13582 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/16145 ,  H01L2224/274 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4556 ,  H01L2224/45572 ,  H01L2224/45599 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/48844 ,  H01L2224/49109 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2224/83851 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/90 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01R12/52 ,  H05K1/141 ,  H05K3/20 ,  H05K3/308 ,  H05K3/326 ,  H05K3/3421 ,  H05K3/3426 ,  H05K3/368 ,  H05K3/4015 ,  H05K3/4092 ,  H05K2201/0397 ,  H05K2201/068 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10378 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/10757 ,  H05K2201/10878 ,  H05K2201/10909 ,  H05K2201/10946 ,  Y02P70/611 ,  Y02P70/613 ,  Y10S977/712 ,  Y10S977/723 ,  Y10T29/49004 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49169 ,  Y10T29/49171 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/4922 ,  Y10T29/49812 ,  Y10T428/12396 ,  Y10T428/12528 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/48824 ,  H01L2224/48744 ,  H01L2224/29099 ,  H01L2224/29075 ,  H01L2224/85399

Abstract: Resilient contact structures are mounted directly to bond pads on semiconductor dies, prior to the dies being singulated (separated) from a semiconductor wafer. This enables the semiconductor dies to be exercised (e.g., tested and/or burned-in) by connecting to the semiconductor dies with a circuit board or the like having a plurality of terminals disposed on a surface thereof. Subsequently, the semiconductor dies may be singulated from the semiconductor wafer, whereupon the same resilient contact structures can be used to effect interconnections between the semiconductor dies and other electronic components (such as wiring substrates, semiconductor packages, etc.). Using the all-metallic composite interconnection elements of the present invention as the resilient contact structures, burn-in can be performed at temperatures of at least 150° C., and can be completed in less than 60 minutes.

Abstract translation: 弹性接触结构直接安装在半导体晶片上的接合焊盘上，在裸片与半导体晶片分离（分离）之前。 这使得半导体管芯能够通过具有设置在其表面上的多个端子的电路板等连接到半导体管芯来进行（例如，测试和/或烧入）。 接下来，半导体管芯可以从半导体晶片分离，因此可以使用相同的弹性接触结构来实现半导体管芯和其他电子部件（例如布线基板，半导体封装等）之间的互连。 使用本发明的全金属复合互连元件作为弹性接触结构，可以在至少150℃的温度下进行老化，并且可以在少于60分钟内完成。

公开(公告)号：US20060009053A1

公开(公告)日：2006-01-12

申请号：US11186617

申请日：2005-07-21

Applicant: Peter Broghammer ,  Peter Wahl

Inventor： Peter Broghammer ,  Peter Wahl

IPC: H01R12/00

CPC classification number: H05K3/303 ,  H01H9/06 ,  H01H2001/5888 ,  H01H2011/0087 ,  H05K2201/10318 ,  H05K2201/10424 ,  Y02P70/613

Abstract: An electrical switch for an electric device is provided, including a contact system including at least one electrical power supply line, an electronic control circuit and an electrical connection element arranged between at least one contact face of the control circuit and the power supply line. The electrical connection element has at least one metal pin that is fixed in an electrically non-conductive fixing element such that the pin is aligned with respect to the contact face and the power supply line, and such that the pin protrudes from the fixing element on both sides thereof to contact the contact face and the power supply line.

Abstract translation: 提供了一种用于电气设备的电气开关，包括包括至少一个电源线，电子控制电路和布置在控制电路的至少一个接触面与电源线之间的电连接元件的接触系统。 电连接元件具有固定在非导电固定元件中的至少一个金属销，使得销相对于接触面和电源线对准，并且使得销从固定元件上突出 其两侧接触接触面和电源线。

公开(公告)号：US20050277310A1

公开(公告)日：2005-12-15

申请号：US11197034

申请日：2005-08-04

Applicant: Joseph Dibene ,  David Hartke ,  Carl Hoge ,  Edward Derian

Inventor： Joseph Dibene ,  David Hartke ,  Carl Hoge ,  Edward Derian

IPC: G06F1/18 ,  G06F1/20 ,  H01L23/427 ,  H01L23/433 ,  H01R12/00 ,  H01R12/04 ,  H01R13/24 ,  H05K1/02 ,  H05K1/14 ,  H05K3/30 ,  H05K3/36 ,  H05K7/10 ,  H05K7/20

CPC classification number: H05K7/1092 ,  G06F1/18 ,  G06F1/182 ,  G06F1/189 ,  G06F1/20 ,  H01L23/427 ,  H01L23/433 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/15192 ,  H01L2924/15312 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01R12/52 ,  H01R12/57 ,  H01R13/24 ,  H05K1/0206 ,  H05K1/0262 ,  H05K1/0263 ,  H05K1/141 ,  H05K1/144 ,  H05K1/182 ,  H05K3/301 ,  H05K3/368 ,  H05K2201/10189 ,  H05K2201/10318 ,  H05K2201/10325 ,  H05K2201/10598 ,  H05K2201/10689 ,  H05K2201/10704 ,  H05K2201/10734 ,  H05K2201/2018 ,  Y10T29/49124

Abstract: A power interconnection system comprising a plurality of z-axis compliant connectors passing power and ground signals between a first circuit board to a second circuit board is disclosed. The interconnection system provides for an extremely low impedance through a broad range of frequencies and allows for large amounts of current to pass from one substrate to the next either statically or dynamically. The interconnection system may be located close to the die or may be further away depending upon the system requirements. The interconnection may also be used to take up mechanical tolerances between the two substrates while providing a low impedance. interconnect.

Abstract translation: 公开了一种电源互连系统，其包括在第一电路板到第二电路板之间传递电力和接地信号的多个z轴兼容的连接器。 互连系统通过宽范围的频率提供极低的阻抗，并允许大量的电流从静电或动态从一个衬底传递到下一个衬底。 互连系统可以靠近模具定位，或者可以根据系统要求进一步远离。 互连也可用于在提供低阻抗的同时承受两个基板之间的机械公差。 互连。

公开(公告)号：US20050275094A1

公开(公告)日：2005-12-15

申请号：US10626117

申请日：2003-07-23

Applicant: Michele Berry

Inventor： Michele Berry

IPC: H01L21/48 ,  H01L23/498 ,  H05K3/34 ,  H01L21/44

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15312 ,  H05K3/3421 ,  H05K2201/10318 ,  H05K2201/10977 ,  H05K2203/1189 ,  Y02P70/613 ,  H01L2224/05599

Abstract: Solder joints coupling pins to a microelectronic package substrate are enshrouded with an encapsulation material. In this manner, pin movement is limited even if the pin solder subsequently melts.

Abstract translation: 将引脚连接到微电子封装衬底的焊接接头与封装材料一起包围。 以这种方式，即使引脚焊料随后熔化，引脚移动也受到限制。

公开(公告)号：US20050257958A1

公开(公告)日：2005-11-24

申请号：US11189999

申请日：2005-07-27

Applicant: Aneta Wyrzykowska ,  Herman Kwong ,  Luigi Difilippo

Inventor： Aneta Wyrzykowska ,  Herman Kwong ,  Luigi Difilippo

IPC: H05K1/11 ,  H05K3/30 ,  H05K3/46

CPC classification number: H05K1/112 ,  H01L2224/14 ,  H01L2224/17 ,  H01L2924/00014 ,  H05K3/303 ,  H05K3/4623 ,  H05K2201/09472 ,  H05K2201/09518 ,  H05K2201/09536 ,  H05K2201/10318 ,  H05K2201/10424 ,  H05K2201/10659 ,  H05K2201/10704 ,  H05K2201/10734 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/49139 ,  Y10T29/49147 ,  Y10T29/49165 ,  H01L2224/0401

Abstract: A method for implementing a circuit component on a surface of a multilayer circuit board is provided. The circuit component includes a plurality of pins and the circuit board includes a plurality of electrically conductive vias penetrating at least one layer of the circuit board and being arranged so as to form at least one channel for routing one or more traces at one or more signal layers of the circuit board. The method comprises the step of forming at least one pin of the plurality of pins of the circuit component to have a length compatible with a depth of a corresponding via of the circuit board.

公开(公告)号：US20050155791A1

公开(公告)日：2005-07-21

申请号：US10846923

申请日：2004-05-17

Applicant: Hajime Saiki

Inventor： Hajime Saiki

IPC: H01L23/12 ,  H01L23/498 ,  H05K1/11 ,  H05K3/46

CPC classification number: H05K1/112 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15312 ,  H01L2924/19105 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10318 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A multilayer wiring board includes a substrate, a first planar conductor layer, a second planar conductor layer, resin dielectric layers, filled vias, and stacked via structures. Each of the stacked via structures is disposed in the resin dielectric layers and is configured such that the filled vias are stacked substantially coaxially and are mutually connected together. A first end of the stacked via structure is connected directly to either the first planar conductor layer or the second planar conductor layer. A second end of the stacked via structure is unconnected, directly, to both the first planar conductor layer and the second planar conductor layer.

Abstract translation: 多层布线基板包括基板，第一平面导体层，第二平面导体层，树脂电介质层，填充的通孔和堆叠的通孔结构。 层叠的通孔结构中的每一个设置在树脂电介质层中，并且构造成使得填充的通孔基本上同轴地堆叠并且相互连接在一起。 堆叠通孔结构的第一端直接连接到第一平面导体层或第二平面导体层。 层叠通孔结构的第二端直接与第一平面导体层和第二平面导体层两者不连接。

公开(公告)号：US20050035347A1

公开(公告)日：2005-02-17

申请号：US10889334

申请日：2004-07-12

Applicant: Igor Khandros ,  A. Sporck ,  Benjamin Eldridge

Inventor： Igor Khandros ,  A. Sporck ,  Benjamin Eldridge

IPC: B23K1/00 ,  B23K20/00 ,  C23C18/16 ,  C25D5/08 ,  C25D5/22 ,  C25D7/12 ,  C25D21/02 ,  G01R1/04 ,  G01R1/067 ,  G01R1/073 ,  G01R31/28 ,  H01L21/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/60 ,  H01L21/603 ,  H01L21/66 ,  H01L23/48 ,  H01L23/485 ,  H01L23/49 ,  H01L23/498 ,  H01L25/065 ,  H01L25/16 ,  H05K1/14 ,  H05K3/20 ,  H05K3/30 ,  H05K3/32 ,  H05K3/34 ,  H05K3/36 ,  H05K3/40 ,  H05K7/10 ,  H01L23/58

CPC classification number: H05K3/4015 ,  B23K1/0016 ,  B23K20/004 ,  B23K2101/40 ,  C25D5/08 ,  C25D5/22 ,  C25D21/02 ,  G01R1/06711 ,  G01R1/07342 ,  G01R1/07364 ,  G01R1/07378 ,  G01R31/2886 ,  H01L21/4853 ,  H01L21/4889 ,  H01L21/563 ,  H01L21/76897 ,  H01L22/20 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/49 ,  H01L24/72 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/16 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/45014 ,  H01L2224/45144 ,  H01L2224/49109 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2224/85201 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2924/0001 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01R12/52 ,  H05K1/141 ,  H05K3/20 ,  H05K3/308 ,  H05K3/326 ,  H05K3/3421 ,  H05K3/3426 ,  H05K3/368 ,  H05K3/4092 ,  H05K7/1069 ,  H05K2201/0397 ,  H05K2201/068 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10378 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/10757 ,  H05K2201/10878 ,  H05K2201/10909 ,  H05K2201/10946 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05599

Abstract: In a probe card assembly, a series of probe elements can be arrayed on a silicon space transformer. The silicon space transformer can be fabricated with an array of primary contacts in a very tight pitch, comparable to the pitch of a semiconductor device. One preferred primary contact is a resilient spring contact. Conductive elements in the space transformer are routed to second contacts at a more relaxed pitch. In one preferred embodiment, the second contacts are suitable for directly attaching a ribbon cable, which in turn can be connected to provide selective connection to each primary contact. The silicon space transformer is mounted in a fixture that provides for resilient connection to a wafer or device to be tested. This fixture can be adjusted to planarize the primary contacts with the plane of a support probe card board.

Abstract translation: 在探针卡组件中，可以将一系列探针元件排列在硅空间变压器上。 硅空间变压器可以以与半导体器件的间距相当的非常紧密的间距的主要触点阵列制造。 一个优选的主要接触是弹性弹簧接触。 空间变压器中的导电元件以更放松的间距被路由到第二触点。 在一个优选实施例中，第二触点适于直接连接带状电缆，带状电缆又可连接以提供对每个主触点的选择性连接。 硅空间变压器安装在固定装置中，其提供与待测试的晶片或装置的弹性连接。 可以调整该夹具以使主触头与支撑探针卡板的平面平坦化。

公开(公告)号：US06835597B2

公开(公告)日：2004-12-28

申请号：US10603812

申请日：2003-06-26

Applicant: Kei Murayama

Inventor： Kei Murayama

IPC: H01L2144

CPC classification number: H05K1/111 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/3025 ,  H05K3/3436 ,  H05K3/4602 ,  H05K2201/09663 ,  H05K2201/09772 ,  H05K2201/10318 ,  Y02P70/611 ,  H01L2224/0401

Abstract: A semiconductor package provided with an interconnection layer including an interconnection pattern and pad formed on an insulating substrate or insulating layer, a protective layer covering the interconnection layer except at the portion of the pad and the insulating substrate or insulating layer, and an external connection terminal bonded with the pad exposed from the protective layer, the pad to which the external connection terminal is bonded being comprised of a plurality of pad segments, sufficient space being opened for passing an interconnection between pad segments, and the pad segments being comprised of at least one pad segment connected to an interconnection and other pad segments not connected to interconnections.

Abstract translation: 一种半导体封装，其具有包括形成在绝缘基板或绝缘层上的互连图案和焊盘的互连层，覆盖所述焊盘部分以外的所述互连层的保护层和绝缘基板或绝缘层，以及外部连接端子 与从保护层暴露的焊盘接合，外部连接端子被接合到的焊盘由多个焊盘段组成，足够的空间被打开以通过焊盘段之间的互连，并且焊盘段至少包括 连接到互连的一个焊盘段和未连接到互连的其它焊盘段。

公开(公告)号：US20040183212A1

公开(公告)日：2004-09-23

申请号：US10423877

申请日：2003-04-28

Applicant: Endicott Interconnect technologies, Inc.

Inventor： David Alcoe

IPC: H01L023/48 ,  H01L029/40

CPC classification number: H01L23/49838 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/15312 ,  H01L2924/16195 ,  H05K1/113 ,  H05K1/114 ,  H05K1/115 ,  H05K1/116 ,  H05K3/3426 ,  H05K3/4602 ,  H05K2201/09454 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/0979 ,  H05K2201/10318 ,  Y10T29/49149 ,  H01L2224/0401

Abstract: An electronic package and information handling system utilizing same wherein the package substrate includes an internally conductive layer coupled to an external pad and of a size sufficiently large enough to substantially prevent cracking, separation, etc. of the pad when the pad is subjected to a tensile pressure of about 1.4 grams per square mil or greater.

Abstract translation: 一种利用其的电子封装和信息处理系统，其中封装衬底包括耦合到外部焊盘的内部导电层，并且具有足够大的尺寸以足以基本上防止衬垫经受拉伸时的焊盘的开裂，分离等 约1.4克/平方密度或更大的压力。

公开(公告)号：US20040152348A1

公开(公告)日：2004-08-05

申请号：US10749028

申请日：2003-12-30

Applicant: FormFactor, Inc.

Inventor： David V. Pedersen ,  Benjamin N. Eldridge ,  Igor Y. Khandros

IPC: H05K001/00

CPC classification number: H01L25/16 ,  B23K1/0016 ,  B23K20/004 ,  B23K2101/40 ,  C25D5/08 ,  C25D5/22 ,  C25D21/02 ,  G01R1/0408 ,  G01R1/0433 ,  G01R1/06711 ,  G01R1/07342 ,  G01R1/07378 ,  G01R31/01 ,  G01R31/2863 ,  G01R31/2886 ,  G01R31/2889 ,  H01L21/4853 ,  H01L21/4889 ,  H01L21/563 ,  H01L22/20 ,  H01L23/04 ,  H01L23/13 ,  H01L23/32 ,  H01L23/49811 ,  H01L23/5385 ,  H01L24/06 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/45 ,  H01L24/49 ,  H01L24/72 ,  H01L24/81 ,  H01L25/0652 ,  H01L2223/54473 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/45144 ,  H01L2224/49109 ,  H01L2224/73203 ,  H01L2224/81136 ,  H01L2224/81801 ,  H01L2224/85201 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/19043 ,  H05K1/141 ,  H05K3/20 ,  H05K3/325 ,  H05K3/326 ,  H05K3/3421 ,  H05K3/368 ,  H05K3/4015 ,  H05K2201/09472 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10757 ,  H05K2201/10878 ,  H05K2201/10909 ,  H05K2201/10946 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/48

Abstract: Products and assemblies are provided for socketably receiving elongate interconnection elements, such as spring contact elements, extending from electronic components, such as semiconductor devices. Socket substrates are provided with capture pads for receiving ends of elongate interconnection elements extending from electronic components. Various capture pad configurations are disclosed. Connections to external devices are provided via conductive traces adjacent the surface of the socket substrate. The socket substrate may be supported by a support substrate. In a particularly preferred embodiment the capture pads are formed directly on a primary substrate such as a printed circuit board.

Abstract translation: 提供产品和组件用于可插拔地接收从电子部件（例如半导体器件）延伸的细长互连元件，例如弹簧接触元件。 插座基板设置有用于接收从电子部件延伸的细长互连元件的端部的捕获垫。 公开了各种捕获垫结构。 通过邻近插座基板表面的导电迹线提供与外部设备的连接。 插座基板可以由支撑基板支撑。 在特别优选的实施例中，捕获垫直接形成在诸如印刷电路板的主要基底上。