公开(公告)号：US20240387239A1

公开(公告)日：2024-11-21

申请号：US18209488

申请日：2023-06-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Tsang Chen ,  Chia-Ching Lin ,  Wen-Liang Huang

IPC: H01L21/762 ,  H01L21/8234 ,  H01L29/66

Abstract: A manufacturing method of a semiconductor structure includes the following steps. Fin-shaped structures are formed by patterning a first region of a semiconductor substrate. A first shallow trench is formed in a second region of the semiconductor substrate. A part of the semiconductor substrate is exposed by a bottom of the first shallow trench. A first etching process is performed. At least a part of one of the fin-shaped structures is removed by the first etching process, and the part of the semiconductor substrate exposed by the first shallow trench is partially removed by the first etching process for forming a first deep trench. The manufacturing method of the present invention may be used to achieve the purposes of process simplification and/or manufacturing cost reduction.

公开(公告)号：US12150313B2

公开(公告)日：2024-11-19

申请号：US18500994

申请日：2023-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Rong Wu ,  I-Fan Chang ,  Rai-Min Huang ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H10B61/00 ,  G11C11/16 ,  H01F10/32 ,  H01F41/34 ,  H01L23/522 ,  H01L23/528 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a MTJ on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes a stripe pattern according to a top view and the blocking layer could include metal or a dielectric layer.

公开(公告)号：US20240379670A1

公开(公告)日：2024-11-14

申请号：US18206609

申请日：2023-06-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Ting Hu ,  Chih-Yi Wang ,  Yao-Jhan Wang ,  Wei-Che Chen ,  Kun-Szu Tseng ,  Yun-Yang He ,  Wen-Liang Huang ,  Lung-En Kuo ,  Po-Tsang Chen ,  Po-Chang Lin ,  Ying-Hsien Chen

IPC: H01L27/088 ,  H01L21/762

Abstract: A semiconductor device includes a substrate with a high voltage region and a low voltage region. A first deep trench isolation is disposed within the high voltage region. The first deep trench isolation includes a first deep trench and a first insulating layer filling the first deep trench. The first deep trench includes a first sidewall and a second sidewall facing the first sidewall. The first sidewall is formed by a first plane and a second plane. The edge of the first plane connects to the edge of the second plane. The slope of the first plane is different from the slope of the second plane.

公开(公告)号：US20240371855A1

公开(公告)日：2024-11-07

申请号：US18772301

申请日：2024-07-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Lin ,  Chien-Ting Lin ,  Chia-Jung Hsu ,  Chun-Ya Chiu ,  Chin-Hung Chen

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, a HV device on the HV region, and a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is lower than a top surface of the fin-shaped structure.

公开(公告)号：US20240365563A1

公开(公告)日：2024-10-31

申请号：US18762663

申请日：2024-07-03

Applicant: UNITED MICROELECTRONICS CORP

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Hung-Yueh Chen ,  Wei Chen

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10B61/22 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A semiconductor device including a magnetic tunneling junction (MTJ) and a hard mask on a substrate, a first inter-metal dielectric (IMD) layer around the MTJ, a first metal interconnection adjacent to the MTJ, a first barrier layer and a channel layer on the first IMD layer to directly contact the hard mask and electrically connect the MTJ and the first metal interconnection, and a stop layer around the channel layer.

公开(公告)号：US12131993B2

公开(公告)日：2024-10-29

申请号：US18191894

申请日：2023-03-29

Applicant: United Microelectronics Corp.

Inventor： To-Wen Tsao ,  Ching-Chang Hsu

IPC: H01L23/528 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L23/5221

Abstract: An interconnect structure is formed on a substrate in a semiconductor device. The interconnect structure includes a dielectric layer and a metal layer. The dielectric layer includes a region and a plurality of protrusions. The metal layer is disposed on the region and between the protrusions, wherein tops of the protrusions are exposed with respect to the metal layer. In a top view of the semiconductor device, the protrusions are distributed in the region. Any straight path crossing through a central region of the region is always intersected with a portion of the protrusions.

公开(公告)号：US12131976B2

公开(公告)日：2024-10-29

申请号：US17037542

申请日：2020-09-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin

IPC: H01L23/36 ,  H01L21/768 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/48 ,  H01L23/485 ,  H01L25/00 ,  H01L25/07

CPC classification number: H01L23/3677 ,  H01L21/76898 ,  H01L23/3735 ,  H01L23/481 ,  H01L23/485 ,  H01L24/08 ,  H01L24/32 ,  H01L25/074 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/32145 ,  H01L2224/32225

Abstract: A semiconductor structure with a heat dissipation structure includes a first device wafer includes a front side and a back side. A first transistor is disposed on the front side. The first transistor includes a first gate structure disposed on the front side. Two first source/drain doping regions are embedded within the first device wafer at two side of the first gate structure. A channel region is disposed between the two first source/drain doping regions and embedded within the first device wafer. A first dummy metal structure contacts the back side of the first device wafer, and overlaps the channel region.

公开(公告)号：US20240355887A1

公开(公告)日：2024-10-24

申请号：US18757558

申请日：2024-06-28

Applicant: United Microelectronics Corp.

Inventor： Chih-Tung Yeh

IPC: H01L29/40 ,  H01L29/08 ,  H01L29/417 ,  H01L21/225 ,  H01L29/45 ,  H01L29/778

CPC classification number: H01L29/401 ,  H01L29/0843 ,  H01L29/41725 ,  H01L21/2258 ,  H01L29/452 ,  H01L29/7786

Abstract: A semiconductor device includes a III-V compound semiconductor layer and a source/drain structure. The source/drain structure is disposed on the III-V compound semiconductor layer. The source/drain structure includes a metal layer and metal silicide patterns. The metal layer is disposed on the metal silicide patterns, and a portion of the metal layer is disposed between the metal silicide patterns adjacent to each other.

公开(公告)号：US12127413B2

公开(公告)日：2024-10-22

申请号：US18113070

申请日：2023-02-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Tai-Cheng Hou ,  Hsin-Jung Liu ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Ang Chan ,  Chih-Yueh Li ,  Chun-Tsen Lu

IPC: H10B61/00 ,  G11C11/16 ,  H01F10/32 ,  H01F41/34 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/00 ,  G11C11/161 ,  H01F10/3254 ,  H01F41/34 ,  H10N50/01 ,  H10N50/80

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ, a passivation layer on the first ULK dielectric layer, and a second ULK dielectric layer on the passivation layer. Preferably, the first ULK dielectric layer includes a first thickness, the passivation layer between the first MTJ and the second MTJ includes a second thickness, the passivation layer on top of the first MTJ includes a third thickness, and the second thickness is greater than the third thickness

公开(公告)号：US20240349493A1

公开(公告)日：2024-10-17

申请号：US18754195

申请日：2024-06-26

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yi-Wei Chen ,  Hsu-Yang Wang ,  Chun-Chieh Chiu ,  Shih-Fang Tzou

IPC: H10B12/00 ,  H01L21/768

CPC classification number: H10B12/485 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76819 ,  H01L21/76895 ,  H10B12/053 ,  H10B12/482

Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.