公开(公告)号：US20070125575A1

公开(公告)日：2007-06-07

申请号：US11634170

申请日：2006-12-06

Applicant: Yasuhiko Inui ,  Takamichi Ogawa ,  Seiji Ichiyanagi ,  Jun Otsuka ,  Manabu Sato

Inventor： Yasuhiko Inui ,  Takamichi Ogawa ,  Seiji Ichiyanagi ,  Jun Otsuka ,  Manabu Sato

IPC: H05K1/00

CPC classification number: H05K1/162 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/092 ,  H05K3/4644 ,  H05K2201/0175 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2201/09736 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/4981 ,  Y10T407/1946 ,  Y10T407/1948 ,  H01L2924/00

Abstract: A dielectric structure comprising: a metal foil; a dielectric layer; and a conductor layer provided in this order, wherein the metal foil has a thickness of from 10 to 40 μm, the dielectric layer has a thickness of from 0.3 to 5 μm, and the conductor layer has a thickness of from 0.3 to 10 μm, the dielectric structure has plural vias which are separated from each other, and which penetrate through both of the dielectric layer and the conductor layer, and the vias of the dielectric layer have different diameters which are in a range of from 100 to 300 μm, a diameter of each of the vias of the conductor layer is larger than a diameter of a corresponding via of the dielectric layer by 5 to 50 μm, and a minimum via pitch is from 100 to 350 μm.

Abstract translation: 一种电介质结构，包括：金属箔; 电介质层; 以及依次设置的导电体层，其中，所述金属箔的厚度为10〜40μm，所述电介质层的厚度为0.3〜5μm，所述导体层的厚度为0.3〜10μm， 电介质结构具有彼此分离并且穿透介电层和导体层两者的多个通孔，并且电介质层的通孔具有不同的直径，其范围为100-300μm，a 导体层的每个通孔的直径大于电介质层的相应通孔的直径为5至50μm，最小通孔间距为100至350μm。

公开(公告)号：US20070104926A1

公开(公告)日：2007-05-10

申请号：US11595088

申请日：2006-11-09

Applicant: Christian Goebl ,  Rainer Popp

Inventor： Christian Goebl ,  Rainer Popp

IPC: B32B15/04 ,  B32B3/02

CPC classification number: H01L25/165 ,  H01L23/3675 ,  H01L24/33 ,  H01L25/162 ,  H01L2924/1301 ,  H01L2924/13091 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/366 ,  H05K7/20445 ,  H05K7/209 ,  H05K2201/0352 ,  H05K2201/049 ,  H05K2201/09736 ,  H05K2201/10674 ,  Y10T428/24777 ,  Y10T428/31678 ,  H01L2924/00

Abstract: A frequency converter is presented. The frequency converter includes a circuit module, which is interconnected to a circuit board and is connected to a heat sink. For attaining a frequency converter in a modular version with optimal cooling properties, the circuit module has a flexible, electrically insulating plastic film, which on one side has a circuit-structured logic metal layer and on the opposite side has a circuit-structured power metal layer that is contacted with a contact edge to a peripheral portion of the circuit board. The flexible circuit module protrudes at an angle away from the circuit board. Power semiconductor chips are contacted on the power metal layer. A substrate is secured to the heat sink and is embodied with a circuit structure for contacting the power semiconductor chips.

Abstract translation: 提出了一种变频器。 变频器包括电路模块，其连接到电路板并连接到散热器。 为了以具有最佳冷却特性的模块化版本获得变频器，电路模块具有柔性的电绝缘塑料膜，其一侧具有电路结构的逻辑金属层，并且在相对侧上具有电路结构的功率金属 该层与电路板的周边部分的接触边缘接触。 柔性电路模块以远离电路板的角度突出。 功率半导体芯片在功率金属层上接触。 基板被固定到散热器，并且具有用于接触功率半导体芯片的电路结构。

公开(公告)号：US20070102796A1

公开(公告)日：2007-05-10

申请号：US11595082

申请日：2006-11-09

Applicant: Christian Goebl ,  Karlheinz Augustin

Inventor： Christian Goebl ,  Karlheinz Augustin

IPC: H01L23/02 ,  H01L23/34

CPC classification number: H05K3/4007 ,  H01L23/49833 ,  H01L23/4985 ,  H01L23/5385 ,  H01L23/5387 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/45 ,  H01L24/48 ,  H01L24/50 ,  H01L25/072 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/24226 ,  H01L2224/2518 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/19107 ,  H01L2924/20757 ,  H05K1/0265 ,  H05K1/0393 ,  H05K1/09 ,  H05K3/4046 ,  H05K2201/0352 ,  H05K2201/0367 ,  H05K2201/09736 ,  H05K2201/10166 ,  H05K2203/049 ,  H01L2924/00

Abstract: A power semiconductor module is presented. The power semiconductor module has a substrate, a composite film, and a power semiconductor component between the substrate and the composite film. The composite film has a thin circuit-structured logic metal layer and a thick circuit-structured power metal layer and between them a thin electrically insulating plastic film. The composite film includes contact nubs, which provide bonding to the power semiconductor component. Feedthrough holes are provided between the logic metal layer and the power metal layer. The plastic film in the region of the respective through-plated hole includes a recess in a region that is free of the logic metal layer. A segment of a flexible thin wire extends through the free region of the logic metal layer and through the recess in the plastic film and is bonded to the logic metal layer and the power metal layer by means of bonding sites.

Abstract translation: 介绍了功率半导体模块。 功率半导体模块在基板和复合膜之间具有基板，复合膜和功率半导体部件。 复合膜具有薄的电路结构的逻辑金属层和厚电路结构的功率金属层，并且在它们之间是薄的电绝缘塑料膜。 复合膜包括提供与功率半导体部件的接合的接触凸块。 在逻辑金属层和功率金属层之间提供穿通孔。 在相应的通孔的区域中的塑料膜包括在没有逻辑金属层的区域中的凹部。 柔性细线的一段延伸穿过逻辑金属层的自由区域并穿过塑料膜中的凹槽，并通过结合位点结合到逻辑金属层和功率金属层。

公开(公告)号：US20070087122A1

公开(公告)日：2007-04-19

申请号：US11637715

申请日：2006-12-13

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: B05D1/32

CPC classification number: H01L24/86 ,  H01L21/563 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/0393 ,  H05K1/112 ,  H05K3/242 ,  H05K3/243 ,  H05K3/323 ,  H05K3/422 ,  H05K2201/0352 ,  H05K2201/0391 ,  H05K2201/0394 ,  H05K2203/049 ,  H05K2203/072 ,  H05K2203/0733 ,  H05K2203/1476 ,  H05K2203/1545 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671

Abstract: There is provided a semiconductor device comprising: a first plating layer formed on one surface of an interconnect pattern; a second plating layer formed within through holes in the interconnect pattern; a semiconductor chip electrically connected to the first plating layer; an anisotropic conductive material provided on the first plating layer; and a conductive material provided on the second plating layer, wherein the first plating layer has appropriate adhesion properties with the anisotropic conductive material, and the second plating layer has appropriate adhesion properties with the conductive material.

Abstract translation: 提供了一种半导体器件，包括：形成在互连图案的一个表面上的第一镀层; 形成在所述互连图案中的通孔内的第二镀层; 电连接到第一镀层的半导体芯片; 设置在第一镀层上的各向异性导电材料; 以及设置在所述第二镀层上的导电材料，其中所述第一镀层与所述各向异性导电材料具有适当的粘合性，并且所述第二镀层与所述导电材料具有适当的粘合性能。

公开(公告)号：US20060157826A1

公开(公告)日：2006-07-20

申请号：US11247307

申请日：2005-10-12

Applicant: Hee-seok Lee ,  Un-byoung Kang ,  Yun-hyeok Im

Inventor： Hee-seok Lee ,  Un-byoung Kang ,  Yun-hyeok Im

IPC: H01L23/58

CPC classification number: H05K3/4641 ,  H01L23/66 ,  H01L2924/0002 ,  H05K1/0237 ,  H05K1/09 ,  H05K2201/0338 ,  H05K2201/0352 ,  H01L2924/00

Abstract: A multi-path printed circuit board (PCB) comprising separate direct current (DC) and alternating current (AC) paths, and a power delivery system including the same are provided. The multi-path PCB comprises a plurality of planar layers, each comprising a metal layer, and a plurality of insulators interposed between the planar layers. The metal layers may have different conductivities. The power delivery system includes a power source, a semiconductor IC, and the multi-path PCB. The multi-path PCB is adapted to function as a power delivery path for delivering power from the power source to the semiconductor IC.

Abstract translation: 提供了包括单独的直流（DC）和交流（AC）路径的多路径印刷电路板（PCB），以及包括其的电力输送系统。 多路径PCB包括多个平面层，每个平面层包括金属层，以及介于平面层之间的多个绝缘体。 金属层可以具有不同的电导率。 电力输送系统包括电源，半导体IC和多路PCB。 多路径PCB适于用作将功率从电源传送到半导体IC的功率传递路径。

公开(公告)号：US20060131616A1

公开(公告)日：2006-06-22

申请号：US11018948

申请日：2004-12-21

Applicant: Douglas Devaney ,  David Lueneburg

Inventor： Douglas Devaney ,  David Lueneburg

IPC: H01L29/768 ,  H01L27/148

CPC classification number: A61B5/14532 ,  A61B5/1486 ,  A61B2562/02 ,  H05K1/09 ,  H05K3/108 ,  H05K3/388 ,  H05K2201/0141 ,  H05K2201/0352

Abstract: This invention relates to a copperless flexible circuit; more particularly, a two-sided copperless flexible circuit.

Abstract translation: 本发明涉及无铜柔性电路; 更具体地，是双面无铜柔性电路。

公开(公告)号：US20060051952A1

公开(公告)日：2006-03-09

申请号：US11079389

申请日：2005-03-15

Applicant: Shih-Ping Hsu ,  Sao-Hsia Tang ,  Ying-Tung Wang ,  Wen-Hung Hu ,  Chao-Wen Shih ,  Meng-Da Chou

Inventor： Shih-Ping Hsu ,  Sao-Hsia Tang ,  Ying-Tung Wang ,  Wen-Hung Hu ,  Chao-Wen Shih ,  Meng-Da Chou

IPC: H01L21/44

CPC classification number: H05K3/3473 ,  H01L21/4853 ,  H01L23/49816 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H05K3/242 ,  H05K3/4602 ,  H05K2201/0352 ,  H05K2201/09436 ,  H05K2201/096 ,  H05K2203/043 ,  H05K2203/054 ,  H05K2203/0574 ,  H05K2203/1476 ,  H05K2203/1572 ,  H05K2203/1581 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method for fabricating conductive bumps of a circuit board is proposed. First of all, a circuit board having a first surface and a corresponding second surface is provided. A circuit structure having a plurality of conductive pads is formed on each of the first surface and the second surface, and conductive structures are formed in the circuit board for electrically connecting the circuit structures. Also, an insulating layer having a plurality of openings penetrating therethrough is formed on the circuit board for exposing the conductive pad. Then, a conductive layer is formed on a surface of the insulating layer having the opening formed on the first surface of the circuit board. An electroplating process is performed via the conductive layer and the conductive structure, such that a conductive bump is formed on the conductive pad located on the second surface of the circuit board. Subsequently, a resist layer is formed on the second surface of the circuit board to cover the conductive bump, and another resist layer having openings penetrating therethrough is formed on the first surface of the circuit board to expose the conductive pad. Finally, a conductive bump is formed on the conductive pad located on the first surface of the circuit board by an electroplating process. By such arrangement, the conductive bumps are successively formed on the first surface and the second surface of the circuit board.

Abstract translation: 提出了一种用于制造电路板的导电凸块的方法。 首先，提供具有第一表面和相应的第二表面的电路板。 在所述第一表面和所述第二表面中的每一个上形成具有多个导电焊盘的电路结构，并且在所述电路板中形成导电结构以电连接所述电路结构。 此外，在电路板上形成具有贯穿其中的多个开口的绝缘层，用于暴露导电焊盘。 然后，在具有形成在电路板的第一表面上的开口的绝缘层的表面上形成导电层。 通过导电层和导电结构进行电镀处理，使得在位于电路板的第二表面上的导电焊盘上形成导电凸块。 随后，在电路板的第二表面上形成抗蚀剂层以覆盖导电凸块，并且在电路板的第一表面上形成具有贯穿其中的开口的另一个抗蚀剂层，以露出导电焊盘。 最后，通过电镀工艺在位于电路板的第一表面上的导电焊盘上形成导电凸块。 通过这种布置，导电凸块依次形成在电路板的第一表面和第二表面上。

公开(公告)号：US06967152B1

公开(公告)日：2005-11-22

申请号：US10686315

申请日：2003-10-15

Applicant: Phillip L. Jordan ,  John P. Yarno ,  Jeffery A. Strole ,  Mikhail P. Bak ,  Joseph R. Ketterl

Inventor： Phillip L. Jordan ,  John P. Yarno ,  Jeffery A. Strole ,  Mikhail P. Bak ,  Joseph R. Ketterl

IPC: H01L21/44 ,  H05K3/10 ,  H05K3/28 ,  H05K3/46

CPC classification number: H05K3/107 ,  H05K3/28 ,  H05K3/46 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/0352 ,  H05K2201/09036

Abstract: A method of producing a multi-level electronic device that begins with machining into a sheet of dielectric material from a surface to create a set of first indentations at a first level. Conductive material is then deposited into the first indentations to create a set of first conductive features. The first indentations are then substantially filled with dielectric material. The process is continued by machining again into the sheet of dielectric material from a surface and thereby creating a set of second indentations at a second level. Further conductive material is deposited into the second indentations to create a set of second conductive features.

Abstract translation: 一种制造多级电子装置的方法，该多级电子装置首先从表面机械加工成电介质材料片，以在一级形成一组第一压痕。 然后将导电材料沉积到第一压痕中以产生一组第一导电特征。 然后，第一压痕基本上被介电材料填充。 该过程通过从表面再次进入介电材料片继续进行，从而在第二级创建一组第二压痕。 另外的导电材料沉积到第二压痕中以产生一组第二导电特征。

公开(公告)号：US20050253235A1

公开(公告)日：2005-11-17

申请号：US11116046

申请日：2005-04-27

Applicant: Kazumi Hara

Inventor： Kazumi Hara

IPC: H01L23/29 ,  H01L23/00 ,  H01L23/02 ,  H01L23/31 ,  H01L29/06 ,  H05K1/02

CPC classification number: H01L23/562 ,  H01L23/3171 ,  H01L29/0657 ,  H01L2924/0002 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K2201/0166 ,  H05K2201/0352 ,  H05K2201/068 ,  H05K2201/09136 ,  H05K2201/09736 ,  H05K2201/09909 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A semiconductor chip is provided that is highly packageable and particularly well suited for mounting on a circuit board having a curved surface. The semiconductor chip comprises a warpage control film that controls the warpage of a substrate.

Abstract translation: 提供了一种高度可封装的半导体芯片，特别适用于安装在具有曲面的电路板上。 半导体芯片包括控制基板翘曲的翘曲控制膜。

公开(公告)号：US20050190017A1

公开(公告)日：2005-09-01

申请号：US11119225

申请日：2005-04-29

Applicant: Takayuki Hirabayashi

Inventor： Takayuki Hirabayashi

IPC: H05K3/46 ,  H01P1/203 ,  H01P3/08 ,  H01P7/08 ,  H05K1/16 ,  H05K3/02

CPC classification number: H01P1/20345 ,  H01L2224/16225 ,  H01L2924/15184 ,  H01L2924/16152 ,  H01P1/203 ,  H05K1/16 ,  H05K3/02 ,  H05K3/4644 ,  H05K2201/0352 ,  H05K2201/09236 ,  H05K2201/1006

Abstract: This invention is a filter circuit having a filter element. A filter element (4) is a parallel resonator circuit including a pair of first resonator lines (19a) (19b) formed by a thick film forming technique and a pair of second resonator lines (20a) (20b). As the thickness of the pair of second resonator lines (20a) (20b) is significantly reduced, the impedance ratio between the pair of second resonator lines (20a) (20b) and the pair of first resonator lines (19a) (19b) is increased. Therefore, the length of these pairs of resonator lines (19a) (19b) (20a) (20b) is reduced and miniaturization of the filter element is realized.