公开(公告)号：US08209860B2

公开(公告)日：2012-07-03

申请号：US12552957

申请日：2009-09-02

Applicant: Jin Yong An ,  Seok Kyu Lee

Inventor： Jin Yong An ,  Seok Kyu Lee

IPC: H01R9/00

CPC classification number: H05K3/4007 ,  H05K3/0097 ,  H05K3/4682 ,  H05K2201/0367 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49165 ,  Y10T29/49213 ,  Y10T428/24917

Abstract: Disclosed herein are a printed circuit board having metal bumps which have uniform diameter and are formed at fine pitch, and a method of manufacturing the printed circuit board.

Abstract translation: 这里公开了具有均匀直径并以细间距形成的金属凸块的印刷电路板，以及制造印刷电路板的方法。

公开(公告)号：US20120073867A1

公开(公告)日：2012-03-29

申请号：US13313896

申请日：2011-12-07

Applicant: Chih-Peng Fan ,  Yen-Ti Chia

Inventor： Chih-Peng Fan ,  Yen-Ti Chia

IPC: H05K1/09 ,  H05K1/00

CPC classification number: H05K1/111 ,  H01L2224/16225 ,  H05K3/108 ,  H05K3/243 ,  H05K3/3452 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0989 ,  H05K2201/10674 ,  H05K2203/0574 ,  Y02P70/611 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A circuit structure suitable for being disposed on a carrier board. The circuit structure comprises a first patterned conductive layer, a second patterned conductive layer, and a solder mask. The first patterned conductive layer is disposed on the carrier board. The second patterned conductive layer is disposed on a part of the first patterned conductive layer. A part of the edge of the second patterned conductive layer and a part of the edge of the first patterned conductive layer are substantially coplanar. The patterned solder mask covers a part of the first patterned conductive layer and has at least one opening for exposing the second patterned conductive layer and a part of the first patterned conductive layer adjacent to the second patterned conductive layer.

Abstract translation: 适于布置在载板上的电路结构。 电路结构包括第一图案化导电层，第二图案化导电层和焊接掩模。 第一图案化导电层设置在载体板上。 第二图案化导电层设置在第一图案化导电层的一部分上。 第二图案化导电层的边缘的一部分和第一图案化导电层的边缘的一部分基本上共面。 图案化的焊接掩模覆盖第一图案化导电层的一部分并且具有用于暴露第二图案化导电层的至少一个开口和与第二图案化导电层相邻的第一图案化导电层的一部分。

公开(公告)号：US20120060365A1

公开(公告)日：2012-03-15

申请号：US13373387

申请日：2011-11-14

Applicant: Myung Sam Kang ,  Jeong Woo Park ,  Ok Tae Kim ,  Kil Yong Yun

Inventor： Myung Sam Kang ,  Jeong Woo Park ,  Ok Tae Kim ,  Kil Yong Yun

IPC: H05K3/00

CPC classification number: H05K1/111 ,  H05K1/09 ,  H05K1/115 ,  H05K3/205 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2203/0323 ,  H05K2203/0376 ,  Y02P70/611 ,  Y10T29/49124 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49204 ,  Y10T29/49222

Abstract: A method of manufacturing a printed circuit board having a metal bump, including: forming a recess for creation of the metal bump on a first carrier, forming a first barrier layer on the first carrier, and forming an upper circuit layer on the first barrier layer, the upper circuit layer including a metal bump charged in the recess and a circuit pattern; forming a second barrier layer on a second carrier, and forming a lower circuit layer on the second barrier layer; preparing an insulating layer, and transferring the upper and lower circuit layers to the insulating layer; removing the first and second carriers; and removing the first and second barrier layers.

Abstract translation: 一种制造具有金属凸块的印刷电路板的方法，包括：在第一载体上形成用于形成金属凸块的凹部，在第一载体上形成第一阻挡层，并在第一阻挡层上形成上电路层 所述上电路层包括充电在所述凹部中的金属凸块和电路图案; 在第二载体上形成第二阻挡层，并在第二阻挡层上形成下电路层; 制备绝缘层，并将上下电路层转移到绝缘层; 移除第一和第二载体; 以及去除所述第一和第二阻挡层。

公开(公告)号：US08134225B2

公开(公告)日：2012-03-13

申请号：US12164152

申请日：2008-06-30

Applicant: John J. Maloney ,  Robert M. Smith ,  Charles H. Wilson

Inventor： John J. Maloney ,  Robert M. Smith ,  Charles H. Wilson

IPC: H01L23/495

CPC classification number: H01L23/49548 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15747 ,  H01L2924/181 ,  H05K3/341 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/10689 ,  H05K2201/10727 ,  H05K2201/10969 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A QFN package with improved joint solder thickness for improved second level attachment fatigue life. The copper leadframe of a QFN chip carrier is provided with rounded protrusions in both the chip attach pad region and the surrounding lead regions before second level attachment. The rounded stand-off protrusions are formed from the copper itself of the copper of the leadframe. This may be achieved by punching dimples into one surface of the copper plate of the leadframe before plating to form protrusions on the opposing surface. This method of forming the rounded protrusions simplifies the process of forming stand-offs. The protrusions provide a structure that increases wetting area and allows the use of a larger quantity of solder for increased solder joint thickness and better die paddle solder joint area coverage. As a result of the increased solder joint thickness, second level fatigue life is significantly improved. As a result of the improved die paddle solder joint area coverage, improved thermal performance of the chip carrier is also significantly improved.

Abstract translation: QFN封装，具有改进的焊点厚度，可提高二级附着疲劳寿命。 QFN芯片载体的铜引线框架在第二级附接之前在芯片连接焊盘区域和周围的引线区域中设置有圆形突起。 圆形的突出突起由引线框架的铜的铜本身形成。 这可以通过在电镀之前将凹坑冲压到引线框架的铜板的一个表面中以在相对表面上形成突起来实现。 形成圆形突起的这种方法简化了形成支座的过程。 突起提供了增加润湿面积的结构，并且允许使用更大量的焊料以增加焊接接​​头厚度和更好的焊盘焊接区域覆盖。 由于焊接接头厚度的增加，二级疲劳寿命显着提高。 由于焊盘焊接区域覆盖率的提高，芯片载体的热性能也得到了显着提高。

公开(公告)号：US08119516B2

公开(公告)日：2012-02-21

申请号：US12290873

申请日：2008-11-04

Applicant: Kimitaka Endo

Inventor： Kimitaka Endo

IPC: H01L21/44 ,  H01L23/043

CPC classification number: H05K3/4007 ,  H01L21/4846 ,  H01L21/4853 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81192 ,  H01L2224/81399 ,  H01L2224/81444 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H05K3/20 ,  H05K2201/0367 ,  H05K2203/0113 ,  H01L2924/00014

Abstract: A method for forming a bump structure and a bump structure for conductive interconnection with another element having at least one of microelectronic devices or wiring thereon, used as an electric connection in an electronic circuit, includes the steps of forming a mandrel by steps including forming at least one opening extending through a bump-forming die body in the thickness direction thereof and positioning a bump-forming die lid on a surface of the bump-forming die body so as to cover one end of the opening and to thereby define a bump-forming recess. The bump-forming die body may be comprised of a metal sheet. A metal layer is formed at least on an inner surface of the bump-forming die lid exposed within the bump-forming recess. The mandrel is removed so as to expose the metal layer and form a bump structure.

Abstract translation: 用于形成凸起结构和用于与用于电子电路中的电连接的具有微电子器件或其上的布线的至少一个的另一元件的导电互连的凸块结构的方法包括以下步骤：通过以下步骤形成心轴： 至少一个开口沿其厚度方向延伸穿过凸块成形模体，并将凸块形成模具盖定位在凸块形成模具主体的表面上，以覆盖开口的一端， 形成凹槽。 凸块形成模体可以由金属板构成。 至少在凸块形成用模具盖的内表面上形成金属层，露出在凸块形成凹部内。 去除心轴以露出金属层并形成凸块结构。

公开(公告)号：US08110921B2

公开(公告)日：2012-02-07

申请号：US12616324

申请日：2009-11-11

Applicant: Yuji Kunimoto

Inventor： Yuji Kunimoto

IPC: H01L23/34

CPC classification number: H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0655 ,  H01L2224/02333 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K1/185 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2201/10674 ,  H05K2203/1469

Abstract: A plurality of semiconductor devices having different thicknesses from each other and having respective electrode terminals are fixed on a surface of the support plate through a resin layer in such a manner that terminal surfaces of the electrode terminals are on the level with each other. An insulating layer covers terminal forming surfaces of the semiconductor devices. At least one tapered bump having a tip surface formed in a smaller area than an area of the terminal surface of the electrode terminal of the semiconductor device is formed on one of the terminal surfaces of the electrode terminals and penetrates the insulating layer in such a manner that the tip surface of the tapered bump is exposed to a surface of the insulating layer. A wiring pattern is formed on the surface of the insulating layer and connected to the tip surface of the tapered bump.

Abstract translation: 多个具有彼此不同厚度且具有各个电极端子的半导体器件通过树脂层固定在支撑板的表面上，使得电极端子的端子表面彼此水平。 绝缘层覆盖半导体器件的端子形成表面。 在电极端子的一个端子表面上形成至少一个具有形成在比半导体器件的电极端子的端面的面积小的区域中的尖端表面的锥形凸块，并以这种方式穿透绝缘层 锥形突起的尖端表面暴露于绝缘层的表面。 在绝缘层的表面上形成有与锥形突起的前端面相连接的布线图形。

公开(公告)号：US08084349B2

公开(公告)日：2011-12-27

申请号：US12752896

申请日：2010-04-01

Applicant: Dae Jo Hong

Inventor： Dae Jo Hong

IPC: H01L21/44

CPC classification number: H05K3/243 ,  H01L21/6835 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K2201/0367 ,  H05K2203/0588 ,  H01L2224/13099

Abstract: Disclosed is a method for forming post bumps, the method including the steps of: forming a seed layer for metal plating on a substrate; forming a resist layer having openings provided as positions where the seed layer is subjected to metal plating; forming a dummy sheet, exposing the openings, on the resist layer; forming a post by performing metal plating of the openings; forming solder balls on the post; and removing the dummy sheet and the resist layer.

Abstract translation: 公开了一种用于形成凸块的方法，所述方法包括以下步骤：在基板上形成用于金属电镀的晶种层; 形成具有开口的抗蚀剂层，所述开口设置在种子层经受金属电镀的位置; 在所述抗蚀剂层上形成假片，露出所述开口; 通过对开口进行金属电镀形成柱; 在柱上形成焊球; 并且去除虚设片和抗蚀剂层。

公开(公告)号：US20110284158A1

公开(公告)日：2011-11-24

申请号：US13067223

申请日：2011-05-18

Applicant: Manabu Katsumura

Inventor： Manabu Katsumura

IPC: B32B38/14 ,  B05C5/02

CPC classification number: H05K3/4007 ,  H01L24/11 ,  H01L24/13 ,  H01L24/742 ,  H01L2224/05647 ,  H01L2224/11013 ,  H01L2224/11312 ,  H01L2224/11332 ,  H01L2224/11505 ,  H01L2224/11848 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K3/125 ,  H05K2201/0367 ,  H05K2203/0285 ,  H05K2203/1476 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method of manufacturing a functionally gradient material having a gradient from a first material to a second material different to the first material by ejecting inks onto a base material from a plurality of inkjet heads, includes the steps of: supplying a first functional ink containing the first material to a first inkjet head; supplying a second functional ink containing the second material to a second inkjet head; specifying a ratio between a volume of the first functional ink ejected from the first inkjet head and a volume of the second functional ink ejected from the second inkjet head; causing the first inkjet head to eject the first functional ink and/or causing the second inkjet head to eject the second functional ink, in accordance with the specified ratio, so as to form one layer; and stacking a plurality of layers onto the base material by repeating the forming step, so as to obtain a laminated body, wherein in the control step, the ratio between the first functional ink and the second functional ink is specified in such a manner that respective layers of the plurality of layers progressively have a smaller ratio of the first functional ink and a larger ratio of the second functional ink, toward an upper layer.

Abstract translation: 通过从多个喷墨头喷射墨到基材上，制造具有从第一材料到与第一材料不同的第二材料的梯度的功能梯度材料的方法包括以下步骤：将含有 第一材料到第一喷墨头; 将含有第二材料的第二功能油墨供应到第二喷墨头; 指定从第一喷墨头喷射的第一功能墨水的体积与从第二喷墨头喷射的第二功能墨水的体积之间的比率; 使第一喷墨头按照规定的比例排出第一功能油墨和/或使第二喷墨头喷射第二功能油墨，形成一层; 并且通过重复形成步骤将多个层层叠到基材上，从而获得层压体，其中在控制步骤中，以如下方式指定第一功能油墨和第二功能油墨之间的比例： 多个层的层逐渐地具有较小的第一功能油墨的比例和较大的第二功能油墨的比例朝向上层。

公开(公告)号：US20110260320A1

公开(公告)日：2011-10-27

申请号：US13155825

申请日：2011-06-08

Applicant: Yoichi Kubota ,  Teck-Gyu Kang ,  Jae M. Park ,  Belgacem Haba

Inventor： Yoichi Kubota ,  Teck-Gyu Kang ,  Jae M. Park ,  Belgacem Haba

IPC: H01L23/498

CPC classification number: H05K1/0366 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/49175 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/1532 ,  H05K3/06 ,  H05K3/4007 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2203/063 ,  H05K2203/0733 ,  Y10T29/49126 ,  Y10T29/49156 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A packaged microelectronic element includes connection component incorporating a dielectric layer (22) carrying traces (58) remote from an outer surface (26), posts (48) extending from the traces and projecting beyond the outer surface of the dielectric, and pads (30) exposed at the outer surface of the dielectric layer, the pads being connected to the posts by the traces. The dielectric element overlies the front surface of a microelectronic element, and contacts (74) exposed on the front surface of the microelectronic element are connected to the pads by elongated leads (76) such as wire bonds. Methods of making the connection component are also disclosed.

Abstract translation: 封装的微电子元件包括连接部件，其包括承载远离外表面（26）的迹线（58）的介电层（22），从该迹线延伸并突出超过电介质外表面的柱（48） ）暴露在介电层的外表面处，焊盘通过迹线连接到柱。 电介质元件覆盖在微电子元件的前表面上，暴露在微电子元件的前表面上的触点（74）通过诸如引线键的细长引线（76）连接到焊盘。 还公开了制造连接部件的方法。

公开(公告)号：US08045331B2

公开(公告)日：2011-10-25

申请号：US12188319

申请日：2008-08-08

Applicant: Ho-Seong Seo ,  Young-Min Lee ,  Kyu-Sub Kwak

Inventor： Ho-Seong Seo ,  Young-Min Lee ,  Kyu-Sub Kwak

IPC: H01L23/52 ,  H01L23/02 ,  H01L21/48

CPC classification number: H05K3/4092 ,  H05K1/11 ,  H05K3/326 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2201/09036 ,  H05K2203/308 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155

Abstract: A printed circuit board includes a core layer, an insulation layer formed on the core layer and having a cavity formed on a part of the insulation layer, and a circuit pattern formed on the insulation layer, wherein the circuit pattern comprises one or more external terminals positioned above the cavity.

Abstract translation: 印刷电路板包括芯层，形成在芯层上并具有形成在绝缘层的一部分上的空腔的绝缘层和形成在绝缘层上的电路图案，其中电路图案包括一个或多个外部端子 位于空腔上方。