公开(公告)号：US20110279544A1

公开(公告)日：2011-11-17

申请号：US13131392

申请日：2009-11-30

Applicant: Michael Dovrat ,  Ran Asher Peleg ,  Amir Hadar ,  Hanan Gothait

Inventor： Michael Dovrat ,  Ran Asher Peleg ,  Amir Hadar ,  Hanan Gothait

IPC: B41J2/145

CPC classification number: H01L21/288 ,  B41J2/155 ,  B41J3/543 ,  B41J25/001 ,  B41J2202/04 ,  B41J2202/21 ,  B41M1/22 ,  B41M5/0047 ,  C23C4/01 ,  H01L31/0504 ,  H05K3/125 ,  H05K2201/09236

Abstract: Embodiments of the invention are directed to a method of printing lines. A method may include positioning a plurality of print units according to a predefined spacing parameter. A method may include depositing material on a substrate by a plurality of print units to form a respective plurality of parallel lines according to a predefined spacing parameter. A printing unit may be positioned at an angle with respect to a predefined scan direction such that a predefined width of a printed line is achieved. A substrate may be rotated between scans such that a plurality of lines in a respective plurality of directions is printed in a scan direction.

Abstract translation: 本发明的实施例涉及一种打印线的方法。 一种方法可以包括根据预定义的间隔参数来定位多个打印单元。 一种方法可以包括通过多个打印单元在衬底上沉积材料以根据预定义的间隔参数形成相应的多条平行线。 打印单元可以相对于预定扫描方向成一角度定位，使得实现印刷线的预定宽度。 衬底可以在扫描之间旋转，使得在扫描方向上打印在相应多个方向上的多条线。

公开(公告)号：US08051558B2

公开(公告)日：2011-11-08

申请号：US12329584

申请日：2008-12-06

Applicant: Ting-Hao Lin ,  Chien-Wei Chang

Inventor： Ting-Hao Lin ,  Chien-Wei Chang

IPC: H05K3/02 ,  H05K3/10

CPC classification number: H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/108 ,  H05K3/205 ,  H05K2201/09236 ,  H05K2201/09881 ,  Y10T29/49002 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49155

Abstract: A manufacturing method for mainly embedding the passive device structure in the printed circuit board is presented. In this structure, both the source electrode and the ground electrode of the passive device belong to the same level, and includes several source branches and several ground branches that are formed vertically on the inside of the dielectric layer of the circuit board which are connected, respectively, to avoid the conducting between the source electrode and the ground electrode during lamination. When it is in the form of the capacitor structure, through the use of the ultra-fine wiring technique, these source branches and ground branches are separated by a small gap between each other. Therefore, the side face area and quantities of the source branches and ground branches are both increased.

Abstract translation: 提出了一种主要将无源器件结构嵌入印刷电路板的制造方法。 在该结构中，无源器件的源电极和接地电极都属于同一水平，并且包括垂直形成在电路板的电介质层的内部上的数个源极分支和几个接地分支， 以避免在层压期间源电极和接地电极之间的导电。 当它是电容器结构的形式时，通过使用超细布线技术，这些源极分支和接地分支之间彼此间有很小的间隙。 因此，源分支和接地分支的侧面积和数量都增加。

公开(公告)号：US08050043B2

公开(公告)日：2011-11-01

申请号：US11560763

申请日：2006-11-16

Applicant: Hyun-Jin Choi ,  Young-Chan Cho

Inventor： Hyun-Jin Choi ,  Young-Chan Cho

IPC: H05K7/00

CPC classification number: H05K7/1459 ,  G06F13/409 ,  G11C5/04 ,  G11C5/063 ,  H05K1/0296 ,  H05K2201/044 ,  H05K2201/09236

Abstract: Disclosed herein is a printed circuit board facilitating expansion of number of memory modules and memory system including the same. The printed circuit board of the present invention includes a plurality of slots and a plurality of controller terminals. Each of slots disposed in locations ranging from a 2n−1+1th location to a 2nth location with respect to the controller terminals includes 2k−n module terminals connected to the module terminals of slots ranging from the slot disposed in the first location to a slot disposed in a 2n−1th location; wherein, in the printed circuit board and memory system including the printed circuit board according to the present invention, dummy modules are not required to expand the number of memory modules. Further, according to the printed circuit board of the present invention, the expansion of the number of memory modules is facilitated.

Abstract translation: 这里公开了一种便于扩展存储器模块数量和包括其的存储器系统的印刷电路板。 本发明的印刷电路板包括多个槽和多个控制器端子。 设置在相对于控制器端子的从2n-1 + 1位置到第2n位置的位置中的每个槽包括连接到从设置在第一位置的槽到槽的槽的模块端子的2k-n模块端子 放置在第2n位; 其中，在包括根据本发明的印刷电路板的印刷电路板和存储器系统中，不需要虚拟模块来扩展存储器模块的数量。 此外，根据本发明的印刷电路板，容易扩大存储器模块的数量。

公开(公告)号：US08044303B2

公开(公告)日：2011-10-25

申请号：US12098661

申请日：2008-04-07

Applicant: Yu-Huan Qiu ,  Wen-Kang Fan

Inventor： Yu-Huan Qiu ,  Wen-Kang Fan

IPC: H05K1/03

CPC classification number: H05K3/222 ,  H05K1/0237 ,  H05K3/0005 ,  H05K2201/09236 ,  H05K2201/10265

Abstract: A trace carrier is provided. The trace carrier includes a first insulating tube, a second insulating tube, a trace pair, and a sealed hollow insulating cylinder. The trace pair is passing through the first insulating tube and the second insulating tube, and is coiled up in an inner space of the first insulating tube and the second insulating tube. The sealed hollow insulating cylinder encapsulates the first insulating tube, the second insulating tube, and the trace pair, but the four terminals of the trace pair are exposed to the outside of the sealed hollow insulating cylinder.

Abstract translation: 提供轨迹载体。 迹线载体包括第一绝缘管，第二绝缘管，迹线对和密封中空绝缘筒。 轨迹对通过第一绝缘管和第二绝缘管，并且被卷绕在第一绝缘管和第二绝缘管的内部空间中。 密封的中空绝缘圆柱体封装第一绝缘管，第二绝缘管和迹线对，但是迹线对的四个端子暴露于密封的中空绝缘筒的外部。

公开(公告)号：US08023278B2

公开(公告)日：2011-09-20

申请号：US12120304

申请日：2008-05-14

Applicant: Ching-Jen Wang

Inventor： Ching-Jen Wang

IPC: H05K7/00 ,  H05K1/18 ,  H05K1/03 ,  H05K1/11

CPC classification number: H05K1/0256 ,  H05K1/0237 ,  H05K1/0266 ,  H05K1/181 ,  H05K3/28 ,  H05K2201/09236 ,  H05K2201/09936

Abstract: A circuit board includes a plurality of conductive layers, a plurality of insulating layers, a telecommunication network connection port and a modem card processing module. A high voltage signal line is laid out at one of the conductive layers. The insulating layers are disposed between each of the conducting layers, respectively. The telecommunication network connection port is disposed on the conductive layers and is electrically connected to one end of the high voltage signal line. The modem card processing module is disposed on the conductive layers and is electrically connected to the other end of the high voltage signal line.

Abstract translation: 电路板包括多个导电层，多个绝缘层，电信网络连接端口和调制解调器卡处理模块。 高电压信号线布置在导电层之一处。 绝缘层分别设置在每个导电层之间。 电信网络连接端口设置在导电层上并与高压信号线的一端电连接。 调制解调器卡处理模块设置在导电层上并与高电压信号线的另一端电连接。

公开(公告)号：US20110222255A1

公开(公告)日：2011-09-15

申请号：US13040915

申请日：2011-03-04

Applicant: Naofumi KITANO ,  Toshiro NISHIMURA

Inventor： Naofumi KITANO ,  Toshiro NISHIMURA

IPC: H05K7/02

CPC classification number: H05K1/0231 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16225 ,  H05K1/0251 ,  H05K1/113 ,  H05K1/165 ,  H05K3/4614 ,  H05K2201/09236 ,  H05K2201/09636 ,  H05K2201/10545 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611

Abstract: An electronic circuit is obtained that has reduced EMI levels. The circuit includes an integrated circuit, which is a source of noise, a bypass capacitor, and a circuit substrate on which they are mounted. An electronic circuit one electrode terminal of the bypass capacitor and one connecting electrode of the integrated circuit are connected through a first wire interconnect formed in the circuit substrate, and, additionally, another electrode terminal of the bypass capacitor and another connecting electrode of the integrated circuit are connected through a second wire interconnect, and the gap between the first wire interconnect and the second wire interconnect is made smaller than either the gap between the one connecting electrode and the other connecting electrode on the integrated circuit or the gap between the one electrode terminal and the other electrode terminal of the bypass capacitor.

Abstract translation: 获得具有降低的EMI电平的电子电路。 电路包括作为噪声源的集成电路，旁路电容器和安装在其上的电路基板。 旁路电容器的一个电极端子和集成电路的一个连接电极的电子电路通过形成在电路基板中的第一线路互连而连接，另外，旁路电容器的另一个电极端子和集成电路的另一个连接电极 通过第二导线互连连接，并且使第一线互连和第二线互连之间的间隙小于集成电路上的一个连接电极和另一个连接电极之间的间隙或者一个电极端子之间的间隙 旁路电容器的另一个电极端子。

公开(公告)号：US08013427B2

公开(公告)日：2011-09-06

申请号：US12548371

申请日：2009-08-26

Applicant: Maraki Maetani

Inventor： Maraki Maetani

IPC: H01L23/58 ,  H05K1/11

CPC classification number: H05K1/0245 ,  H01L2924/0002 ,  H05K1/0251 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/09636 ,  H05K2201/09672 ,  H01L2924/00

Abstract: A wiring board equipped with differential lines which compensate for differences in via lengths to minimize signal deterioration is disclosed. Two conductors are couple to different substrate levels through vias of different lengths. Compensation means are provided to correct for the phase difference caused by the different lengths.

Abstract translation: 公开了配备有差分线路的布线板，其补偿通路长度的差异以最小化信号劣化。 两个导体通过不同长度的通孔耦合到不同的衬底层。 提供补偿装置来校正由不同长度引起的相位差。

公开(公告)号：US08013255B2

公开(公告)日：2011-09-06

申请号：US12126748

申请日：2008-05-23

Applicant: Shou-Kuo Hsu ,  Chun-Jen Chen

Inventor： Shou-Kuo Hsu ,  Chun-Jen Chen

IPC: H05K1/03

CPC classification number: H05K1/0245 ,  H05K1/0298 ,  H05K2201/09236 ,  H05K2201/09336

Abstract: An exemplary PCB includes a first reference layer, a first signal layer, and a second signal layer in that order. A first differential pair is arranged in the first signal layer in an edge-coupled structure referencing the first reference layer. A second differential pair is arranged in the second signal layer in edge-coupled structure. A first ground part and a second ground part are symmetrically arranged in the second signal layer and at opposite sides of the second differential pair. The first differential pair is arranged above the first ground part such that a projection of the first differential pair onto the second signal layer having an area coincident with the first ground part. The second differential pair references the first and second ground parts.

Abstract translation: 示例性的PCB包括第一参考层，第一信号层和第二信号层。 第一差分对以参考第一参考层的边缘耦合结构布置在第一信号层中。 第二差分对以边缘耦合结构布置在第二信号层中。 第一接地部分和第二接地部分对称地布置在第二信号层中并且在第二差分对的相对侧。 第一差分对被布置在第一接地部分上方，使得第一差分对的突起与第一接地部分重合的区域的第二信号层上。 第二差分对参考第一和第二接地部分。

公开(公告)号：US08004812B2

公开(公告)日：2011-08-23

申请号：US12795625

申请日：2010-06-07

Applicant: Anthony A. Anthony ,  William M. Anthony

Inventor： Anthony A. Anthony ,  William M. Anthony

IPC: H02H9/00

CPC classification number: H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/552 ,  H01L23/66 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/023 ,  H05K1/0237 ,  H05K2201/09236 ,  H05K2201/10378 ,  Y10T29/49124 ,  Y10T29/4913 ,  Y10T29/49204 ,  H01L2924/00 ,  H01L2224/05599

Abstract: The present invention relates to an interposer substrate for interconnecting between active electronic componentry such as but not limited to a single or multiple integrated circuit chips in either a single or a combination and elements that could comprise of a mounting substrate, substrate module, a printed circuit board, integrated circuit chips or other substrates containing conductive energy pathways that service an energy utilizing load and leading to and from an energy source. The interposer will also possess a multi-layer, universal multi-functional, common conductive shield structure with conductive pathways for energy and EMI conditioning and protection that also comprise a commonly shared and centrally positioned conductive pathway or electrode of the structure that can simultaneously shield and allow smooth energy interaction between grouped and energized conductive pathway electrodes containing a circuit architecture for energy conditioning as it relates to integrated circuit device packaging. The invention can be employed between an active electronic component and a multilayer circuit card. A method for making the interposer is not presented and can be varied to the individual or proprietary construction methodologies that exist or will be developed.

Abstract translation: 本发明涉及用于将有源电子元件（例如但不限于单个或多个）单个或多个集成电路芯片互连的插入器基板，以及可以包括安装基板，基板模块，印刷电路 板，集成电路芯片或其他包含导电能量路径的基板，其能够利用负载和通向能量源的能量。 插入器还将具有多层通用多功能通用导电屏蔽结构，其具有用于能量和EMI调节和保护的导电路径，其还包括可共同屏蔽的结构的共同共享和中心定位的导电路径或电极， 允许包含用于能量调节的电路架构的组合和通电的导电路径电极之间的平滑的能量相互作用，因为它涉及集成电路器件封装。 本发明可以用于有源电子部件和多层电路卡之间。 不提供制作插入器的方法，并且可以根据现有或将要开发的个人或专有的施工方法来改变。

公开(公告)号：US07986020B2

公开(公告)日：2011-07-26

申请号：US12423612

申请日：2009-04-14

Applicant: Osamu Kagaya

Inventor： Osamu Kagaya

IPC: H01L31/0232

CPC classification number: H05K1/0245 ,  H05K1/0224 ,  H05K1/0234 ,  H05K1/025 ,  H05K1/0253 ,  H05K1/0393 ,  H05K1/147 ,  H05K1/167 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/0969 ,  H05K2201/09727 ,  H05K2201/10121

Abstract: A flexible printed circuit board includes: a signal wiring pattern including: a transmission line for connecting an end of an optical device with an end of a signal generation circuit; and another transmission line for connecting another end of the optical device with another end of the signal generation circuit; a thin film resistor layer formed in a region including a region facing the signal wiring pattern so as to constitute a first microstrip line together with each of the transmission lines; a ground conductor formed in a region except a part of a region facing the thin film resistor layer within a region including a region facing the signal wiring pattern so as to constitute a second microstrip line together with each of the transmission lines; and an insulating layer formed between each two of the signal wiring pattern, the thin film resistor layer, and the ground conductor.

Abstract translation: 柔性印刷电路板包括：信号布线图案，包括：用于将光学装置的端部与信号发生电路的端部连接的传输线; 以及用于将所述光学装置的另一端与所述信号发生电路的另一端连接的另一传输线; 形成在包括面向信号布线图案的区域的区域中的薄膜电阻层，以与每个传输线一起构成第一微带线; 形成在除面向薄膜电阻层的区域以外的区域内的区域内的接地导体，所述区域包括面向信号布线图案的区域，以与每条传输线一起构成第二微带线; 以及形成在每个信号布线图案，薄膜电阻层和接地导体之间的绝缘层。