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    Packaging substrate with electrostatic discharge protection
    71.
    发明申请
    Packaging substrate with electrostatic discharge protection 有权
    包装基板采用静电放电保护

    公开(公告)号：US20020185305A1

    公开(公告)日：2002-12-12

    申请号：US10164356

    申请日：2002-06-06

    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

    Inventor： Juang-Sheng Chiang

    IPC: H05K001/09 ,  H01L023/58

    CPC classification number: H05K1/0259 ,  H01L23/60 ,  H01L2924/0002 ,  H05K3/0052 ,  H05K3/284 ,  H05K2201/09354 ,  H05K2201/09681 ,  H01L2924/00

    Abstract: The present invention relates to a packaging substrate with electrostatic discharge protection. Each of the mold gates on the substrate is electrically connected to the first copper-mesh layer on the periphery of a top side of the substrate. When static electricity is generated during the molding process, static electric charges will be conducted from the mold gate to the first copper-mesh layer. The static electric charges are collected and restricted to a capacitor formed by a first copper-mesh layer, a dielectric layer and a second copper-mesh layer, and are discharged via a metal pad and supporter. On the other hand, the static electric charge is conducted via the first copper-mesh layer, a through hole, the second copper-mesh layer, the metal pad to the supporter. Therefore, basing on capacitor effects or conductive effects, the static electricity generated during the molding process can be safely conducted away from the substrate, preventing the dies to be packaged from damage due to electrostatic discharge so as to raise the yield rate of semiconductor package products.

    Abstract translation: 本发明涉及具有静电放电保护的封装基板。 基板上的每个模具浇口与衬底顶侧周边的第一铜网层电连接。 当在成型过程中产生静电时，静电荷将从模具门到第一铜网层进行。 静电收集并限制在由第一铜网层，电介质层和第二铜网层形成的电容器上，并通过金属垫和支撑体排出。 另一方面，静电荷通过第一铜网层，通孔，第二铜网层，金属垫到支撑体进行。 因此，基于电容器效应或导电效应，可以将成型过程中产生的静电安全地从基板导出，防止由于静电放电而使芯片受到损坏，从而提高半导体封装产品的成品率 。

    Power semiconductor module of high isolation strength
    72.
    发明授权
    Power semiconductor module of high isolation strength 有权
    功率半导体模块隔离强度高

    公开(公告)号：US06469378B2

    公开(公告)日：2002-10-22

    申请号：US10027802

    申请日：2001-12-20

    Applicant: Uwe Scheuermann

    Inventor： Uwe Scheuermann

    IPC: H01L2352

    CPC classification number: H05K1/0256 ,  C04B2237/407 ,  H01L23/15 ,  H01L23/3735 ,  H01L23/5383 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K2201/0355 ,  H05K2201/09145 ,  H05K2201/09354 ,  H01L2924/00

    Abstract: A power semiconductor module achieves high isolation strength from a base through selectively positioning a plurality of metal coatings on first and second surfaces and positioning edges of the plurality to beneficially reduce the field strength tangentially to a selected position, especially in a defined critical region directly adjacent a metal coating edge on a first surface opposite the base. This design results in regions which beneficially allow field lines to extend without functional detriment. The beneficial position selection is is achieved by means of an optimization process in which the tangential components of the field strength beside the first or second metallization edge reach identical values.

    Abstract translation: 功率半导体模块通过在第一和第二表面上选择性地定位多个金属涂层并且将多个金属涂层的定位边缘有选择地有选择地降低到选定位置的切向强度，特别是在直接相邻的限定的临界区域 在与基座相对的第一表面上的金属涂层边缘。 这种设计导致有利地允许场线延伸而没有功能损害的区域。 有利的位置选择通过优化过程来实现，其中在第一或第二金属化边缘旁边的场强的切向分量达到相同的值。

    Embedded waveguide and embedded electromagnetic shielding
    73.
    发明申请
    Embedded waveguide and embedded electromagnetic shielding 审中-公开
    嵌入式波导和嵌入式电磁屏蔽

    公开(公告)号：US20020130739A1

    公开(公告)日：2002-09-19

    申请号：US10046323

    申请日：2002-01-14

    Inventor： Martin A. Cotton

    IPC: H01P003/08

    CPC classification number: H05K1/0218 ,  H01L23/552 ,  H01L2223/6622 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15192 ,  H05K1/0221 ,  H05K1/115 ,  H05K3/0035 ,  H05K3/0041 ,  H05K3/4652 ,  H05K2201/09036 ,  H05K2201/09354 ,  H05K2201/09509 ,  H05K2201/09854 ,  H05K2201/09981 ,  H01L2224/0401

    Abstract: Construction of printed circuit boards (PCBs) containing electromagnetic shielding and conductive tubes forming signal lines and/or waveguides. The method of construction calls for forming of grooves through layers of the PCB and coating the interior surfaces of these grooves with conductive material. These conductor-coated groove walls serve as conductive surfaces between embedded conductive surfaces on different layers. The conductive surfaces thus joined form a continuous electrically conductive surface that can be configured to act as an electromagnetic shield. Such conductive surfaces may be configured with internal conductors to act as a signal line, or without internal conductors to act as a waveguide.

    Abstract translation: 构造包含电磁屏蔽和形成信号线和/或波导的导电管的印刷电路板（PCB）。 施工方法要求通过PCB的层形成凹槽，并用导电材料涂覆这些凹槽的内表面。 这些导体涂覆的槽壁用作不同层上的嵌入的导电表面之间的导电表面。 这样连接的导电表面形成连续的导电表面，该表面可配置为充当电磁屏蔽。 这样的导电表面可以配置有内部导体以用作信号线，或者不具有用作波导的内部导体。

    Electrical connector
    76.
    发明授权
    Electrical connector 失效
    电连接器

    公开(公告)号：US5679008A

    公开(公告)日：1997-10-21

    申请号：US570386

    申请日：1995-12-11

    Applicant: Hisafumi Takahashi ,  Kouichi Uchiyama

    Inventor： Hisafumi Takahashi ,  Kouichi Uchiyama

    IPC: H01R9/05 ,  H01R13/512 ,  H05K1/11 ,  H05K1/14 ,  H01R9/09

    CPC classification number: H01R9/0515 ,  H01R13/512 ,  H05K1/117 ,  H01R12/598 ,  H05K1/144 ,  H05K2201/0379 ,  H05K2201/0715 ,  H05K2201/09354 ,  H05K2201/10356

    Abstract: An electrical connector 1 comprises a mediate circuit board assembly 4, a housing 2, and a plurality of contacts 3. The mediate circuit board assembly 4 has a plurality of signal paths, to which signal cables 5 are connected, and the housing 2 houses this mediate circuit board assembly 4. The contacts 3 are retained in the housing 2 and connected to the signal paths of the mediate circuit board assembly 4, which is housed in the housing 2. Two double-sided circuit boards, each having at least the signal paths formed on the front face and a grounding path formed on the rear face, constitute the mediate circuit board assembly 4 when these two double-sided circuit boards are abutted with each other, connecting the grounding paths of their rear faces.

    Abstract translation: 电连接器1包括中介电路板组件4，壳体2和多个触点3.中间电路板组件4具有多个信号路径，信号电缆5连接到该多个信号路径，并且壳体2容纳该 介质电路板组件4.触点3保持在壳体2中并连接到容纳在壳体2中的中介电路板组件4的信号路径。两个双面电路板，每个至少具有信号 形成在前表面上的路径和形成在后表面上的接地路径构成了当这两个双面电路板彼此抵接时​​连接其后表面的接地路径的中间电路板组件4。

    ESD bypass and EMI shielding trace design in burn-in board
    77.
    发明授权
    ESD bypass and EMI shielding trace design in burn-in board 失效
    老化板中的ESD旁路和EMI屏蔽跟踪设计

    公开(公告)号：US5659245A

    公开(公告)日：1997-08-19

    申请号：US658524

    申请日：1996-06-03

    Applicant: King-Ho Ping ,  Jian-Hsing Lee

    Inventor： King-Ho Ping ,  Jian-Hsing Lee

    IPC: G01R1/18 ,  G01R31/28 ,  H05K1/02 ,  H05K3/00 ,  H05K9/00 ,  G01R31/02

    CPC classification number: G01R31/2863 ,  G01R1/18 ,  H05K1/0218 ,  H05K1/0259 ,  H05K9/0067 ,  H05K1/0215 ,  H05K2201/09354 ,  H05K2201/10189 ,  H05K2201/10689 ,  H05K3/0061

    Abstract: A burn-in board assembly for the protection of integrated circuit modules from Electrostatic discharge and the shielding of said integrated circuit modules from Electromagnetic Interference during said electrostatic discharge is described. The burn-in board assembly has a printed circuit board onto which the integrated circuits are mounted by soldering or plugging into sockets soldered to said burnin board assembly. Disposed upon the printed circuit board is a plurality of input stimuli, feedback sensing, and output response signal traces to connect the integrated circuit modules to a connector that is coupled to a input stimulus generator and feedback sensing and output response monitor. Also disposed upon the printed circuit board is a plurality of ground traces and voltage supply traces to connect the integrated circuit modules to the connector that is coupled to a voltage supply source and the system ground reference point. An electrostatic discharge bypass track is disposed peripherally upon the printed circuit board and is connected to the ground reference point through the connector to prevent damage to the printed circuit modules during an electrostatic discharge event. A first and a second electromagnetic interference shielding trace is disposed upon the printed circuit board. Each electromagnetic shielding trace is connected at opposite ends to the ground reference point through the connector to shield the printed circuit traces from the effects of the electromagnetic interference.

    Abstract translation: 描述了一种用于在静电放电期间保护集成电路模块免受静电放电和屏蔽所述集成电路模块与电磁干扰的老化板组件。 老化板组件具有印刷电路板，集成电路通过焊接或插入到焊接到所述燃烧板组件的插座中而安装在该印刷电路板上。 布置在印刷电路板上的是多个输入刺激，反馈感测和输出响应信号迹线，以将集成电路模块连接到耦合到输入激励发生器和反馈感测和输出响应监视器的连接器。 还布置在印刷电路板上的是多个接地迹线和电压提供迹线，用于将集成电路模块连接到耦合到电压源和系统接地参考点的连接器。 静电放电旁路轨道周边布置在印刷电路板上，并通过连接器连接到接地参考点，以防止在静电放电事件期间损坏印刷电路模块。 第一和第二电磁干扰屏蔽迹线设置在印刷电路板上。 每个电磁屏蔽迹线通过连接器在相对端连接到接地参考点，以屏蔽印刷电路迹线免受电磁干扰的影响。

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