公开(公告)号：US08294529B2

公开(公告)日：2012-10-23

申请号：US12361781

申请日：2009-01-29

Applicant: Heung-Kyu Kim

Inventor： Heung-Kyu Kim

IPC: H01P3/08

CPC classification number: H01P3/081 ,  H01P11/003 ,  H05K1/0221 ,  H05K3/205 ,  H05K2201/0376 ,  H05K2201/0715 ,  H05K2201/09509 ,  H05K2201/09827

Abstract: A printed circuit board having a micro strip line, a printed circuit board having a strip line and a method of manufacturing thereof are disclosed. The printed circuit board having a micro strip line in accordance with an embodiment of the present invention includes a first insulation layer, a signal line buried in one surface of the first insulation layer, a plurality of conductors penetrating through the first insulation layer and being disposed on both sides of the signal line in parallel with the signal line, and a ground layer formed to be electrically connected to the conductor on the other surface of the first insulation layer.

Abstract translation: 公开了一种具有微带线的印刷电路板，具有带状线的印刷电路板及其制造方法。 根据本发明实施例的具有微带线的印刷电路板包括第一绝缘层，埋在第一绝缘层的一个表面中的信号线，穿过第一绝缘层并被布置的多个导体 在与信号线并联的信号线的两侧，以及形成为与第一绝缘层的另一个表面上的导体电连接的接地层。

公开(公告)号：US08294036B2

公开(公告)日：2012-10-23

申请号：US12410699

申请日：2009-03-25

Applicant: Shinichiro Kakei ,  Kenji Horino ,  Hitoshi Saita ,  Yasunobu Oikawa

Inventor： Shinichiro Kakei ,  Kenji Horino ,  Hitoshi Saita ,  Yasunobu Oikawa

IPC: H05K1/16 ,  H05K1/18

CPC classification number: H05K1/162 ,  H05K3/382 ,  H05K2201/0175 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2203/033

Abstract: In a dielectric element, the side faces are roughened so that the surface roughness Ra is 15 nm or greater. By this means, the area of contact between a glass epoxy resin substrate and insulating material is increased, adhesion with resin substrates is improved, and strength and reliability can be enhanced when buried between two resin substrates. In the dielectric element, the surface roughness Ra of side surfaces is 5000 nm or less, so that when burying the dielectric element between a glass epoxy resin substrate and insulating material, the occurrence of air bubbles between the surface of the dielectric element and the resin can be prevented.

Abstract translation: 在电介质元件中，侧面粗糙化，使得表面粗糙度Ra为15nm以上。 通过这种方式，玻璃环氧树脂基板和绝缘材料之间的接触面积增加，与树脂基板的粘合性提高，并且当埋在两个树脂基板之间时可以提高强度和可靠性。 在电介质元件中，侧面的表面粗糙度Ra为5000nm以下，因此当在玻璃环氧树脂基板和绝缘材料之间埋入电介质元件时，介电元件表面与树脂之间产生气泡 可以防止。

公开(公告)号：US08258620B2

公开(公告)日：2012-09-04

申请号：US12673409

申请日：2008-08-08

Applicant: Mayumi Nakasato ,  Ryosuke Usui ,  Kiyoshi Shibata

Inventor： Mayumi Nakasato ,  Ryosuke Usui ,  Kiyoshi Shibata

IPC: H01L23/053 ,  H01L23/12

CPC classification number: H01L23/145 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L29/0657 ,  H01L2221/68345 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/0508 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81136 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83104 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H05K1/0366 ,  H05K1/0373 ,  H05K1/113 ,  H05K3/002 ,  H05K3/305 ,  H05K3/4007 ,  H05K2201/0209 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/1152 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/3512 ,  H01L2224/05599

Abstract: A circuit device includes an insulating base provided with a resin layer mixed with a fibrous filler, bumps provided in the insulating base and functioning as electrodes for connection, a semiconductor device that is flip-chip mounted, and an underfill filling a gap between the semiconductor device and the insulating base. By allowing the fibrous filler projecting through the top surface of the resin layer to be in contact with the underfill, strength of adhesion between the underfill and the insulating base is improved.

Abstract translation: 电路装置包括：绝缘基体，设置有与纤维填料混合的树脂层，设置在绝缘基底中的凸起，用作连接用电极，倒装芯片安装的半导体器件，以及填充半导体之间的间隙的底部填充物 设备和绝缘基座。 通过使通过树脂层的上表面突出的纤维状填料与底部填充剂接触，提高了底部填充剂和绝缘基材之间的粘合强度。

公开(公告)号：US08236619B2

公开(公告)日：2012-08-07

申请号：US13092913

申请日：2011-04-23

Applicant: Charles W. C. Lin ,  Chia-Chung Wang

Inventor： Charles W. C. Lin ,  Chia-Chung Wang

IPC: H01L21/00

CPC classification number: H01L21/486 ,  H01L23/3677 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L33/483 ,  H01L33/642 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/32188 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83855 ,  H01L2224/85207 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/0132 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12041 ,  H01L2924/15174 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/351 ,  H05K1/0204 ,  H05K1/115 ,  H05K3/0061 ,  H05K3/06 ,  H05K2201/09054 ,  H05K2201/09509 ,  H05K2201/10106 ,  H05K2203/0369 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01007 ,  H01L2924/01015 ,  H01L2924/01026 ,  H01L2924/00012

Abstract: A method of making a semiconductor chip assembly includes providing a post and a base, mounting a second adhesive on the base, mounting a substrate with a conductive pattern on the second adhesive, mounting a first adhesive on the substrate and mounting a conductive layer on the first adhesive, then flowing the first adhesive upward between the post and the conductive layer and flowing the second adhesive upward between the post and the substrate, solidifying the adhesives, then providing a conductive trace that includes a pad, a terminal, the conductive pattern, first and second vias and a selected portion of the conductive layer, mounting a semiconductor device on the post, wherein a heat spreader includes the post and the base, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.

Abstract translation: 一种制造半导体芯片组件的方法包括提供柱和基座，将第二粘合剂安装在基座上，将具有导电图案的基板安装在第二粘合剂上，将第一粘合剂安装在基板上并将导电层安装在 第一粘合剂，然后使第一粘合剂在柱和导电层之间向上流动并使第二粘合剂在柱和基底之间向上流动，固化粘合剂，然后提供包括垫，端子，导电图案的导电迹线， 第一和第二通孔和导电层的选定部分，将半导体器件安装在柱上，其中散热器包括柱和基座，将半导体器件电连接到导电迹线并将半导体器件热连接到热 吊具

公开(公告)号：US20120174805A1

公开(公告)日：2012-07-12

申请号：US13383978

申请日：2010-07-13

Applicant: Wen Te Chen ,  Yueh Ching Chen ,  Chen Chen

Inventor： Wen Te Chen ,  Yueh Ching Chen ,  Chen Chen

IPC: B41L13/14

CPC classification number: H05K3/0094 ,  H05K3/0008 ,  H05K3/1216 ,  H05K2201/09063 ,  H05K2201/09509

Abstract: The present application discloses a method for performing a hole-plugging process on a circuit board. The method comprises: forming at least two locating holes on the circuit board; delivering the circuit board to a locating area of a hole-plugging screen printer, and adjusting a moving path of the circuit board in the locating area according to a locating device of the hole-plugging screen printer and the locating holes; and transporting the circuit board to a screen printing area of the hole plugging screen printer automatically according to the moving path, and adjusting a hole-plugging stencil of the hole-plugging screen printer to align an inking point of the hole-plugging stencil with a hole to be plugged on the circuit board, so as to plug ink dropped from the inking point of the hole-plugging stencil into the hole. The present application discloses a system for executing above method.

Abstract translation: 本申请公开了一种在电路板上进行空穴堵塞处理的方法。 该方法包括：在电路板上形成至少两个定位孔; 将电路板输送到孔塞式丝网印刷机的定位区域，根据孔堵丝网印刷机的定位装置和定位孔调整定位区域中电路板的移动路径; 以及根据移动路径自动将电路板传送到孔堵丝网印刷机的丝网印刷区域，以及调整孔封丝网印刷机的孔塞模板以将孔塞模板的着色点与 要插入电路板上的孔，以将从插孔模板的着墨点滴落的墨水插入孔中。 本申请公开了一种用于执行上述方法的系统。

公开(公告)号：US20120162857A1

公开(公告)日：2012-06-28

申请号：US13409424

申请日：2012-03-01

Applicant: John D. Prymak ,  Chris Stolarski ,  Alethla Melody ,  Antony P. Chacko ,  Gregory J. Dunn

Inventor： John D. Prymak ,  Chris Stolarski ,  Alethla Melody ,  Antony P. Chacko ,  Gregory J. Dunn

IPC: H01G4/06 ,  H01G9/00 ,  H01B7/02

CPC classification number: H05K1/162 ,  H01G9/012 ,  H01G9/042 ,  H01G9/045 ,  H01G9/15 ,  H05K3/429 ,  H05K2201/0329 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2201/09909 ,  H05K2203/0315 ,  Y10T29/417 ,  Y10T29/435

Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.

公开(公告)号：US20120140423A1

公开(公告)日：2012-06-07

申请号：US12958293

申请日：2010-12-01

Applicant: Joseph Fisher, JR. ,  Sean Mayo ,  Dennis R. Pyper ,  Paul Nangeroni ,  Jose Mantovani

Inventor： Joseph Fisher, JR. ,  Sean Mayo ,  Dennis R. Pyper ,  Paul Nangeroni ,  Jose Mantovani

IPC: H05K7/00

CPC classification number: H05K9/0084 ,  H01L23/552 ,  H01L2224/16225 ,  H01L2924/12044 ,  H01L2924/15192 ,  H05K3/284 ,  H05K9/0092 ,  H05K2201/0715 ,  H05K2201/09509 ,  H01L2924/00

Abstract: Electrical components such as integrated circuits may be mounted on a printed circuit board. To prevent the electrical components from being subjected to electromagnetic interference, radio-frequency shielding structures may be formed over the components. The radio-frequency shielding structures may be formed from a layer of metallic paint. Components may be covered by a layer of dielectric. Channels may be formed in the dielectric between blocks of circuitry. The metallic paint may be used to coat the surfaces of the dielectric and to fill the channels. Openings may be formed in the surface of the metallic paint to separate radio-frequency shields from each other. Conductive traces on the surface of the printed circuit board may be used in connecting the metallic paint layer to internal printed circuit board traces.

Abstract translation: 诸如集成电路的电气部件可以安装在印刷电路板上。 为了防止电气部件受到电磁干扰，可以在部件上形成射频屏蔽结构。 射频屏蔽结构可以由一层金属涂料形成。 组件可以被一层电介质覆盖。 可以在电路块之间的电介质中形成通道。 金属涂料可用于涂覆电介质的表面并填充通道。 可以在金属涂料的表面中形成开口以将射频屏蔽彼此分开。 印刷电路板表面上的导电迹线可用于将金属漆层连接到内部印刷电路板迹线。

公开(公告)号：US08178789B2

公开(公告)日：2012-05-15

申请号：US12146279

申请日：2008-06-25

Applicant: Michimasa Takahashi ,  Masakazu Aoyama

Inventor： Michimasa Takahashi ,  Masakazu Aoyama

IPC: H05K1/11 ,  H05K7/02

CPC classification number: H05K3/4691 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/00014 ,  H05K1/0366 ,  H05K1/148 ,  H05K3/0052 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/0209 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A wiring board assembly and a method of making a wiring board assembly. The wiring board assembly includes a first wiring board having a first substrate, a non-pliable second substrate having a smaller mounting area than a mounting area of the first substrate and a base substrate laminated between the first substrate and the second substrate such that the first substrate extends beyond an edge of the second substrate. At least one via formed in at least one of the first substrate or the second substrate. A second wiring board includes a pliable member connecting the first wiring board to the second wiring board.

Abstract translation: 一种接线板组件及其制造方法。 布线基板组件包括：第一布线板，具有第一基板，非柔性第二基板，其安装面积小于第一基板的安装面积;以及基板基板，层压在第一基板和第二基板之间， 衬底延伸超过第二衬底的边缘。 至少一个通孔形成在第一基板或第二基板中的至少一个中。 第二布线板包括将第一布线板连接到第二布线板的柔性构件。

公开(公告)号：US20120115263A1

公开(公告)日：2012-05-10

申请号：US13353014

申请日：2012-01-18

Applicant: Makoto MATSUDA

Inventor： Makoto MATSUDA

IPC: H01L33/48

CPC classification number: H01L33/486 ,  H01L33/62 ,  H01L33/647 ,  H01L2224/45144 ,  H01L2224/48091 ,  H05K1/0203 ,  H05K1/183 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/10106 ,  H05K2203/049 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An embodiment of the present invention has an insulating substrate in which a first concave hole for mounting an LED chip and a second concave hole for connecting a metallic small-gauge wire are formed, where a metallic sheet that serves as a first wiring pattern is formed at a portion that includes the first concave hole, a metallic sheet that serves as a second wiring pattern is formed at a portion that includes the second concave hole, an LED chip is mounted upon the metallic sheet inside the first concave hole, the LED chip is electrically connected to the metallic sheet inside the second concave hole via a metallic small-gauge wire, and the chip-type LED is sealed with a clear resin.

Abstract translation: 本发明的实施例具有绝缘基板，其中形成用于安装LED芯片的第一凹孔和用于连接金属小规格金属丝的第二凹孔，其中形成用作第一布线图案的金属片 在包括第一凹孔的部分，在包括第二凹孔的部分处形成用作第二布线图案的金属片，将LED芯片安装在第一凹孔内的金属片上，LED芯片 通过金属小规格导线与第二凹孔内的金属片电连接，芯片型LED用透明树脂密封。

公开(公告)号：US20120111607A1

公开(公告)日：2012-05-10

申请号：US13354438

申请日：2012-01-20

Applicant: Shuhichi OKABE ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

Inventor： Shuhichi OKABE ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

IPC: H05K1/02

CPC classification number: H05K1/0265 ,  H05K1/116 ,  H05K3/107 ,  H05K3/108 ,  H05K3/205 ,  H05K3/421 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2203/0361

Abstract: A circuit board including: an insulator having a trench; a first circuit pattern formed to bury a portion of the trench; and a second circuit pattern formed on a surface of the insulator having the trench formed therein.

Abstract translation: 一种电路板，包括：具有沟槽的绝缘体; 形成为埋入沟槽的一部分的第一电路图案; 以及形成在其中形成有沟槽的绝缘体的表面上的第二电路图案。