公开(公告)号：US20070149057A1

公开(公告)日：2007-06-28

申请号：US11522530

申请日：2006-09-18

Applicant: Thomas Cohen ,  Marc Cartier ,  Mark Gailus

Inventor： Thomas Cohen ,  Marc Cartier ,  Mark Gailus

IPC: H01R13/648

CPC classification number: H05K7/1445 ,  H01R13/514 ,  H01R13/6587 ,  H01R13/6591 ,  H05K1/0231 ,  H05K1/0237 ,  H05K1/116 ,  H05K1/14 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09718 ,  H05K2201/10189 ,  H05K2203/1572

Abstract: A midplane has a first side to which contact ends of a first differential connector are connected and a second side opposite the first side to which contact ends of a second differential connector are connected. The midplane includes a plurality of vias extending from the first side to the second side, with the vias providing first signal launches on the first side and second signal launches on the second side. The first signal launches are provided in a plurality of rows, with each row having first signal launches along a first line and first signal launches along a second line substantially parallel to the first line. The second signal launches are provided in a plurality of columns, with each column having second signal launches along a third line and second signal launches along a fourth line substantially parallel to the third line.

Abstract translation: 中平面具有连接第一差分连接器的接触端的第一侧和与第二差分连接器的接触端连接的第一侧相对的第二侧。 中平面包括从第一侧延伸到第二侧的多个通孔，其中通孔在第一侧上提供第一信号发射，而第二信号在第二侧上发射。 第一信号发射被设置成多行，每行具有沿着第一线的第一信号发射，并且第一信号沿着基本上平行于第一线的第二线发射。 第二信号发射被提供在多列中，每列具有沿着第三线的第二信号发射，而第二信号沿着基本上平行于第三线的第四线发射。

公开(公告)号：US20070132088A1

公开(公告)日：2007-06-14

申请号：US11580928

申请日：2006-10-16

Applicant: Takashi Kariya ,  Hironori Tanaka

Inventor： Takashi Kariya ,  Hironori Tanaka

IPC: H01L23/04

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/3011 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09827 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  H01L2224/05599

Abstract: A printed circuit board including a conductor portion, an insulating layer formed over the conductor portion, a thin-film capacitor formed over the insulating layer and including a first electrode, a second electrode and a high-dielectric layer interposed between the first electrode and the second electrode, and a via-hole conductor structure formed through the second electrode and insulating layer and electrically connecting the second electrode and the conductor portion. The via-hole conductor structure has a first portion in the second electrode and a second portion in the insulating layer. The first portion of the via-hole conductor structure has a truncated-cone shape tapering toward the conductor portion.

Abstract translation: 一种印刷电路板，包括导体部分，在导体部分上形成的绝缘层，形成在绝缘层之上的薄膜电容器，并且包括第一电极，第二电极和介于第一电极和第二电极之间的高电介质层 第二电极和通过第二电极和绝缘层形成的通孔导体结构，并且电连接第二电极和导体部分。 通孔导体结构在第二电极中具有第一部分，在绝缘层中具有第二部分。 通孔导体结构的第一部分具有朝向导体部分逐渐变细的截锥形。

公开(公告)号：US07227268B2

公开(公告)日：2007-06-05

申请号：US10977263

申请日：2004-10-29

Applicant: Chi Shih Chang ,  William T. Chen ,  Ajit Trivedi

Inventor： Chi Shih Chang ,  William T. Chen ,  Ajit Trivedi

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/49816 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K3/3436 ,  H05K2201/09718 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/0401

Abstract: The present invention discloses techniques that improve the reliability of a flip packages that uses underfill encapsulation. One embodiment of the present invention describes a method and apparatus of packaging a flip chip by relocating the neutral plane of the package substrate away from its mid-plane. Another embodiment of the present invention describes a method and apparatus of arranging the layers of a laminate for use in PBGA packaging that arranges the layers of the laminate according to the stiffness of each layer. Another embodiment of the present invention describes a method and apparatus of packaging a flip chip that uses one or more redundant interconnections at the bottom of the package substrate where the redundant interconnections are within the shadow of the IC chip.

Abstract translation: 本发明公开了提高使用底部填充封装的翻盖封装的可靠性的技术。 本发明的一个实施例描述了一种通过将封装衬底的中性平面远离其中间平面重新定位来封装倒装芯片的方法和装置。 本发明的另一个实施例描述了一种将层压板的层布置在用于PBGA封装中的方法和装置，其根据每层的刚度来布置层压板的层。 本发明的另一个实施例描述了一种在封装衬底的底部使用一个或多个冗余互连的倒装芯片的封装方法和装置，其中冗余互连在IC芯片的阴影之内。

公开(公告)号：US20070075405A1

公开(公告)日：2007-04-05

申请号：US11239952

申请日：2005-09-30

Applicant: Xiaoning Ye

Inventor： Xiaoning Ye

IPC: H01L23/495

CPC classification number: H01L23/49827 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/645 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/15311 ,  H05K1/0251 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/093 ,  H05K2201/0969 ,  H05K2201/09718 ,  H05K2201/09727

Abstract: A system may include a conductive plane defining a non-conductive antipad area and a second non-conductive area extending from the antipad area in at least a first direction, a dielectric plane coupled to the conductive plane, a conductive via passing through the dielectric plane and the antipad area, a conductive pad connected to an end of the conductive via, and a conductive trace coupled to the dielectric plane and connected to the conductive pad, the conductive trace extending from the conductive pad in the first direction.

Abstract translation: 系统可以包括限定非导电止动区域的导电平面和在至少第一方向上从止血区域延伸的第二非导电区域，耦合到导电平面的电介质平面，穿过电介质平面的导电通孔 并且所述反面区域，连接到所述导电通孔的端部的导电焊盘以及耦合到所述电介质平面并连接到所述导电焊盘的导电迹线，所述导电迹线从所述导电焊盘沿所述第一方向延伸。

公开(公告)号：US20070074905A1

公开(公告)日：2007-04-05

申请号：US11392003

申请日：2006-03-29

Applicant: Yu-Hsu Lin ,  Shang-Tsang Yeh ,  Chuan-Bing Li

Inventor： Yu-Hsu Lin ,  Shang-Tsang Yeh ,  Chuan-Bing Li

IPC: H05K1/11 ,  H01R12/04

CPC classification number: H05K1/116 ,  G06F17/5068 ,  H05K1/0237 ,  H05K3/0005 ,  H05K3/0047 ,  H05K3/429 ,  H05K2201/09718 ,  H05K2203/163

Abstract: A method is for controlling an impedance of a via of a printed circuit board. The Via is connected with a trace and includes a drill hole, a pad and an anti-pad. The method includes steps of: building a math model; testing whether an impedance of the via matching with an impedance of the trace; analyzing the impedance of the via if passing the testing; and adjusting parameters of the pad, the anti-pad, and the drill hole if fails testing, and returning to the simulating step, till impedance matching achieved. The method which can efficiently keep signals integrality and increase signal transmission speed.

Abstract translation: 一种用于控制印刷电路板的通孔的阻抗的方法。 通道与轨迹连接，并包括一个钻孔，一个垫和一个防磨垫。 该方法包括以下步骤：构建数学模型; 测试通孔的阻抗是否匹配跟踪的阻抗; 通过测试分析通孔的阻抗; 并且如果测试失败，则调整焊盘，防焊盘和钻孔的参数，并返回到模拟步骤，直到达到阻抗匹配。 可有效保持信号完整性，提高信号传输速度的方法。

公开(公告)号：US07193838B2

公开(公告)日：2007-03-20

申请号：US10744695

申请日：2003-12-23

Applicant: Gregory J. Dunn ,  Remy J. Chilini ,  Robert T. Croswell ,  Timothy B. Dean ,  Claudia V. Gamboa ,  Jovica Savic

Inventor： Gregory J. Dunn ,  Remy J. Chilini ,  Robert T. Croswell ,  Timothy B. Dean ,  Claudia V. Gamboa ,  Jovica Savic

IPC: H01G4/30

CPC classification number: H05K1/162 ,  H05K3/025 ,  H05K3/429 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718

Abstract: A dielectric circuit board foil (400, 600) includes a conductive metal foil layer (210, 660), a crystallized dielectric oxide layer (405, 655) disposed adjacent a first surface of the conductive metal foil layer, a lanthanum nickelate layer (414, 664) disposed on the crystallized dielectric oxide layer, and an electrode layer (415, 665) that is substantially made of one or more base metals disposed on the lanthanum nickelate layer. The foil (400, 600) may be adhered to a printed circuit board sub-structure (700) and used to economically fabricate a plurality of embedded capacitors, including isolated capacitors of large capacitive density (>1000 pf/mm2).

Abstract translation: 电介质电路板箔（400,600）包括导电金属箔层（210,660），邻近导电金属箔层的第一表面设置的结晶介电氧化物层（405,655），镍酸镧层（414） ，664）和基本上由设置在镍酸镧层上的一种或多种贱金属制成的电极层（415,665）。 箔（400,600）可以粘附到印刷电路板子结构（700）上，并用于经济地制造多个嵌入式电容器，包括具有大电容密度（> 1000pf / mm 2）的隔离电容器， / SUP>）。

公开(公告)号：US20070000691A1

公开(公告)日：2007-01-04

申请号：US11478922

申请日：2006-06-30

Applicant: Yu-Hsu Lin ,  Shang-Tsang Yeh ,  Chao-Chen Huang ,  Chuan-Bing Li

Inventor： Yu-Hsu Lin ,  Shang-Tsang Yeh ,  Chao-Chen Huang ,  Chuan-Bing Li

IPC: H05K1/11

CPC classification number: H05K1/116 ,  H05K1/0216 ,  H05K3/429 ,  H05K2201/0352 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09718 ,  Y10T29/49165

Abstract: A printed circuit board (PCB) having vias for reducing reflections of input signals includes a first signal layer, a second signal layer, one via, an input signal line arranged on the first signal layer, and an output signal line arranged on the second signal layer. The via further includes a drill hole, a first pad, and a second pad. The first pad is electrically connected with the input signal line, and the second pad is electrically connected with the output signal line. An outer diameter of the first pad is smaller than an outer diameter of the second pad.

Abstract translation: 具有用于减少输入信号的反射的通孔的印刷电路板（PCB）包括第一信号层，第二信号层，一个通孔，布置在第一信号层上的输入信号线和布置在第二信号上的输出信号线 层。 通孔还包括钻孔，第一垫和第二垫。 第一焊盘与输入信号线电连接，第二焊盘与输出信号线电连接。 第一垫的外径小于第二垫的外径。

公开(公告)号：US07141742B2

公开(公告)日：2006-11-28

申请号：US10621925

申请日：2003-07-17

Applicant: Andew Harvey Barr ,  Dale John Shidla ,  Robert William Dobbs

Inventor： Andew Harvey Barr ,  Dale John Shidla ,  Robert William Dobbs

IPC: H01R12/04 ,  H05K1/00 ,  H05K3/36 ,  H01K3/10

CPC classification number: H05K1/0251 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/0373 ,  H05K2201/09245 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09681 ,  H05K2201/09718 ,  H05K2201/09781 ,  Y10T29/49126 ,  Y10T29/49165

Abstract: A printed circuit board includes a first conductive plane and a second conductive plane substantially parallel to the first conductive plane. The printed circuit board includes a via signal barrel transecting the first and second conductive planes and a first anti-pad positioned between the first conductive plane and the via signal barrel. The first anti-pad has a first voided area. The printed circuit board includes a second anti-pad positioned between the second conductive plane and the via signal barrel. The second anti-pad has a second voided area. The first voided area does not completely overlap the second voided area.

Abstract translation: 印刷电路板包括基本上平行于第一导电平面的第一导电平面和第二导电平面。 印刷电路板包括横穿第一和第二导电平面的通孔信号筒和位于第一导电平面和通孔信号筒之间的第一防焊盘。 第一个防磨垫具有第一个无效区域。 印刷电路板包括位于第二导电平面和通孔信号筒之间的第二防焊垫。 第二个防磨垫具有第二个无效区域。 第一排空区域不完全与第二空隙区域重叠。

公开(公告)号：US07124502B2

公开(公告)日：2006-10-24

申请号：US10917553

申请日：2004-08-11

Applicant: Joel R. Goergen

Inventor： Joel R. Goergen

IPC: H01K3/22

CPC classification number: H05K3/4688 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/382 ,  H05K3/429 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09354 ,  H05K2201/09381 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2203/061 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49163 ,  Y10T29/49165

Abstract: The disclosed board fabrication techniques and design features enable the construction of a reliable, high-layer-count, and economical backplane for routers and the like that require a large number of signaling paths across the backplane at speeds of 2.5 Gbps or greater, as well as distribution of significant amounts of power to router components. The disclosed techniques and features allow relatively thick (e.g., three- or four-ounce copper) power distribution planes to be combined with large numbers of high-speed signaling layers in a common backplane. Using traditional techniques, such a construction would not be possible because of the number of layers required and the thickness of the power distribution layers. The disclosed embodiments use novel layer arrangements, material selection, processing techniques, and panel features to produce the desired high-speed layers and low-noise high-power distribution layers in a single mechanically stable board.

公开(公告)号：US20060199390A1

公开(公告)日：2006-09-07

申请号：US11369448

申请日：2006-03-06

Applicant: George Dudnikov ,  Franz Gisin

Inventor： George Dudnikov ,  Franz Gisin

IPC: H01L21/311 ,  H01L23/48

CPC classification number: H05K3/429 ,  H05K1/0257 ,  H05K1/0259 ,  H05K1/116 ,  H05K1/167 ,  H05K3/184 ,  H05K3/422 ,  H05K2201/0187 ,  H05K2201/0738 ,  H05K2201/096 ,  H05K2201/09645 ,  H05K2201/09718 ,  H05K2201/09881 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Systems and methods for simultaneously partitioning a plurality of via structures into electrically isolated portions by using plating resist within a PCB stackup are disclosed. Such via structures are made by selectively depositing plating resist in one or more locations in a sub-composite structure. A plurality of sub-composite structures with plating resist deposited in varying locations are laminated to form a PCB stackup of a desired PCB design. Through-holes are drilled through the PCB stackup through conductive layers, dielelectric layers and through the plating resist. Thus, the PCB panel has multiple through-holes that can then be plated simultaneously by placing the PCB panel into a seed bath, followed by immersion in an electroless copper bath. Such partitioned vias increase wiring density and limit stub formation in via structures. Such partitioned vias allow a plurality of electrical signals to traverse each electrically isolated portion without interference from each other.

Abstract translation: 公开了通过在PCB堆叠中使用电镀抗蚀剂将多个通孔结构同时分隔成电隔离部分的系统和方法。 通过在子复合结构中的一个或多个位置选择性地沉积电镀抗蚀剂来制造这种通孔结构。 具有在不同位置沉积的电镀抗蚀剂的多个亚复合结构层压以形成期望的PCB设计的PCB堆叠。 通过导电层，电介质层和电镀抗蚀剂在PCB堆叠中钻出通孔。 因此，PCB面板具有多个通孔，然后可以通过将PCB面板放置在种子池中，然后浸入无电解铜浴中而同时进行电镀。 这种分隔的通孔增加布线密度并限制通孔结构中的短截线形成。 这种分隔的通孔允许多个电信号穿过每个电隔离部分而没有彼此的干扰。